CN111081677A - Semiconductor device and its manufacturing method and testing method - Google Patents
Semiconductor device and its manufacturing method and testing method Download PDFInfo
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- CN111081677A CN111081677A CN201811224706.0A CN201811224706A CN111081677A CN 111081677 A CN111081677 A CN 111081677A CN 201811224706 A CN201811224706 A CN 201811224706A CN 111081677 A CN111081677 A CN 111081677A
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to the technical field of semiconductors, and provides a semiconductor device, and a manufacturing method and a testing method of the semiconductor device. The semiconductor device may include a wafer, a scribe lane, and a plurality of clock doubling circuits; the scribing channels are vertically distributed to divide the wafer into a plurality of chips; the multiple clock frequency multiplier circuits are arranged in the scribing channel, and the output ends of the clock frequency multiplier circuits are connected with the chip. The high-frequency clock with the frequency consistent with the clock frequency of the chip can be provided, and the performance, the power consumption and the area of the chip are not influenced; and the wafer level test scheme design of the chip is simplified.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a method for manufacturing the semiconductor device, and a method for testing the semiconductor device.
Background
After the chips are produced, the electrical characteristics of the chips on the wafer need to be tested to see whether the chips work normally and meet the design requirements.
In the related art, the Test is generally performed using Automatic Test Equipment (ATE). However, in the related art, the upper limit of the clock frequency of the automatic test equipment often fails to reach the working clock frequency of the chip, so that the automatic test equipment cannot effectively test die (single chip) on the wafer.
Therefore, it is necessary to design a new semiconductor device, a manufacturing method of the semiconductor device, and a testing method of the semiconductor device.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiency that the automatic test equipment in the prior art cannot effectively test die (single chip) in a wafer due to a low clock frequency, and provides a semiconductor device, a method for manufacturing the semiconductor device, and a method for testing the semiconductor device, which can generate a high-frequency clock signal to effectively measure the die.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
According to an aspect of the present invention, a semiconductor device includes:
a wafer;
the scribing channels are vertically distributed to divide the wafer into a plurality of chips;
and the clock frequency doubling circuit is arranged in the scribing channel, and the output end of the clock frequency doubling circuit is connected with the chip.
In an exemplary embodiment of the disclosure, a frequency of a clock signal of the clock frequency doubling circuit is greater than or equal to a frequency of a clock signal when the chip operates.
In an exemplary embodiment of the present disclosure, the clock doubling circuit includes a nor gate circuit or a phase locked loop.
In an exemplary embodiment of the present disclosure, the chip includes a DRAM chip, a NAND chip, or a NOR chip.
According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:
providing a wafer;
arranging a plurality of scribing channels on the wafer, wherein the scribing channels are vertically distributed to divide the wafer into a plurality of chips;
and forming a clock frequency doubling circuit in the scribing channel, wherein the output end of the clock frequency doubling circuit is connected with the chip.
In an exemplary embodiment of the disclosure, a frequency of a clock signal of the clock frequency doubling circuit is greater than or equal to a frequency of a clock signal when the chip operates.
In an exemplary embodiment of the present disclosure, the clock doubling circuit includes a nor gate circuit or a phase locked loop.
In an exemplary embodiment of the present disclosure, the chip includes a DRAM chip, a NAND chip, or a NOR chip.
According to an aspect of the present disclosure, there is provided a method of testing a semiconductor device, for testing the semiconductor device of any one of the above, comprising:
and connecting the test equipment to the input end of the clock frequency doubling circuit, and connecting the output end of the frequency doubling circuit to at least one chip to test the chip.
In an exemplary embodiment of the present disclosure, the test equipment includes an integrated circuit automatic test machine.
According to the technical scheme, the invention has at least one of the following advantages and positive effects:
in the semiconductor device, the manufacturing method of the semiconductor device and the testing method of the semiconductor device of the invention, the scribing channels are mutually and vertically distributed to divide the wafer into a plurality of chips; and a plurality of clock frequency doubling circuits are arranged in the scribing channel, and the output ends of the clock frequency doubling circuits are connected with the chip. On one hand, the clock frequency multiplier circuit can provide a high-frequency clock with the frequency consistent with the clock frequency of the chip, and meanwhile, the performance, the power consumption and the area of the chip are not lost; on the other hand, the clock frequency doubling circuit is arranged in the scribing channel, so that the design of a chip test scheme can be simplified.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 is a schematic view of a wafer structure;
FIG. 2 is a schematic view of a partially enlarged structure of a semiconductor device of the present invention;
FIG. 3 is a schematic flow chart of a method of manufacturing a semiconductor device of the present invention;
the reference numerals of the main elements in the figures are explained as follows:
1. a wafer; 2. a chip; 3. an automatic tester for integrated circuits; 4. a clock frequency multiplier circuit; 5. scribing a street; 6. scribing the street edges.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The present invention firstly provides a semiconductor device, as shown in fig. 2, the semiconductor device may include a wafer 1, a scribe lane and a plurality of clock frequency doubling circuits 4; the scribing channels 5 are vertically distributed to divide the wafer 1 into a plurality of chips; the clock frequency multiplier circuits 4 are arranged in the scribing channel 5, and the output ends of the clock frequency multiplier circuits are connected with the chip 2.
In the present exemplary embodiment, referring to fig. 1 and 2, a wafer 1 may include a plurality of chips 2; after the wafer 1 is produced, the working electrical characteristics of the wafer 1 need to be tested to see whether the wafer works normally, so that the design requirements are met. After the test, the wafer 1 needs to be cut, so a plurality of scribe lanes 5 are provided between the plurality of chips 2, and a scribe lane 5 is provided between any two adjacent chips 2. A clock frequency multiplier circuit 4 is arranged in the scribing channels 5 to change the frequency of the clock signal and generate a high-frequency clock signal, so that the test effect is achieved.
The type of the chip 2 may be a DRAM (Dynamic Random Access Memory) chip, a NAND chip, or a NOR chip, or may be other types of chips, which is not limited in this embodiment.
In this exemplary embodiment, the clock frequency doubling circuit 4 may be disposed in any scribe lane 5 that is close to the chip 2 to be tested, and only one clock frequency doubling circuit 4 may be disposed in one scribe lane 5, or a plurality of clock frequency doubling circuits 4 may be disposed in the scribe lane 5, which is not specifically limited in this embodiment.
In the present exemplary embodiment, each clock multiplier circuit 4 is connected to one chip 2 or a plurality of chips 2, i.e., each clock multiplier circuit 4 detects one chip 2 or a plurality of chips 2.
In the present exemplary embodiment, referring to a schematic diagram of a partially enlarged structure of the semiconductor device of the present invention shown in fig. 2, a clock frequency doubling circuit 4 is provided in a dicing street 5; automatic Test Equipment (ATE) is arranged outside the wafer 1 and electrically connected with the clock frequency multiplier circuit 4, and the clock frequency multiplier circuit 4 is connected with the chip 2. The clock pulse signal of the automatic test equipment is transmitted to the clock frequency doubling circuit 4, and the chip 2 is tested after the frequency of the clock pulse signal is changed by the clock frequency doubling circuit 4. After the wafer 1 is tested, the wafer 1 is cut along the scribing way edge 6, the clock frequency doubling circuit 4 is cut off, so that the clock frequency doubling circuit 4 does not occupy the area of the chip 2, the chip 2 is not damaged, and meanwhile, the test effect can be well achieved.
In the present exemplary embodiment, the frequency of the clock signal of the clock multiplier circuit 4 is greater than or equal to the frequency of the clock signal when the chip 2 operates, so that the chip can be accurately tested when the chip runs at full speed.
In the present exemplary embodiment, the clock frequency multiplier circuit 4 may be a phase-locked loop or a nor gate circuit as long as the frequency multiplication function is achieved, and is not particularly limited in the present exemplary embodiment.
Further, the present invention also provides a method for manufacturing the semiconductor device; referring to fig. 3, the preparation method may include:
in step S110, a wafer is provided.
Step S120, arranging a plurality of scribing lanes on the wafer, wherein the scribing lanes are vertically distributed to divide the wafer into a plurality of chips; and forming a clock frequency doubling circuit in the scribing channel, wherein the output end of the clock frequency doubling circuit is connected with the chip.
The respective steps of the manufacturing method of the semiconductor device will be described in detail below.
In step S110, a wafer is provided.
In the present exemplary embodiment, a wafer is provided, and a plurality of scribe lines are disposed on the wafer, and the scribe lines are distributed perpendicular to each other to divide the wafer into a plurality of chips; after the wafer 1 is produced, the working electrical characteristics of the wafer 1 need to be tested to see whether the wafer works normally or not, the wafer 1 needs to be cut after the test, and therefore a plurality of scribing channels 5 are arranged between a plurality of chips 2, and the scribing channels 5 are arranged between any two adjacent chips 2.
The type of the chip may be a DRAM (Dynamic Random Access Memory) chip, a NAND chip, or a NOR chip, or may be other types of chips, which is not specifically limited in this embodiment.
In step S120, a plurality of scribe lines are disposed on the wafer, and the scribe lines are vertically distributed to divide the wafer into a plurality of chips; and forming a clock frequency doubling circuit in the scribing channel, wherein the output end of the clock frequency doubling circuit is connected with the chip.
In the present exemplary embodiment, referring to fig. 2, a clock frequency doubling circuit 4 is disposed in the scribe lane 5 to change the frequency of the test operating clock, so as to generate a high frequency clock signal, thereby achieving the test effect. The clock frequency multiplier circuit 4 is arranged in the scribing channel 5; automatic Test Equipment (ATE) is arranged outside the wafer 1 and connected with the clock frequency multiplier circuit 4, and the clock frequency multiplier circuit 4 is connected with the chip 2. The clock signal of the automatic test equipment is transmitted to the clock frequency doubling circuit 4, and the chip 2 is tested after the frequency of the clock signal is changed by the clock frequency doubling circuit 4.
Referring to fig. 1 and 2, after the wafer 1 is tested, the wafer 1 is cut along the edge of the scribe line, and the clock frequency doubling circuit 4 is cut together, so that the clock frequency doubling circuit 4 does not occupy the area of the chip 2 and does not damage the chip 2; meanwhile, the testing effect can be well achieved.
In an exemplary embodiment, referring to fig. 2, the clock doubling circuit 4 may be a phase-locked loop, an input clock of the phase-locked loop may be provided by the automatic test equipment, and an output clock of the phase-locked loop may reach an operating clock required by the chip, even though the clock frequency of the clock doubling circuit 4 is adapted to the clock frequency of the chip 2. In another exemplary embodiment, the clock frequency doubling circuit 4 may also be a nor gate circuit as long as the frequency doubling effect can be achieved, and the kind of the clock frequency doubling circuit is not particularly limited in this exemplary embodiment.
In one example embodiment. The formation of the scribe lines 5 and the formation of the clock doubling circuit 4 on the wafer may be performed simultaneously, or in another exemplary embodiment, the scribe lines 5 may be formed first, and then the clock doubling circuit 4 may be formed in the scribe lines 5. The present embodiment is not particularly limited.
Still further, the present invention also provides a semiconductor test method for testing the semiconductor device described above, which may include connecting a test device to the clock doubling circuit 4 for testing.
In the present exemplary embodiment, the used test equipment is an automatic integrated circuit tester 3, the automatic integrated circuit tester is connected to the clock frequency multiplier circuit 4, the clock frequency multiplier circuit 4 is connected to the chip 2 to be tested, and the clock signal of the automatic integrated circuit tester 3 changes the frequency of the clock pulse signal thereof through the clock frequency multiplier circuit 4, so that the frequency of the clock signal satisfies the frequency required by the chip 2 to be tested.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to utilize the invention.
Claims (10)
1. A semiconductor device, comprising:
a wafer;
the scribing channels are vertically distributed to divide the wafer into a plurality of chips;
and the clock frequency doubling circuit is arranged in the scribing channel, and the output end of the clock frequency doubling circuit is connected with the chip.
2. The semiconductor device according to claim 1, wherein a frequency of a clock signal of the clock doubling circuit is greater than or equal to a frequency of a clock signal when the chip operates.
3. The semiconductor device of claim 1, wherein the clock doubling circuit comprises a nor gate or a phase-locked loop.
4. The semiconductor device according to claim 1, wherein the chip comprises a DRAM chip, a NAND chip, or a NOR chip.
5. A method of manufacturing a semiconductor device, comprising:
providing a wafer;
arranging a plurality of scribing channels on the wafer, wherein the scribing channels are vertically distributed to divide the wafer into a plurality of chips;
and forming a clock frequency doubling circuit in the scribing channel, wherein the output end of the clock frequency doubling circuit is connected with the chip.
6. The method according to claim 5, wherein a frequency of a clock signal of the clock frequency doubling circuit is greater than or equal to a frequency of a clock signal of the chip during operation.
7. The method according to claim 5, wherein the clock multiplier circuit comprises an NOR gate circuit or a phase-locked loop.
8. The method for manufacturing a semiconductor device according to claim 5, wherein the chip comprises a DRAM chip, a NAND chip, or a NOR chip.
9. A method for testing a semiconductor device according to any one of claims 1 to 4, comprising:
and connecting the test equipment to the input end of the clock frequency doubling circuit, and connecting the output end of the frequency doubling circuit to at least one chip to test the chip.
10. The method for testing a semiconductor device according to claim 9, wherein the test apparatus comprises an automatic integrated circuit tester.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811224706.0A CN111081677A (en) | 2018-10-19 | 2018-10-19 | Semiconductor device and its manufacturing method and testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811224706.0A CN111081677A (en) | 2018-10-19 | 2018-10-19 | Semiconductor device and its manufacturing method and testing method |
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| Publication Number | Publication Date |
|---|---|
| CN111081677A true CN111081677A (en) | 2020-04-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811224706.0A Pending CN111081677A (en) | 2018-10-19 | 2018-10-19 | Semiconductor device and its manufacturing method and testing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111798898A (en) * | 2019-04-08 | 2020-10-20 | 长鑫存储技术有限公司 | DRAM chip and parameter testing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1190255A (en) * | 1997-02-04 | 1998-08-12 | 摩托罗拉公司 | Method and apparatus for performing operative testing on integrated circuit |
| JPH11204597A (en) * | 1998-01-19 | 1999-07-30 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing method and semiconductor wafer |
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2018
- 2018-10-19 CN CN201811224706.0A patent/CN111081677A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1190255A (en) * | 1997-02-04 | 1998-08-12 | 摩托罗拉公司 | Method and apparatus for performing operative testing on integrated circuit |
| JPH11204597A (en) * | 1998-01-19 | 1999-07-30 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing method and semiconductor wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111798898A (en) * | 2019-04-08 | 2020-10-20 | 长鑫存储技术有限公司 | DRAM chip and parameter testing method thereof |
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Application publication date: 20200428 |