CN111063733A - Preparation method and structure of grid oxide layer and preparation method of grid - Google Patents
Preparation method and structure of grid oxide layer and preparation method of grid Download PDFInfo
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- CN111063733A CN111063733A CN201811207099.7A CN201811207099A CN111063733A CN 111063733 A CN111063733 A CN 111063733A CN 201811207099 A CN201811207099 A CN 201811207099A CN 111063733 A CN111063733 A CN 111063733A
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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Abstract
本申请涉及半导体器件制造领域，公开了一种栅极氧化层制备方法及结构、一种栅极制备方法及结构，栅极氧化层制备方法包括：1)提供一半导体衬底，半导体衬底内形成有浅槽隔离结构，在半导体衬底上形成有掩膜层，掩膜层具有第一刻蚀窗口，第一刻蚀窗口定义栅极沟槽结构的位置和形状；2)通过第一刻蚀窗口在半导体衬底内形成栅极沟槽结构，栅极沟槽结构延伸穿过半导体衬底的多个有源区，或栅极沟槽结构延伸穿过半导体衬底的多个有源区以及有源区之间的浅槽隔离结构；3)以沉积方式在栅极沟槽结构的底部及侧壁形成栅极氧化层前体层；4)对半导体衬底进行氧化，通过氧化填补栅极氧化层前体层的孔隙，以将栅极氧化层前体层转换形成栅极氧化层。
The present application relates to the field of semiconductor device manufacturing, and discloses a method and structure for preparing a gate oxide layer, and a method and structure for preparing a gate. The method for preparing a gate oxide layer comprises: 1) providing a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, and a mask layer is formed on the semiconductor substrate, wherein the mask layer has a first etching window, and the first etching window defines the position and shape of a gate trench structure; 2) forming a gate trench structure in the semiconductor substrate through the first etching window, wherein the gate trench structure extends through a plurality of active regions of the semiconductor substrate, or the gate trench structure extends through a plurality of active regions of the semiconductor substrate and a shallow trench isolation structure between the active regions; 3) forming a gate oxide layer precursor layer at the bottom and sidewalls of the gate trench structure by deposition; and 4) oxidizing the semiconductor substrate, and filling the pores of the gate oxide layer precursor layer by oxidation, so as to convert the gate oxide layer precursor layer into a gate oxide layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor device manufacturing, and in particular, to a gate oxide layer preparation method, a gate oxide layer structure, and a gate preparation method.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, the memory cells are arranged in an array form, and each memory cell is electrically connected with each other through a word line and a bit line. As electronic products are increasingly developed to be light, thin, short and small, the design of DRAM devices must meet the requirements of high integration and high density and the trend of miniaturization, and in order to increase the integration of DRAM devices to increase the operation speed of the devices and meet the demands of consumers for miniaturized electronic devices, the embedded gate DRAM devices have been developed in recent years to meet the above-mentioned demands.
In the existing grid electrode process, a grid electrode oxidation layer is generally generated by adopting an on-site water vapor generation oxidation method or a low-pressure free radical oxidation method. The thickness of the generated gate oxide layer is greatly influenced by the crystal plane direction, the thickness of the gate oxide layer in the gate groove structure is not uniform at different positions, electrons easily tunnel at the thinner position, so that the working voltage is reduced, and the gate cannot be normally opened.
Disclosure of Invention
The purpose of the present application is to provide a gate oxide layer preparation method, a gate oxide layer structure, a gate preparation method, and a gate structure, which can manufacture a gate oxide layer with good uniformity, avoid electron tunneling easily occurring due to an excessively thin gate oxide layer at the bottom of a gate trench structure, and effectively ensure normal operation of the gate structure.
In order to achieve the above object, in a first aspect of the present application, there is provided a gate oxide layer preparation method, including: 1) providing a semiconductor substrate, wherein a shallow groove isolation structure is formed in the semiconductor substrate, a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the position and the shape of a grid groove structure; 2) forming the gate trench structure in the semiconductor substrate through the first etch window, the gate trench structure extending through a plurality of active regions of the semiconductor substrate; or forming the gate trench structure in the semiconductor substrate through the first etching window, wherein the gate trench structure extends through a plurality of active regions of the semiconductor substrate and the shallow trench isolation structures between the active regions; 3) forming a gate oxide layer precursor layer on the bottom and the side wall of the gate trench structure in a deposition manner; 4) and oxidizing the semiconductor substrate, and filling the pores of the grid oxide layer precursor layer through oxidation so as to convert the grid oxide layer precursor layer into a grid oxide layer.
Optionally, a surface protection layer is formed on the semiconductor substrate, the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
Optionally, the thickness of the gate oxide layer precursor layer in step 3) is 1nm to 9nm, and a thickness ratio of the gate oxide layer precursor layer in the crystal plane direction of the bottom and the sidewall of the gate trench structure is less than 1.05.
Optionally, the gas phase precursor used in step 3) comprises a silicon source gas.
Optionally, the step 3) includes forming the gate oxide layer precursor layer by an atomic layer deposition method, wherein a process temperature is 300-600 ℃, and a process time is 5-60 min.
Optionally, the gas used in step 4) comprises oxygen (O)2) Hydrogen (H)2) Superoxide (O)3) And water vapor (H)2O), and the method for forming the grid oxide layer in the step 4) comprises at least one of in-situ steam generation oxidation and low-pressure free radical oxidation.
Optionally, the method for forming the gate oxide layer in step 4) is in-situ steam generation oxidation, wherein the process temperature is 1000-1300 ℃, the process time is 1-60 s, and the gas flow is 1-10 slm.
Optionally, the aspect ratio of the shallow trench isolation structure is 10 to 30, and the aspect ratio of the gate trench structure is 5 to 20.
The second aspect of the present application provides a method for manufacturing a gate, including: preparing a grid oxide layer by using the preparation method of the grid oxide layer provided by the application; a gate wire is formed in the gate trench structure.
A third aspect of the present application provides a gate oxide structure, comprising: the semiconductor device comprises a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the position and the shape of a grid trench structure; a gate trench structure extending through a plurality of active regions of the semiconductor substrate; or a gate trench structure extending through a plurality of active regions of the semiconductor substrate and the shallow trench isolation structure between the active regions; and the grid oxide layer is positioned at the bottom and the side wall of the grid groove structure.
Optionally, the gate oxide layer structure further includes: and the surface protection layer is positioned between the mask layer and the semiconductor substrate and is provided with a second etching window corresponding to the first etching window.
Optionally, the aspect ratio of the shallow trench isolation structure is 10 to 30, and the aspect ratio of the gate trench structure is 5 to 20.
According to the preparation method of the grid oxide layer, the grid oxide layer precursor layer is formed at the bottom and on the side wall of the grid groove structure in a deposition mode, then the hole of the grid oxide layer precursor layer is filled in an oxidation mode, and the grid oxide layer precursor layer is converted to form the grid oxide layer.
Additional features and advantages of the present application will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIG. 1 is a flow chart of a method of fabricating a gate oxide layer according to one embodiment of the present application;
FIG. 2A is a top view of a semiconductor substrate prepared using a gate oxide layer preparation method according to one embodiment of the present application;
FIG. 2B is a cross-sectional view of a semiconductor substrate prepared using a gate oxide layer preparation method according to one embodiment of the present application;
FIG. 3 is a cross-sectional view of another semiconductor substrate prepared using a gate oxide layer preparation method according to one embodiment of the present application;
fig. 4A is a top view of the gate trench structure formed in step 2) of the gate oxide layer preparation method according to an embodiment of the present application;
fig. 4B is a cross-sectional view of the gate trench structure formed in step 2) of the gate oxide layer preparation method according to an embodiment of the present application;
FIG. 5A is a top view of a gate oxide precursor layer formed in step 3) of a gate oxide preparation method according to one embodiment of the present disclosure;
fig. 5B is a cross-sectional view of the gate oxide precursor layer formed in step 3) of the gate oxide preparation method according to one embodiment of the present application;
fig. 6A is a top view of the gate oxide layer formed in step 4) of the gate oxide layer preparation method according to one embodiment of the present disclosure;
fig. 6B is a cross-sectional view of the gate oxide layer formed in step 4) of the gate oxide layer preparation method according to one embodiment of the present application;
FIG. 7 is a schematic view of the gate oxide layer formed in step 4) of the gate oxide layer preparation method according to one embodiment of the present disclosure;
fig. 8A is a top view of a semiconductor substrate prepared by a gate oxide layer preparation method according to another embodiment of the present application;
fig. 8B is a cross-sectional view of a semiconductor substrate prepared by a gate oxide layer preparation method according to another embodiment of the present application;
fig. 9 is a cross-sectional view of another semiconductor substrate fabricated using a gate oxide layer fabrication method according to another embodiment of the present application;
fig. 10A is a top view of a gate trench structure formed in step 2) of a gate oxide layer formation method according to another embodiment of the present disclosure;
fig. 10B is a cross-sectional view of the gate trench structure formed in step 2) of the gate oxide layer preparation method according to another embodiment of the present application;
fig. 11A is a top view of a gate oxide precursor layer formed in step 3) of a gate oxide preparation method according to another embodiment of the present application;
fig. 11B is a cross-sectional view of the gate oxide precursor layer formed in step 3) of the gate oxide preparation method according to another embodiment of the present application;
fig. 12A is a top view of the gate oxide layer formed in step 4) of the gate oxide layer preparation method according to another embodiment of the present application;
fig. 12B is a cross-sectional view of the gate oxide layer formed at step 4) of the gate oxide layer preparation method according to another embodiment of the present application;
fig. 13A is a cross-sectional view of a gate wire formed using a gate fabrication method according to an embodiment of the present application;
fig. 13B is a cross-sectional view of a gate wire formed using a gate fabrication method according to another embodiment of the present application;
FIG. 14A is a cross-sectional view of a gate oxide layer formed using a gate fabrication method according to one embodiment of the present application;
fig. 14B is a cross-sectional view of a gate oxide layer formed using a gate fabrication method according to another embodiment of the present application.
Description of the reference numerals
100 semiconductor substrate 110 shallow trench isolation structure
120 gate trench structure 130 gate oxide precursor layer
140 gate oxide layer 150 gate wire
200 mask layer 210 first etch window
300 surface protection layer 310 second etch window
Detailed Description
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present application, are given by way of illustration and explanation only, and are not intended to limit the present application.
In this application, the use of directional words such as "above/over, below/under, left/left, right/right" generally means up, down, left, right with reference to the drawings, unless stated to the contrary. "inner and outer" refer to the inner and outer contours of the respective component itself.
In the drawings, the shapes shown may be modified depending on manufacturing processes and/or tolerances. Accordingly, the exemplary embodiments of the present application are not limited to the specific shapes illustrated in the drawings, and may include shape changes caused during a manufacturing process. Furthermore, the different elements and regions in the drawings are only schematically shown, so that the application is not limited to the relative dimensions or distances shown in the drawings.
As shown in fig. 1, the present application provides a method for preparing a gate oxide layer, comprising the following steps:
1) providing a semiconductor substrate, wherein a shallow groove isolation structure is formed in the semiconductor substrate, a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the position and the shape of a grid groove structure;
2) forming the gate trench structure in the semiconductor substrate through the first etch window, the gate trench structure extending through a plurality of active regions of the semiconductor substrate; or forming the gate trench structure in the semiconductor substrate through the first etching window, wherein the gate trench structure extends through a plurality of active regions of the semiconductor substrate and the shallow trench isolation structures between the active regions;
3) forming a gate oxide layer precursor layer on the bottom and the side wall of the gate trench structure in a deposition manner;
4) and oxidizing the semiconductor substrate, and filling the pores of the grid oxide layer precursor layer through oxidation so as to convert the grid oxide layer precursor layer into a grid oxide layer.
The following describes a method for fabricating a gate oxide layer in detail with reference to the accompanying drawings.
Because the arrangement of the active regions is different, the gate trench structure of some products may pass through the shallow trench isolation structure, and the gate trench structure of other products may not pass through the shallow trench isolation structure, so the present application is described by the following two embodiments:
the first embodiment is as follows: the gate trench structure does not pass through the shallow trench isolation structure.
By adopting the gate oxide layer preparation method provided by the present application, step 1) is firstly executed, a semiconductor substrate 100 is provided, a shallow trench isolation structure 110 is formed in the semiconductor substrate 100, a mask layer 200 is formed on the semiconductor substrate 100, the mask layer 200 has a first etching window 210, the first etching window 210 defines the position and the shape of the gate trench structure 120, as shown in fig. 2A and 2B, and fig. 2B is a cross-sectional view of a dotted line portion in fig. 2A.
Specifically, the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
A mask layer 200 is formed on the semiconductor substrate 100, and the material of the mask layer 200 includes, but is not limited to, silicon nitride, silicon oxide, carbon, and other materials having a high selectivity with respect to the material of the semiconductor substrate 100. The mask layer 200 has a first etch window 210, the first etch window 210 defining the location and shape of the gate trench structure 120.
Optionally, a surface protection layer 300 is formed on the semiconductor substrate 100, the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, and the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 3.
Specifically, the surface protection layer 300 is used to protect the surface of the semiconductor substrate 100, and the material of the surface protection layer 300 includes, but is not limited to, silicon nitride, silicon oxide, carbon, and other materials having a high selectivity with the material of the semiconductor substrate 100 and the material of the mask layer 200. The surface protective layer 300 has a second etch window 310 corresponding to the first etch window 210.
Next, step 2) is performed, forming the gate trench structure 120 in the semiconductor substrate 100 through the first etching window 210, wherein the gate trench structure 120 extends through a plurality of active regions of the semiconductor substrate 100, as shown in fig. 4A and 4B, and fig. 4B is a cross-sectional view of a dotted line portion in fig. 4A.
Specifically, the semiconductor substrate 100 is deeply etched through the first etching window 210, and the gate trench structure 120 is formed in the semiconductor substrate 100, wherein the gate trench structure 120 extends through the plurality of active regions of the semiconductor substrate 100, and in this application, the semiconductor substrate 100 may be etched by using at least one of a dry etching process and a wet etching process to form the gate trench structure 120.
Continuing to perform step 3), a gate oxide precursor layer 130 is deposited on the bottom and sidewalls of the gate trench structure 120, as shown in fig. 5A and 5B, and fig. 5B is a cross-sectional view of the dotted line portion in fig. 5A.
Optionally, the step 3) includes forming the gate oxide Layer precursor Layer 130 by Atomic Layer Deposition (ALD) at a process temperature of 300-600 ℃ for a process time of 5-60 min.
Specifically, the gate oxide precursor layer 130 is prepared by an ALD method, and a gas phase precursor is introduced into the reaction apparatus in an alternating pulse manner, so that a gas-solid phase chemical adsorption reaction occurs on the surface of the gate trench structure 120 to form the gate oxide precursor layer 130. The process temperature for preparing the gate oxide layer precursor layer 130 is 300-600 ℃, and the process time is 5-60 min.
Optionally, the gas phase precursor used in step 3) comprises a silicon source gas.
Optionally, the thickness of the gate oxide layer precursor layer 130 in step 3) is 1nm to 9nm, and a thickness ratio of the gate oxide layer precursor layer 130 in the crystal plane direction of the bottom and the sidewall of the gate trench structure 120 is less than 1.05.
Specifically, the thickness of the gate oxide layer precursor layer 130 prepared in the present application is 1nm to 9nm, the ratio of the thicknesses of the gate oxide layer precursor layer 130 in the crystal plane directions of the bottom and the sidewall of the gate trench structure 120 is less than 1.05, and the thickness of the formed gate oxide layer precursor layer 130 at the bottom of the gate trench structure 120 is thinner.
Continuing to perform step 4), oxidizing the semiconductor substrate 100, and filling up the pores of the gate oxide precursor layer 130 by oxidation to convert the gate oxide precursor layer 130 into a gate oxide layer 140, as shown in fig. 6A, 6B and 7, where fig. 6B is a cross-sectional view of the dotted line in fig. 6A.
Specifically, the thickness of the gate oxide precursor layer 130 is greatly influenced by the crystal plane orientation, more pores are generated on the gate oxide precursor layer 130 formed at the bottom of the gate trench structure 120, and the thickness of the gate oxide precursor layer 130 at the bottom of the gate trench structure 120 is smaller than the thickness of the gate oxide precursor layer 130 at the sidewall of the gate trench structure 120. The thickness of the gate oxide layer precursor layer 130 at the bottom of the gate trench structure 120 can be increased by oxidation, and the pores of the gate oxide layer precursor layer 130 are filled by oxidation, so that residual impurities Si-O-H and Si-O-NH in the atomic layer deposition process are eliminated2The gate oxide precursor layer 130 is converted to form a gate oxide layer 140 of uniform thickness.
Optionally, the gas used in step 4) comprises oxygen (O)2) Hydrogen (H)2) Superoxide (O)3) And water vapor (H)2O), the method of forming the gate oxide layer 140 in step 4) includes at least one of in-situ steam Generation Oxidation (ISSG) and Low Pressure Radical Oxidation (LPRO).
Specifically, in the present application, the gate oxide layer 140 may be formed by at least one of ISSG and LPRO, which may be selected according to actual requirements, and the embodiments of the present application are not limited thereto.
Optionally, ISSG is used to form the gate oxide layer 140 in step 4), the process temperature is 1000-1300 ℃, the process time is 1-60 s, and the gas flow is 1-10 slm, as shown in fig. 7.
In particular, ISSG can form highly reactive oxygen, Si-O-H and Si-O-NH2Are converted into Si-O-Si to form the gate oxide layer 140 with a uniform thickness. The process temperature of ISSG is 1000-1300 ℃, the process time is 1-60 s, and the gas flow is 1-10 slm.
Optionally, the aspect ratio of the shallow trench isolation structure 110 is 10 to 30, and the aspect ratio of the gate trench structure 120 is 5 to 20.
Specifically, the shallow trench isolation structure 110 with the aspect ratio of 10-30 and the gate trench structure 120 with the aspect ratio of 5-20 can be prepared.
Example two: the gate trench structure passes through the shallow trench isolation structure.
By adopting the gate oxide layer preparation method provided by the present application, step 1) is firstly executed, a semiconductor substrate 100 is provided, a shallow trench isolation structure 110 is formed in the semiconductor substrate 100, a mask layer 200 is formed on the semiconductor substrate 100, the mask layer 200 has a first etching window 210, the first etching window 210 defines the position and the shape of the gate trench structure 120, as shown in fig. 8A and 8B, and fig. 8B is a cross-sectional view of a dotted line portion in fig. 8A.
Specifically, the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
A mask layer 200 is formed on the semiconductor substrate 100, and the material of the mask layer 200 includes, but is not limited to, silicon nitride, silicon oxide, carbon, and other materials having a high selectivity with respect to the material of the semiconductor substrate 100. The mask layer 200 has a first etch window 210, and the first etch window 210 may define a position and a shape of the gate trench structure 120.
Optionally, a surface protection layer 300 is formed on the semiconductor substrate 100, the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, and the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 9.
Specifically, the surface protection layer 300 is used to protect the surface of the semiconductor substrate 100, and the material of the surface protection layer 300 includes, but is not limited to, silicon nitride, silicon oxide, and carbon, which have a high selectivity with the material of the semiconductor substrate 100 and the mask layer 200. The surface protective layer 300 has a second etch window 310 corresponding to the first etch window 210.
Next, step 2) is performed, forming the gate trench structure 120 in the semiconductor substrate 100 through the first etching window 210, wherein the gate trench structure 120 extends through a plurality of active regions of the semiconductor substrate 100, as shown in fig. 10A and 10B, and fig. 10B is a cross-sectional view of a dotted line portion in fig. 10A.
Specifically, the semiconductor substrate 100 is deeply etched through the first etching window 210, and the gate trench structure 120 is formed in the semiconductor substrate 100, wherein the gate trench structure 120 extends through the plurality of active regions of the semiconductor substrate 100, and in this application, the semiconductor substrate 100 may be etched by using at least one of a dry etching process and a wet etching process to form the gate trench structure 120.
Continuing to perform step 3), a gate oxide precursor layer 130 is deposited on the bottom and sidewalls of the gate trench structure 120, as shown in fig. 11A and 11B, where fig. 11B is a cross-sectional view of the dotted line portion in fig. 11A.
Optionally, step 3) includes forming the gate oxide precursor layer 130 by ALD, wherein the process temperature is 300 ℃ to 600 ℃ and the process time is 5min to 60 min.
Specifically, the gate oxide precursor layer 130 is prepared by an ALD method, and a gas phase precursor is introduced into the reaction apparatus in an alternating pulse manner, so that a gas-solid phase chemical adsorption reaction occurs on the surface of the gate trench structure 120 to form the gate oxide precursor layer 130. The process temperature for preparing the gate oxide layer precursor layer 130 is 300-600 ℃, and the process time is 5-60 min.
Optionally, the gas phase precursor used in step 3) comprises a silicon source gas.
Optionally, the thickness of the gate oxide layer precursor layer 130 in step 3) is 1nm to 9nm, and a thickness ratio of the gate oxide layer precursor layer 130 in the crystal plane direction of the bottom and the sidewall of the gate trench structure 120 is less than 1.05.
Specifically, the thickness of the gate oxide layer precursor layer 130 prepared in the present application is 1nm to 9nm, the ratio of the thicknesses of the gate oxide layer precursor layer 130 in the crystal plane directions of the bottom and the sidewall of the gate trench structure 120 is less than 1.05, and the thickness of the formed gate oxide layer precursor layer 130 at the bottom of the gate trench structure 120 is thinner.
Continuing to perform step 4), oxidizing the semiconductor substrate 100, and filling up the pores of the gate oxide precursor layer 130 by oxidation to convert the gate oxide precursor layer 130 into a gate oxide layer 140, as shown in fig. 12A, 12B and 7, where fig. 12B is a cross-sectional view of the dotted line portion in fig. 12A.
Specifically, the thickness of the gate oxide precursor layer 130 is greatly influenced by the crystal plane orientation, more pores are generated on the gate oxide precursor layer 130 formed at the bottom of the gate trench structure 120, and the thickness of the gate oxide precursor layer 130 at the bottom of the gate trench structure 120 is smaller than the thickness of the gate oxide precursor layer 130 at the sidewall of the gate trench structure 120. The thickness of the gate oxide layer precursor layer 130 at the bottom of the gate trench structure 120 can be increased by oxidation, and the pores of the gate oxide layer precursor layer 130 are filled by oxidation, so that residual impurities Si-O-H and Si-O-NH in the atomic layer deposition process are eliminated2The gate oxide precursor layer 130 is converted to form a gate oxide layer 140 of uniform thickness.
Optionally, the gas used in step 4) comprises oxygen (O)2) Hydrogen (H)2) Superoxide (O)3) And water vapor (H)2O), the method of forming the gate oxide layer 140 in step 4) includes at least one of ISSG and LPRO.
Specifically, the gate oxide layer 140 may be formed by at least one of ISSG and LPRO, which may be selected according to actual requirements, and is not limited in this embodiment.
Optionally, ISSG is used to form the gate oxide layer 140 in step 4), the process temperature is 1000-1300 ℃, the process time is 1-60 s, and the gas flow is 1-10 slm, as shown in fig. 7.
In particular, ISSG can form highly reactive oxygen, Si-O-H and Si-O-NH2Are converted into Si-O-Si to form the gate oxide layer 140 with a uniform thickness. The process temperature of ISSG is 1000-1300 ℃, the process time is 1-60 s, and the gas flow is 1-10 slm.
Optionally, the aspect ratio of the shallow trench isolation structure 110 is 10 to 30, and the aspect ratio of the gate trench structure 120 is 5 to 20.
Specifically, the shallow trench isolation structure 110 with the aspect ratio of 10-30 and the gate trench structure 120 with the aspect ratio of 5-20 can be prepared in the present application.
By the method, the gate oxide layer with uniform thickness can be formed, the phenomenon that electron tunneling easily occurs due to the fact that the thickness of the gate oxide layer at the bottom of the gate groove structure is too thin is avoided, and normal work of the gate structure is effectively guaranteed.
In a second aspect, the present application provides a method for manufacturing a gate, including: preparing a gate oxide layer 140 by using the gate oxide layer preparation method provided by the application; a gate wire 150 is formed in the gate trench structure 120.
Specifically, referring to fig. 13A and 13B, fig. 13A is a cross-sectional view of the gate with the gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100, and fig. 13B is a cross-sectional view of the gate with the gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100 and the shallow trench isolation structure 110 between the active regions. The material of the gate wire 150 includes, but is not limited to, titanium and tungsten, and is not limited in this application.
As shown in fig. 14A and 14B, fig. 14A is a cross-sectional view of the gate trench structure 120 extending through the gate oxide layer of the plurality of active regions of the semiconductor substrate 100, and fig. 14B is a cross-sectional view of the gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100 and the gate oxide layer of the shallow trench isolation structure 110 between the active regions.
A third aspect of the present application provides a gate oxide structure, comprising: the semiconductor device comprises a semiconductor substrate 100, wherein a shallow trench isolation structure 110 is formed in the semiconductor substrate 100, a mask layer 200 is formed on the semiconductor substrate 100, the mask layer 200 is provided with a first etching window 210, and the first etching window 210 defines the position and the shape of a gate trench structure 120; a gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100, or a gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100 and the shallow trench isolation structure 110 between the active regions; a gate oxide layer 140 on the bottom and sidewalls of the gate trench structure 120.
Optionally, the gate oxide layer structure further includes: a surface protection layer 300 located between the mask layer 200 and the semiconductor substrate 100, wherein the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 6B and 12B.
Optionally, the aspect ratio of the shallow trench isolation structure 110 is 10 to 30, and the aspect ratio of the gate trench structure 120 is 5 to 20.
As shown in fig. 13A and 13B, fig. 13A is a cross-sectional view of the gate with the gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100, and fig. 13B is a cross-sectional view of the gate with the gate trench structure 120 extending through the plurality of active regions of the semiconductor substrate 100 and the shallow trench isolation structure 110 between the active regions.
It should be noted that, the steps of the gate oxide layer preparation method described in the above embodiments are all necessary steps for reflecting the technical solution of the present application and solving the technical problems of the present application as a whole, but are not limited to the above steps, and those skilled in the art can understand that other steps known in the semiconductor packaging process may also be included, and for conciseness and conciseness of the description of the present application, these conventional known steps are not described in detail in the present application, but should be regarded as belonging to the protection scope of the present application.
The preferred embodiments of the present application have been described in detail with reference to the accompanying drawings, however, the present application is not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the technical idea of the present application, and these simple modifications are all within the protection scope of the present application.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations are not described separately in this application.
In addition, any combination of the various embodiments of the present application is also possible, and the same should be considered as disclosed in the present application as long as it does not depart from the idea of the present application.
Claims (12)
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