CN111052581A - Control device for resonant type converter - Google Patents
Control device for resonant type converter Download PDFInfo
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- CN111052581A CN111052581A CN201980004095.5A CN201980004095A CN111052581A CN 111052581 A CN111052581 A CN 111052581A CN 201980004095 A CN201980004095 A CN 201980004095A CN 111052581 A CN111052581 A CN 111052581A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33571—Half-bridge at primary side of an isolation transformer
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/01—Resonant DC/DC converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
在以连接于功率因数校正电路的输出的大容量电容器的电压为输入的直流电压的谐振型转换器中，能够在可靠地防止谐振偏移的同时，不增加大容量电容器的容量而确保长的保持时间。控制IC(12)具备强制关断控制电路(22)，该强制关断控制电路(22)具有BO端子和IS端子，BO端子被输入将大容量电容器的电压进行分压而得到的电压，IS端子被输入将谐振电流进行分流并转换为电压而得到的谐振电流检测信号。在强制关断控制电路(22)中，在谐振电流检测信号低于用于判断谐振电流反转的阈值电压时输出强制关断信号(fto)，但使该阈值电压依赖于BO端子的电压而变化。由此，防止谐振偏移，并且能够确保长的保持时间。
In a resonant converter that uses the voltage of the bulk capacitor connected to the output of the power factor correction circuit as an input DC voltage, it is possible to reliably prevent resonance shifts, and to ensure a long time without increasing the capacity of the bulk capacitor. hold time. The control IC (12) includes a forced-off control circuit (22), the forced-off control circuit (22) has a BO terminal and an IS terminal, and the BO terminal is input with a voltage obtained by dividing the voltage of the bulk capacitor, IS A resonant current detection signal obtained by dividing the resonant current and converting it into a voltage is input to the terminal. The forced-off control circuit (22) outputs a forced-off signal (fto) when the resonant current detection signal is lower than a threshold voltage for judging resonant current reversal, but the threshold voltage is made to depend on the voltage of the BO terminal to vary Variety. Thereby, resonance shift is prevented, and a long holding time can be ensured.
Description
Technical Field
The present invention relates to a control device for a resonant converter, and more particularly to a control device for a resonant converter which is a current resonant DC-DC converter having a large-capacity capacitor as an output capacitor of a power factor correction circuit connected to an input thereof.
Background
A current resonance type DC-DC converter is suitable for high efficiency and thin profile, and is therefore widely used for liquid crystal televisions, AC-DC adapters, and the like. In this current resonance type DC-DC converter, a power factor correction circuit is used in combination to suppress a harmonic current generated by a switching operation to a certain limit value or less and improve a power factor. The power factor correction circuit generates a boosted intermediate DC voltage from an ac input voltage, and the DC-DC converter converts the intermediate DC voltage into a DC voltage of a predetermined value.
A large-capacity capacitor having a large capacity is provided between the power factor correction circuit and the DC-DC converter, an intermediate voltage generated by the power factor correction circuit is stored in the large-capacity capacitor, and the intermediate voltage stored in the large-capacity capacitor becomes an input voltage of the DC-DC converter. The DC-DC converter converts the input voltage and supplies the converted input voltage to a load.
Here, for example, if the ac input voltage is not supplied to the power factor correction circuit due to the power plug being erroneously removed from the outlet, the supply of energy from the power factor correction circuit to the large-capacity capacitor is stopped. In this case, the energy input to the DC-DC converter is only the energy stored in the large-capacity capacitor, and therefore, the intermediate voltage between the terminals of the large-capacity capacitor gradually decreases.
If the input voltage drops, the DC-DC converter may generate a resonance shift (resonance はずれ) phenomenon, and the switching element may be destroyed. That is, in a current resonance type DC-DC converter, a half-bridge circuit in which a high-side switching element and a low-side switching element are connected in series is used, and the current resonance circuit is driven by alternately turning on the high-side switching element and the low-side switching element. In a current resonance type DC-DC converter, if an input voltage drops, control is performed to lower the operating frequency of a switch in order to maintain a predetermined output voltage, and the switching cycle becomes longer. Therefore, there is a case where the on time of the switching element is too long, and resonance shift occurs in which the resonance current is inverted during the on time, and a large current flows in the subsequent switch. For example, when the high-side switching element is switched from on to off, the direction of the resonance current at the time of off in the normal operation is opposite to the forward direction of a body diode (a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) connected in reverse parallel to the high-side switching element). In other words, the switching element is turned off in a state where no current flows through the body diode. However, if the switching period becomes too long and the resonance current reverses during the on time of the switching element, a current flows in the body diode. When the on/off of the high-side switching device and the low-side switching device are reversed in a state where a current flows through the body diode, the reverse recovery operation of the high-side body diode is started, and a large current (through current) instantaneously flows between the power supply and the ground so that the reverse recovery current of the diode flows through the turned-on low-side switching device. If the current flowing at this time exceeds the rated value of the switching element, the switching element may be broken.
Therefore, in the DC-DC converter, the following control is performed: if the input voltage becomes low, the switching operation is stopped before the resonance shift occurs, and the switching element is protected (see, for example, patent documents 1 and 2).
According to the resonance shift prevention technique described in patent document 1, the resonance current is monitored, forced turn-off of the DC-DC converter is permitted if the resonance current exceeds a first threshold value, and thereafter, forced turn-off of the DC-DC converter is performed if the resonance current is lower than a second threshold value. Thus, the resonance shift of the DC-DC converter is reliably prevented before the resonance current is inverted.
Further, according to patent document 2, the resonance current and the resonance voltage are monitored, the polarity inversion of the resonance current is determined from the resonance voltage to allow the forced turn-off of the DC-DC converter, and thereafter, if the resonance current is lower than a predetermined current threshold value, the forced turn-off of the DC-DC converter is performed. Thus, the resonance shift of the DC-DC converter is reliably prevented before the resonance current is inverted.
In a DC-DC converter, it is desirable to be able to supply a direct-current voltage to a load for as long as possible when power supplied from a power factor correction circuit is lost. This is because a load such as a data processing apparatus needs a time called a retention time during which data backup is performed before shutdown when power is lost. In order to ensure the holding time, the intermediate voltage of the large-capacity capacitor is used to the lowest possible voltage, or the capacity of the large-capacity capacitor is increased.
Documents of the prior art
Patent document
Patent document 1: japanese patent No. 4386743
Patent document 2: japanese patent No. 5761206
Disclosure of Invention
Technical problem
In order to enable the DC-DC converter to use the intermediate voltage of the large-capacity capacitor to a voltage as low as possible, the threshold value of the resonance current for performing the forced turn-off may be set low. However, if the threshold of the resonance current for performing the forced turn-off is set low, the current change rate (dI/dt) of the resonance current becomes large when the input voltage is high, and therefore, it becomes difficult to prevent the resonance shift. On the other hand, if the threshold of the resonance current for performing the forced turn-off is set high, the forced turn-off is performed while the input voltage is not decreased, and therefore, the holding time becomes short, and accordingly, the energy of the large-capacity capacitor becomes inefficiently used. That is, if the threshold value of the resonance current is set low, it is difficult to prevent resonance shift, and if the threshold value of the resonance current is set high, it is difficult to secure the holding time. Therefore, although it is preferable to increase the capacity of the large-capacity capacitor in order to secure the holding time, there is a problem that the component cost of the large-capacity capacitor increases.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a control device for a resonant converter capable of reliably preventing resonance shift and ensuring a long holding time without increasing the capacitance of a large-capacity capacitor.
Technical scheme
In order to solve the above problems, the present invention provides a control device for a resonant converter that receives a dc voltage of a large-capacity capacitor. The control device of the resonant converter is provided with a forced turn-off control circuit. The forced shutdown control circuit receives a resonance current detection signal obtained by dividing a resonance current flowing through the resonance type converter and converting the divided resonance current into a voltage, and outputs a forced shutdown signal if the resonance current detection signal falls between a first variable threshold and a second variable threshold smaller than the first variable threshold. Further, the forced turn-off control circuit can change the first variable threshold value and the second variable threshold value in accordance with an input voltage that is input by dividing the direct-current voltage of the large-capacity capacitor.
Technical effects
The control device for the resonant converter having the above configuration has the following advantages: by making the absolute values of the first variable threshold and the second variable threshold, which are compared with the resonance current detection signal, variable in accordance with the input voltage, it is possible to ensure the holding time at the time of low input voltage while achieving the resonance shift prevention function at the time of high input voltage.
The above and other objects, features and advantages of the present invention will become apparent from the accompanying drawings which illustrate preferred embodiments by way of example of the invention and the associated description below.
Drawings
Fig. 1 is a circuit diagram showing an example of a configuration of a switching power supply device including a DC-DC converter to which a control device according to the present invention is applied.
Fig. 2 is a functional block diagram showing an example of the configuration of a control device of a resonant converter according to an embodiment of the present invention.
Fig. 3 is a circuit diagram showing a configuration example of the forced shutdown control circuit.
Fig. 4 is a diagram showing an input-output relationship of the threshold voltage calculation section of the forced shutdown control circuit.
Fig. 5 is a timing diagram of generation of a forced shutdown signal.
Fig. 6 is a circuit diagram showing an example of the configuration of the switch on/off control circuit.
Fig. 7 is a timing chart at the time of turn-off based on the FB terminal voltage.
Fig. 8 is a timing chart at the time of forced shutdown.
Fig. 9 is a circuit diagram showing an example of the configuration of the level conversion circuit.
Description of the symbols
1: power factor correction circuit
2: DC-DC converter
10: AC power supply
11 n: output terminal
11 p: output terminal
12: control IC
21: switch on-off control circuit
22: forced turn-off control circuit
23: high-side driving circuit
24: low side driver circuit
25: starting circuit
26: voltage stabilizer
31: threshold voltage calculating section
32: level conversion circuit
ADC: analog-to-digital converter
AND1, AND 2: logic and circuit
C1: large-capacity capacitor
C2, C3, C5, C11: capacitor with a capacitor element
C6: resonant capacitor
COMP1, COMP2, COMP3, COMP4, COMP 5: comparator with a comparator circuit
COMP 6: hysteresis comparator
Cis: capacitor with a capacitor element
Co: output capacitor
Cos, Ctd: capacitor with a capacitor element
D1, D2, D3, D4: diode with a high-voltage source
DAC1, DAC 2: digital-to-analog converter
DFF1, DFF2, DFF 3: d flip-flop
INV1, INV2, INV3, INV4, INV5, INV 6: inverter circuit
Ios, Itd: constant current source
OR1, OR 2: logic OR circuit
OS1, OS 2: one-shot circuit
P1: primary coil
P2: auxiliary coil
PC 1: photoelectric coupler
Q1, Q2: switching element
R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, Rb1, Rb2, Ris, Rls1, Rls 2: resistance (RC)
RSFF1, RSFF2, RSFF3, RSFF 4: RS trigger
S1, S2: secondary coil
SR 1: parallel voltage stabilizer
SW1, SW 2: switch with a switch body
T1: transformer device
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the terminal name of a circuit and the voltage, signal, and the like at the terminal may be denoted by the same reference numerals.
Fig. 1 is a circuit diagram showing an example of a configuration of a switching power supply device including a DC-DC converter to which a control device according to the present invention is applied, and fig. 2 is a functional block diagram showing an example of a configuration of a control device of a resonant converter according to an embodiment of the present invention.
The switching power supply device of the present embodiment includes a power factor correction circuit (PFC)1 and a DC-DC converter 2, and a large-capacity capacitor C1 is disposed between the power factor correction circuit 1 and the DC-DC converter 2.
The power factor correction circuit 1 has an ac power supply 10 connected to its input terminal and a large-capacity capacitor C1 connected to its output terminal, and rectifies and boosts an ac voltage to generate a dc voltage Vi as a charging voltage of the large-capacity capacitor C1. The DC voltage Vi becomes a DC input voltage of the DC-DC converter 2.
In the DC-DC converter 2, a positive electrode terminal and a negative electrode terminal of a large-capacity capacitor C1 are connected to a half-bridge circuit in which a high-side switching element Q1 and a low-side switching element Q2 are connected in series. In this embodiment, N-channel MOSFETs are used as the switching elements Q1 and Q2.
A common connection point of the switching elements Q1 and Q2 is connected to one terminal of the primary coil P1 of the transformer T1, and the other terminal of the primary coil P1 is connected to the ground via the resonant capacitor C6. Here, the leakage inductance component of the transformer T1 and the resonant capacitor C6 constitute a resonant circuit. Instead of using the leakage inductance, another inductance different from the inductance constituting the transformer T1 may be connected in series to the resonant capacitor C6, and the inductance may be used as the resonant reactance of the resonant circuit.
One terminal of the secondary winding S1 of the transformer T1 is connected to the anode terminal of the diode D3, and one terminal of the secondary winding S2 is connected to the anode terminal of the diode D4. The cathode terminals of the diodes D3 and D4 are connected to the positive terminal of the output capacitor Co and the output terminal 11 p. The negative terminal of the output capacitor Co is connected to the output terminal 11n and the common connection point of the secondary coils S1 and S2. The secondary coils S1 and S2, the diodes D3 and D4, and the output capacitor Co constitute a circuit for rectifying and smoothing the ac voltage generated in the secondary coils S1 and S2 and converting the ac voltage into a DC output voltage Vo, and constitute an output circuit of the DC-DC converter 2.
A control IC (Integrated Circuit) 12 is a control unit that controls the DC-DC converter 2. The control IC12 has a VH terminal connected to the positive terminal of the large-capacity capacitor C1, a GND terminal connected to ground, and a BO terminal for detecting the input dc voltage Vi. The BO terminal is connected to one terminal of the resistor Rb1 and one terminal of the resistor Rb2, the other terminal of the resistor Rb1 is connected to the positive terminal of the large-capacity capacitor C1, and the other terminal of the resistor Rb2 is connected to the negative terminal of the large-capacity capacitor C1. The resistors Rb1 and Rb2 constitute a voltage divider circuit that divides an input dc voltage Vi and supplies the divided voltage to a BO terminal.
The control IC12 further has an HO terminal connected to the gate terminal of the switching element Q1 via a resistor R11, and an LO terminal connected to the gate terminal of the switching element Q2 via a resistor R12. The control IC12 further includes a VB terminal for high-side power supply, a VS terminal for high-side reference potential, a VCC terminal for power supply of the control IC12, a VW terminal for resonance voltage detection, an FB terminal for feedback of information on the output voltage Vo, and an IS terminal for resonance current detection.
A capacitor C5 is connected between the VB terminal and the VS terminal of the control IC12, and the VS terminal is connected to a common connection point of the switching elements Q1 and Q2. The VCC terminal is connected to the positive terminal of the capacitor C3, and the negative terminal of the capacitor C3 is connected to ground. The VCC terminal is also connected to the anode terminal of a diode D2, and the cathode terminal of the diode D2 is connected to the VB terminal. The VCC terminal is also connected to one terminal of a resistor R13 for current limitation, and the other terminal of the resistor R13 is connected to the cathode terminal of the diode D1. An anode terminal of the diode D1 is connected to one terminal of the auxiliary winding P2 of the transformer T1, and the other terminal of the auxiliary winding P2 is connected to ground. Thus, after the DC-DC converter 2 is started, the capacitor C3 stores the current induced in the auxiliary winding P2 as the power supply of the control IC 12.
The auxiliary winding P2 of the transformer T1 has one terminal connected to one terminal of a resistor R14, the other terminal of the resistor R14 connected to one terminal of a resistor R15, and the other terminal of the resistor R15 connected to ground. A common connection point of the resistor R14 and the resistor R15 is connected to a VW terminal of the control IC12, and a resonance voltage detection signal is supplied to the VW terminal. A connection point between the other terminal of the primary coil P1 of the transformer T1 and the resonant capacitor C6 is connected to one terminal of a capacitor Cis, the other terminal of the capacitor Cis is connected to one terminal of a resistor Ris, and the other terminal of the resistor Ris is connected to ground. The common connection point of the capacitor Cis and the resistor Ris IS connected to the IS terminal of the control IC 12. Thus, the resonance current flowing through the resonance capacitor C6 IS branched by the series circuit of the capacitor Cis and the resistor Ris, and the branched current IS converted into a voltage by the resistor Ris and supplied to the IS terminal of the control IC12 as a resonance current detection signal.
The positive terminal of the output capacitor Co is connected to the anode terminal of the light emitting diode of the photocoupler PC1 through the resistor R16, and the cathode terminal of the light emitting diode is connected to the cathode terminal of the shunt regulator SR 1. A resistor R17 is connected between the anode terminal and the cathode terminal of the light emitting diode. The anode terminal of shunt regulator SR1 is connected to output terminal 11 n. The shunt regulator SR1 has a reference terminal connected to a connection point of resistors R18 and R19 connected in series between the positive terminal and the negative terminal of the output capacitor Co. The shunt regulator SR1 has a series circuit of a resistor R20 and a capacitor C11 connected between a reference terminal and a cathode terminal. The shunt regulator SR1 is a device that causes a current corresponding to a difference between a potential obtained by dividing the output voltage Vo (voltage across the output capacitor Co) by the resistors R18 and R19 and a built-in reference voltage to flow through a light emitting diode of the photocoupler PC 1. As a result, a current corresponding to an error of the output voltage Vo with respect to the target voltage flows through the light emitting diode. A collector terminal of a phototransistor of the photocoupler PC1 is connected to the FB terminal of the control IC12, an emitter terminal is connected to ground, and a capacitor C2 is connected between the collector terminal and the emitter terminal. The FB terminal is pulled up to an internal reference voltage not shown through a resistor not shown.
As shown in fig. 2, the control IC12 includes a switching on/off control circuit 21, a forced off control circuit 22, a high-side drive circuit 23, a low-side drive circuit 24, a start-up circuit 25, and a regulator 26.
The VH terminal of the control IC12 is connected to the input terminal of the startup circuit 25, and the output terminal of the startup circuit 25 is connected to the VCC terminal, the switch on/off control circuit 21, the low-side driver circuit 24, and the regulator 26. The voltage regulator 26 generates a voltage VDD of an internal power supply and supplies it to the switch on/off control circuit 21 and the forced off control circuit 22.
The FB terminal is connected to an input terminal of the switch on/off control circuit 21, and a high-side output terminal of the switch on/off control circuit 21 is connected to an input terminal of the high-side drive circuit 23 to supply the high-side drive signal hi _ pre. The low-side output terminal of the switch on/off control circuit 21 is connected to the input terminal of the low-side driver 24 to provide the low-side drive signal lo _ pre. The output terminal of the high-side driver circuit 23 is connected to the HO terminal, and the output terminal of the low-side driver circuit 24 is connected to the LO terminal. The high-side driver circuit 23 is also connected to a VB terminal for a high-side power supply and a VS terminal that becomes a high-side reference potential.
The VW terminal, the IS terminal, and the BO terminal are connected to an input terminal of the forced-off control circuit 22, and an output terminal of the forced-off control circuit 22 IS connected to an input terminal of the switch on-off control circuit 21, and supplies a forced-off signal fto. The forced turn-off control circuit 22 is also connected to the high-side output terminal and the low-side output terminal of the switch on-off control circuit 21, and receives the high-side drive signal hi _ pre and the low-side drive signal lo _ pre.
According to the DC-DC converter 2, if the charging voltage of the large-capacity capacitor C1 becomes high, the starter circuit 25 operates in the control IC12 to output a current for charging the capacitor C3 from the output terminal thereof. This current charges a capacitor C3 connected to the VCC terminal through the VCC terminal to generate a voltage VCC. Then, a constant voltage VDD is generated from the voltage VCC by the regulator 26 and supplied to the switch on/off control circuit 21 and the forced off control circuit 22. If the voltage VCC and the voltage VDD are asserted and the DC-DC converter 2 starts the switching action, the voltage of the VCC terminal is maintained by the current supplied from the auxiliary winding P2 of the transformer T1.
The switch on/off control circuit 21 receives information of the output voltage Vo input to the FB terminal, and controls the on widths of the high-side drive signal hi _ pre and the low-side drive signal lo _ pre so that the output voltage Vo becomes a predetermined constant value.
The forced shutdown control circuit 22 receives an input voltage detection signal at the BO terminal, a resonance voltage detection signal at the VW terminal, and a resonance current detection signal at the IS terminal. The resonance voltage detection signal received at the VW terminal determines the direction of the resonance current change (the increasing direction or the decreasing direction), and the resonance current detection signal received at the IS terminal determines the timing of forcibly turning off the high-side drive signal hi _ pre and the low-side drive signal lo _ pre. The input voltage sense signal at the BO terminal determines the threshold at which the high side drive signal hi _ pre and the low side drive signal lo _ pre are turned off.
Therefore, the forced-off control circuit 22 turns off the high-side drive signal hi _ pre when the signal of the VW terminal decreases, when the signal of the VW terminal IS lower than the first fixed threshold and the signal of the IS terminal IS lower than the first variable threshold. Further, the forced turn-off control circuit 22 turns off the low-side drive signal lo _ pre when the signal of the VW terminal rises, and when the signal of the VW terminal IS higher than a second fixed threshold smaller than the first fixed threshold and the signal of the IS terminal IS higher than a second variable threshold smaller than the first variable threshold. Here, the first variable threshold and the second variable threshold vary depending on the value of the input voltage detection signal at the BO terminal, that is, the value of the input dc voltage Vi, and are set high when the dc voltage Vi is high, and are set low when the dc voltage Vi is low. The range in which the first variable threshold and the second variable threshold are set low is a range in which the DC-DC converter 2 can maintain the predetermined output voltage Vo. Accordingly, when the dc voltage Vi is high, the first variable threshold and the second variable threshold are set high, and therefore, resonance shift can be reliably prevented. On the other hand, if the direct-current voltage Vi becomes low, the first variable threshold value and the second variable threshold value are set low, it takes time until the signal of the IS terminal reaches the first variable threshold value and the second variable threshold value, and execution of forced turn-off IS delayed accordingly, so the holding time can be extended.
Next, a specific configuration example of the forced off control circuit 22 and the switch on/off control circuit 21 will be described.
Fig. 3 is a circuit diagram showing an example of the configuration of the forced shutdown control circuit, fig. 4 is a diagram showing the input/output relationship of the threshold voltage calculation unit of the forced shutdown control circuit, and fig. 5 is a timing chart of generation of a forced shutdown signal.
As shown in fig. 3, in the forced-off control circuit 22, the VW terminal is connected to the inverting input terminal of the comparator COMP1 and the non-inverting input terminal of the comparator COMP 2. A fixed threshold voltage Vthvwh (first fixed threshold) for the high side is applied to the non-inverting input terminal of the comparator COMP1, and the output terminal of the comparator COMP1 is connected to the clock input terminal C of the D flip-flop DFF 1. A fixed threshold voltage Vthvwl (second fixed threshold) for the low side is applied to the inverting input terminal of the comparator COMP2, and the output terminal of the comparator COMP2 is connected to the clock input terminal C of the D flip-flop DFF 2.
The voltage VDD of the internal power supply is applied to the input terminals D of the D flip-flops DFF1 and DFF2, respectively. The output terminal Q of the D flip-flop DFF1 is connected to the set input terminal S of the reset-prioritized RS flip-flop RSFF 1. The output terminal Q of the D flip-flop DFF2 is connected to the set input terminal S of the reset-prioritized RS flip-flop RSFF 2. The low-side drive signal lo _ pre output by the switch on/off control circuit 21 is input to the reset input terminal R of the D flip-flop DFF1 and the first reset input terminal R1 of the RS flip-flop RSFF 1. The high-side driving signal hi _ pre output from the switch on/off control circuit 21 is input to the reset input terminal R of the D flip-flop DFF2 and the first reset input terminal R1 of the RS flip-flop RSFF 2.
The IS terminal IS connected to a non-inverting input terminal of the comparator COMP3 and an inverting input terminal of the comparator COMP4 via the level shift circuit 32. Since the level shift circuit 32 IS not assumed before the description below, the following description will be given assuming that the signal output from the level shift circuit IS the same as the voltage of the IS terminal. An output terminal of the comparator COMP3 is connected to the second reset input terminal R2 of the RS flip-flop RSFF1, and an output terminal of the comparator COMP4 is connected to the second reset input terminal R2 of the RS flip-flop RSFF 2.
A threshold voltage Vthish (first variable threshold) and Vthisl (second variable threshold) that are variable according to the dc voltage Vi are input to the inverting input terminal of the comparator COMP3 and the non-inverting input terminal of the comparator COMP4, respectively. That is, the BO terminal is connected to the input terminal of the analog-digital converter ADC, and the output terminal of the analog-digital converter ADC is connected to the input terminal of the threshold voltage calculation unit 31. The high-side output terminal of the threshold voltage calculator 31 is connected to the input terminal of the digital-analog converter DAC1, and the low-side output terminal of the threshold voltage calculator 31 is connected to the input terminal of the digital-analog converter DAC 2. An output terminal of the digital-analog converter DAC1 is connected to an inverting input terminal of the comparator COMP3, and an output terminal of the digital-analog converter DAC2 is connected to a non-inverting input terminal of the comparator COMP 4. In this embodiment, the analog-digital converter ADC, the digital-analog converter DAC1, and the DAC2 have 10-bit resolution.
The output terminals Q of the RS flip-flops RSFF1 and RSFF2 are connected to the input terminal of the OR circuit OR1, respectively, and the output terminal of the OR circuit OR1 is connected to the output terminal of the forced off control circuit 22 that outputs the forced off signal fto.
Here, the threshold voltage calculation unit 31 calculates the high-side threshold voltage Vthish and the low-side threshold voltage Vthisl based on the voltage Vbo input to the BO terminal, in accordance with the relationship shown in fig. 4. In fig. 4, the abscissa indicates the voltage Vbo obtained by dividing the dc voltage Vi by the voltage divider circuit including the resistors Rb1 and Rb2, and the ordinate indicates the threshold voltage Vthis for comparing the resonance current calculated by the threshold voltage calculator 31 (the threshold voltage Vthish and the threshold voltage Vthisl are collectively referred to as the threshold voltage Vthis).
The threshold voltage calculation unit 31 outputs a threshold voltage Vthis that is variable according to the voltage Vbo within a predetermined voltage range of the voltage Vbo, and outputs the threshold voltage Vthis that is not variable according to the voltage Vbo outside the predetermined voltage range.
That is, when the voltage Vbo is in the relationship Vbo2< Vbo1, the threshold voltage Vthish for the high side is:
[ mathematical formula 1 ]
When the voltage Vbo is Vbo not less than Vbo1, the following results are obtained:
Vthish＝Vthish1 (2)
when the voltage Vbo is Vbo ≦ Vbo2, the following results are obtained:
Vthish＝Vthish2 (3)。
on the other hand, when the voltage Vbo is in the relationship Vbo2< Vbo1, the low-side threshold voltage Vthisl is:
[ mathematical formula 2 ]
When the voltage Vbo is Vbo not less than Vbo1, the following results are obtained:
Vthisl＝Vthisl1 (5)
when the voltage Vbo is Vbo ≦ Vbo2, the following results are obtained:
Vthisl＝Vthisl2 (6)。
here, taking a numerical example, Vbo1 corresponds to 400 volts (V) of a predetermined voltage, and Vbo2 corresponds to 260V when the voltage drops when the power supply is lost, with respect to the dc voltage Vi. The absolute values of the high-side threshold voltage Vthish1 and the low-side threshold voltage Vthisl1 are 1V, and the absolute values of the high-side threshold voltage Vthish2 and the low-side threshold voltage Vthisl2 are 0.5V. Thus, the threshold voltage Vthis for resonance current comparison is set high when the dc voltage Vi is high, and is set low when the dc voltage Vi is low.
Next, the operation of the forced shutdown control circuit 22 configured as described above will be described with reference to fig. 5. In fig. 5, threshold voltages Vthvwh and Vthvwl for resonance voltage signal comparison are fixed values, and threshold voltages Vthish and Vthisl for resonance current signal comparison have variable values calculated by the threshold voltage calculation unit 31.
First, when the high-side drive signal hi _ pre IS at a high (H) level and the low-side drive signal lo _ pre IS at a low (L) level, the resonance current detection signal of the IS terminal IS in a state higher than the high-side threshold voltage Vthish. Therefore, the comparator COMP3 outputs a signal of H level, the RS flip-flop RSFF1 is reset, and the D flip-flop DFF2 and the RS flip-flop RSFF2 are reset according to the high-side driving signal hi _ pre.
Here, if the resonance voltage detection signal of the VW terminal is lower than the threshold voltage Vthvwh, the output terminal of the comparator COMP1 becomes H level. Thus, the D flip-flop DFF1 latches the voltage VDD (H-level signal) at the rising timing of the signal input to the clock input terminal C, and outputs the H-level signal to the output terminal Q. Although the signal of the H level is input to the set input terminal S of the RS flip-flop RSFF1, since the RS flip-flop RSFF1 is preferentially reset according to the output signal of the comparator COMP3, the output terminal Q thereof is maintained at the L level. Further, since the RS flip-flop RSFF2 is also reset in accordance with the high-side drive signal hi _ pre, the output terminal Q thereof is held at the L level. Therefore, the forced off signal fto output from the OR circuit 1 is at the L level.
Thereafter, if the resonance current detection signal of the IS terminal IS lower than the threshold voltage Vthish for the high side, the comparator COMP3 outputs a signal of the L level. Thereby, both the first reset input terminal R1 and the second reset input terminal R2 of the RS flip-flop RSFF1 become the L level. At this time, the reset of the RS flip-flop RSFF1 is released, and the set input terminal S is set by the H-level signal input thereto, and the H-level signal is output to the output terminal Q. Thus, the OR circuit OR1 outputs the H-level forced off signal fto, and the switch on/off control circuit 21 that has received this signal forcibly sets the H-level high-side drive signal hi _ pre to the L level at that time.
The H-level forced off signal fto becomes L-level at the time when the low-side drive signal lo _ pre becomes H-level and the RS flip-flop RSFF1 is reset.
Similarly, when the high-side drive signal hi _ pre IS at the L level and the low-side drive signal lo _ pre IS at the H level, the resonance current detection signal at the IS terminal IS in a state lower than the low-side threshold voltage Vthisl (however, the absolute value IS larger than the absolute value of the low-side threshold voltage Vthisl). Therefore, the comparator COMP4 outputs a signal of H level, the RS flip-flop RSFF2 is reset, and the D flip-flop DFF1 and the RS flip-flop RSFF1 are reset according to the low-side drive signal lo _ pre.
Here, if the resonance voltage detection signal of the VW terminal becomes higher than the threshold voltage Vthvwl, the output terminal of the comparator COMP2 becomes H level. Thus, in the D flip-flop DFF2, since the signal input to the clock input terminal C rises, the voltage VDD (H-level signal) is latched at the rising timing, and the H-level signal is output to the output terminal Q. Although the signal of the H level is input to the set input terminal S of the RS flip-flop RSFF2, since the RS flip-flop RSFF2 is preferentially reset according to the output signal of the comparator COMP4, the output terminal Q thereof is maintained at the L level. Further, since the RS flip-flop RSFF1 is also reset according to the low-side drive signal lo _ pre, the output terminal Q thereof is held at the L level. Therefore, the forced off signal fto output from the OR circuit 1 is at the L level.
Thereafter, if the resonance current detection signal of the IS terminal becomes higher than the threshold voltage Vthisl for the low side, the comparator COMP4 outputs a signal of the L level. Thereby, both the first reset input terminal R1 and the second reset input terminal R2 of the RS flip-flop RSFF2 become the L level. At this time, the RS flip-flop RSFF2 is set because an H-level signal is input to the set input terminal S, and outputs an H-level signal to the output terminal Q. Thus, the OR circuit OR1 outputs the H-level forced off signal fto, and the switch on/off control circuit 21 that has received this signal forcibly sets the H-level low-side drive signal lo _ pre to the L level at that time.
The H-level forced turn-off signal fto becomes the L level at the timing when the high-side drive signal hi _ pre becomes the H level and resets the RS flip-flop RSFF 2.
In a normal operation in which no resonance shift occurs, the high-side drive signal hi _ pre or the low-side drive signal lo _ pre is set to a high level before the forced off signal fto is output, and the D flip-flop DFF1 or DFF2 is reset again, so that the forced off signal fto is not output.
The forced shutdown control circuit 22 repeatedly executes the above operations and makes the high-side threshold voltage Vthish and the low-side threshold voltage Vthisl variable in accordance with a change in the input dc voltage Vi.
Fig. 6 is a circuit diagram showing an example of the configuration of the switch on/off control circuit, fig. 7 is a timing chart at the time of off based on the FB terminal voltage, and fig. 8 is a timing chart at the time of forced off.
As shown in fig. 6, in the switch on/off control circuit 21, the FB terminal is connected to the inverting input terminal of the comparator COMP 5. The non-inverting input terminal of the comparator COMP5 is connected to a connection point between one terminal of the constant current source Ios and one terminal of the capacitor Cos, and receives the charging voltage Vos of the capacitor Cos. The other terminal of the constant current source Ios receives the voltage VDD, and the other terminal of the capacitor Cos is connected to ground. A switch SW1 is connected in parallel to the capacitor Cos. Here, the comparator COMP5, the constant current source Ios, the capacitor Cos, and the switch SW1 constitute a circuit that determines the on widths, that is, the timings of turning off, of the high-side drive signal hi _ pre and the low-side drive signal lo _ pre.
An output terminal of the comparator COMP5 is connected to a first input terminal of the OR circuit OR 2. A second input terminal of the OR logic 2 is connected to a terminal that receives the forced shutdown signal fto output from the forced shutdown control circuit 22. An output terminal of the OR logic 2 is connected to a set input terminal S of the reset-priority RS flip-flop RSFF 3.
An output terminal Q of the RS flip-flop RSFF3 is connected to a control input terminal of the switch SW1, an input terminal of the inverter circuit INV3, and an input terminal of the one-shot circuit OS2, and outputs a signal Td. An output terminal of the inverter circuit INV3 is connected to an input terminal of the one-shot circuit OS 1.
An output terminal of the inverter circuit INV3 is connected to the control input terminal of the switch SW 2. One terminal of the switch SW2 is connected to one terminal of the constant current source Itd, one terminal of the capacitor Ctd, and an input terminal of the inverter circuit INV1, and the inverter circuit INV1 receives the charging voltage Vtd of the capacitor Ctd. The other terminal of the constant current source Itd receives the voltage VDD, and the other terminal of the capacitor Ctd and the other terminal of the switch SW2 are connected to ground. An output terminal of the inverter circuit INV1 is connected to an input terminal of the inverter circuit INV2, and an output terminal of the inverter circuit INV2 is connected to the second reset input terminal R2 of the RS flip-flop RSFF 3. Here, the constant current source Itd, the switch SW2, the capacitor Ctd, and the inverter circuits INV1 and INV2 constitute a circuit that determines a dead time, that is, a time from when one of the high-side drive signal hi _ pre and the low-side drive signal lo _ pre is turned off (a signal at an L level) to when the other is turned on (a signal at an H level).
A first reset input terminal R1 of the RS flip-flop RSFF3 is connected to an output terminal of the hysteresis comparator COMP 6. An inverting input terminal of the hysteresis comparator COMP6 receives the power supply voltage VCC of the control IC12, and a non-inverting input terminal of the hysteresis comparator COMP6 receives the threshold voltages Vthvcch and Vthvccl. The hysteresis comparator COMP6 constitutes a low Voltage malfunction prevention (UVLO) circuit so that an abnormal operation is not caused when the Voltage VCC drops to a Voltage lower than a Voltage at which the internal circuits of the control IC12 can operate.
An output terminal of the one-shot circuit OS1 is connected to a set input terminal S of the RS flip-flop RSFF4, and outputs a turn-on trigger signal on _ trg that sets the RS flip-flop RSFF 4. The output terminal of the one-shot circuit OS2 is connected to the reset input terminal R of the RS flip-flop RSFF4, and outputs an off trigger signal off _ trg that resets the RS flip-flop RSFF 4. An output terminal Q of the RS flip-flop RSFF4 is connected to first input terminals of the AND circuits AND1, AND 2.
The output terminal of the one-shot circuit OS2 is also connected to the input terminal of the inverter circuit INV 4. An output terminal of the inverter circuit INV4 is connected to the clock input terminal C of the D flip-flop DFF 3. An input terminal D of the D flip-flop DFF3 is connected to an output terminal of the inverter circuit INV5, and an input terminal of the inverter circuit INV5 is connected to an output terminal Q of the D flip-flop DFF 3. The output terminal Q of the D flip-flop DFF3 is also connected to a second input terminal of the AND circuit AND1 AND an input terminal of the inverter circuit INV6, AND outputs the drive selection signal dri _ sel. An output terminal of the inverter circuit INV6 is connected to a second input terminal of the AND circuit AND 2. The output terminal of the AND logic circuit AND1 constitutes an output terminal of the switch on/off control circuit 21 that outputs the high-side drive signal hi _ pre. The output terminal of the AND logic circuit AND2 constitutes an output terminal of the switch on/off control circuit 21 that outputs the low-side drive signal lo _ pre. The reset input terminal R of the D flip-flop DFF3 is connected to the output terminal of the hysteresis comparator COMP 6.
Next, the operation of the switch on/off control circuit 21 will be described with reference to fig. 7. First, if the charging voltage Vos of the capacitor Cos becomes higher than the voltage of the FB terminal, the comparator COMP5 sets the RS flip-flop RSFF3 via the OR circuit OR 2. Thereby, the signal Td of the H level is output from the RS flip-flop RSFF 3. The signal Td is input to the one-shot circuit OS2, and the one-shot circuit OS2 outputs an off trigger signal off _ trg having a predetermined on width that rises in synchronization with the rising edge of the signal Td. The off trigger signal off _ trg resets the RS flip-flop RSFF4, AND the RS flip-flop RSFF4 supplies a signal of L level to the first input terminals of the AND circuits AND1 AND 2. Thereby, the high-side drive signal hi _ pre AND the low-side drive signal lo _ pre output from the AND circuits AND1 AND2 become L level.
If the signal Td becomes H level, the switch SW1 is turned on (turned on) to discharge the charge of the capacitor Cos. Further, since the output of the inverter circuit INV3 becomes L level, the switch SW2 is turned off (opened), the charging of the capacitor Ctd is started, and the charging voltage Vtd thereof rises. If the charging voltage Vtd rises to become higher than the threshold voltage of the inverter circuit INV1, the output of the inverter circuit INV1 becomes L level, and the output of the inverter circuit INV2 becomes H level. The H-level signal resets the RS flip-flop RSFF3 so that the output signal Td thereof becomes L-level. The L-level signal Td is logically inverted by the inverter circuit INV3 and input to the one-shot circuit OS1, and the one-shot circuit OS1 outputs the on-trigger signal on _ trg having a predetermined on width that rises in synchronization with a rising edge of the output signal of the inverter circuit INV3, that is, a falling edge of the signal Td. The on trigger signal on _ trg sets an RS flip-flop RSFF4, AND the RS flip-flop RSFF4 supplies an H-level signal to the first input terminals of the AND circuits AND1 AND 2. Thus, the AND circuits AND1 AND2 output the drive selection signal dri _ sel or the logical inversion signal thereof input to the second input terminal thereof as the high-side drive signal hi _ pre AND the low-side drive signal lo _ pre.
Further, if the signal Td becomes L level, the switch SW2 is turned on (turned on) to discharge the charge of the capacitor Ctd, and the switch SW1 is turned off (turned off), the charging of the capacitor Cos is started, and the charging voltage Vos thereof rises. At the time when the charging voltage Vos reaches the voltage of the FB terminal, the output state of the comparator COMP5 is inverted, and an H-level signal is input to the set input terminal S of the RS flip-flop RSFF 3. At this time, since the second reset input terminal R2 of the RS flip-flop RSFF3 is at the L level, the RS flip-flop RSFF3 outputs the signal Td at the H level.
Since the signal Td becomes H level, the one-shot circuit OS2 outputs the off trigger signal off _ trg. The off trigger signal off _ trg is logically inverted by the inverter circuit INV4 and input to the clock input terminal C of the D flip-flop DFF 3. Thus, the D flip-flop DFF3 latches the output state of the inverter circuit INV5 in synchronization with the falling edge of the off trigger signal off _ trg. That is, when the output state of the D flip-flop DFF3 is at the L level, the H-level signal is latched and outputted. Conversely, when the output state of the D flip-flop DFF3 is at the H level, the L-level signal, which is logically inverted by the inverter circuit INV5, is latched and output. The output signal of the D flip-flop DFF3 is input to the AND circuit AND1 as the drive selection signal dri _ sel, AND is output from the AND circuit AND1 as the high-side drive signal hi _ pre. Further, a signal obtained by logically inverting the drive selection signal dri _ sel outputted from the D flip-flop DFF3 by the inverter circuit INV6 is inputted to the AND circuit AND2, AND is outputted from the AND circuit AND2 as the low-side drive signal lo _ pre.
When the hysteresis comparator COMP6 detects an abnormal drop in the voltage VCC, the hysteresis comparator COMP6 outputs an H-level signal to forcibly reset the RS flip-flop RSFF3 and the D flip-flop DFF 3.
Here, a case where the forced shutdown signal fto is received from the forced shutdown control circuit 22 will be described. The OR logic circuit OR2 receives a signal for controlling the on width by the voltage of the FB terminal from the comparator COMP5, receives the forced off signal fto from the forced off control circuit 22, and inputs the set signal to the RS flip-flop RSFF 4. Therefore, the RS flip-flop RSFF4 is set in response to the signal that first becomes the H level of the signal that controls the on width and the forced off signal fto.
Here, if the forced turn-off signal fto is input before the charging voltage Vos of the capacitor Cos reaches the voltage of the FB terminal, the RS flip-flop RSFF4 outputs a signal Td that rises in synchronization with the rising edge of the forced turn-off signal fto. As shown in fig. 8, the dead time is set and the timing of conduction is the same as that in the normal control.
Next, the level shift circuit 32 shown in fig. 3 will be explained.
Fig. 9 is a circuit diagram showing an example of the configuration of the level conversion circuit. First, although the voltage input to the IS terminal IS generated by the shunt of the resonance current flowing through the resistor Ris, the voltage may be positive or negative depending on the direction of the resonance current. The control IC12 can handle an input of a negative voltage if it is a device to which a negative voltage power supply is supplied, but latch is generated if the input becomes a negative voltage if it is not a device to which a negative voltage power supply is supplied. The level shift circuit 32 IS a circuit that level-shifts (level-rises) the voltage IS to a voltage IS2 that IS always a positive voltage so that a voltage that can be positive or negative (this voltage IS also shown as IS) input to the IS terminal can be handled without latch-up even if the control IC12 IS not a device to which a negative voltage power supply IS supplied.
As shown in fig. 9, the level shift circuit 32 connects the IS terminal to the internal power supply of the voltage VDD via a series circuit including resistors Rls1 and Rls2, and sets the potential IS2 at the connection point between the resistors Rls1 and Rls2 as an output signal of the level shift circuit 32. Here, the voltage IS2 of the output signal IS expressed by the following equation.
[ mathematical formula 3 ]
When the level shift circuit 32 IS used, Vthish and Vthisl obtained by the above expressions (1) to (6) may be substituted into IS of expression (7) to compare the value obtained with IS 2.
Since the resonance voltage detection signal input to the VW terminal IS also a voltage that can be positive or negative, when the control IC12 does not handle a negative voltage, a level shift (level up) circuit connected to the VW terminal IS provided as in the IS terminal, and the threshold voltage to be compared with the voltage of the VW terminal may be converted as in equation (7).
The foregoing is considered as illustrative only of the principles of the invention. It will be apparent to those skilled in the art that numerous modifications and variations can be made, and the present invention is not limited to the exact construction and application examples shown and described, and all modifications and equivalents thereof are intended to be included within the scope of the invention as defined in the appended claims and their equivalents.
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| US11258352B2 (en) * | 2019-05-10 | 2022-02-22 | Dell Products L.P. | Systems and methods for fast response and low total harmonic distortion power factor correction |
| US11418125B2 (en) | 2019-10-25 | 2022-08-16 | The Research Foundation For The State University Of New York | Three phase bidirectional AC-DC converter with bipolar voltage fed resonant stages |
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2019
- 2019-01-23 JP JP2020507379A patent/JP6849143B2/en active Active
- 2019-01-23 WO PCT/JP2019/002019 patent/WO2019181181A1/en active Application Filing
- 2019-01-23 CN CN201980004095.5A patent/CN111052581B/en active Active
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2020
- 2020-02-26 US US16/801,716 patent/US10855189B2/en active Active
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| JP2007151324A (en) * | 2005-11-29 | 2007-06-14 | Mitsumi Electric Co Ltd | Resonance converter |
| CN102035408A (en) * | 2009-09-29 | 2011-04-27 | 三垦电气株式会社 | Resonant type converter apparatus |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN111052581B (en) | 2023-01-24 |
| US10855189B2 (en) | 2020-12-01 |
| US20200195151A1 (en) | 2020-06-18 |
| WO2019181181A1 (en) | 2019-09-26 |
| JPWO2019181181A1 (en) | 2020-10-22 |
| JP6849143B2 (en) | 2021-03-24 |
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