CN111048470B - Manufacturing method of semiconductor chip - Google Patents

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor chip, which comprises the following steps: forming a first metal pattern on a substrate, wherein the first metal pattern is positioned in a chip area and a cutting area of the substrate, and the cutting area surrounds the chip area; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all of the metal material layer located in the dicing area and a portion located in the die area, thereby forming a second metal pattern located in the die area; forming a third metal pattern, wherein the third metal pattern covers the second metal pattern in the chip area and is positioned on the first metal pattern in the cutting area; and singulating along the dicing regions to form semiconductor chips.

Description

Manufacturing method of semiconductor chip

technical field

The invention relates to a method for manufacturing a semiconductor chip.

Background technique

Current wafer dicing technologies include mechanical dicing, laser dicing, and plasma dicing. As the feature size of semiconductor devices shrinks, the number of semiconductor chips formed on each semiconductor wafer continues to increase. As a result, the time required for mechanical cutting or laser cutting is greatly increased. Therefore, in recent years, plasma cutting, which has the advantages of short process time and so on, has been paid more and more attention.

However, when the dicing lines of the semiconductor wafer contain metals or alloys (such as aluminum or aluminum alloys) that are difficult to etch or may produce etching by-products that are difficult to remove, the plasma dicing process will be hindered. In addition, the yield rate of semiconductor chip packaging may also be reduced.

Contents of the invention

The invention provides a method for manufacturing a semiconductor chip, which can make the plasma cutting process go smoothly and improve the yield rate of the semiconductor chip package.

The manufacturing method of the semiconductor chip of the present invention includes: forming a first metal pattern on a substrate, wherein the first metal pattern is located in the chip region and the cutting region of the substrate, and the cutting region surrounds the chip region; forming a metal material on the first metal pattern layer; patterning the metal material layer, to remove substantially all parts of the metal material layer located in the cutting area and a part located in the chip area, thereby forming a second metal pattern located in the chip area; forming a third metal pattern, Wherein the third metal pattern covers the second metal pattern in the chip area and is located on the first metal pattern in the cutting area; and singulates along the cutting area to form a semiconductor chip.

In some embodiments of the present invention, the method for patterning a metal material layer includes: forming a photoresist layer on the metal material layer; performing a first exposure to the photoresist layer, so that the photoresist The layer has a first soluble area, wherein the distribution range of the first soluble area overlaps the chip area and the cutting area; the second exposure is performed on the photoresist layer, so that the photoresist layer also has a second The soluble area, wherein the second soluble area is located in the cutting area; developing to remove the first soluble area and the second soluble area of the photoresist layer to expose the metal material layer; The remaining part of the resist layer is masking and removing the exposed part of the metal material layer to form a second metal pattern; and removing the remaining part of the photoresist layer.

Based on the above, the embodiment of the present invention synchronously removes the material layer in the dicing area that may hinder the etching process when forming the components in the semiconductor chip, so that the singulation step such as the plasma dicing process can be smoothly performed. In this way, the yield rate and production capacity of semiconductor chip packaging can be improved. In some embodiments, the method of simultaneously removing the material layer in the dicing area that may hinder the etching process while forming the components in the chip area includes exposing twice the photoresist used to pattern the material layer. The first exposure is used to define the predetermined pattern of the material layer in the chip region and the cutting region, and the second exposure is used to remove the predetermined pattern of the material layer in the cutting region. In this way, the material layer only forms a predetermined pattern in the chip area, and is substantially completely removed in the cutting area. In these embodiments, it is only necessary to add an additional exposure process in the predetermined process to remove the part of the material layer located in the cutting area without affecting the desired pattern of the material layer in the chip area, and without Need to change the mask design of the predetermined process. In other words, a significant increase in manufacturing cost can be avoided.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1 is a flowchart of a method for manufacturing a semiconductor chip according to some embodiments of the present invention;

2A to 2K are schematic cross-sectional views of structures in various intermediate steps of the manufacturing method of the semiconductor chip according to some embodiments of the present invention.

Detailed ways

FIG. 1 is a flowchart of a method of manufacturing a semiconductor chip 10 according to some embodiments of the present invention. 2A to 2K are schematic cross-sectional views of structures in various intermediate steps of the manufacturing method of the semiconductor chip 10 according to some embodiments of the present invention.

Referring to FIG. 1 and FIG. 2A , step S100 is performed to provide a substrate 100 . In some embodiments, the substrate 100 may be a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate and the SOI substrate may include elemental semiconductors or alloy semiconductors. Elemental semiconductors may include Si or Ge, for example. Alloy semiconductors may include SiGe, SiC, SiGeC, III-V semiconductor materials, or II-VI semiconductor materials. In some embodiments, the substrate 100 may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be N type, and the second conductivity type can be P type. The substrate 100 may include a chip region CR and a cutting region SR surrounding the chip region CR (as shown by the dotted line area in FIG. 2A ). The chip region CR of the substrate 100 may be used to form a semiconductor chip. On the other hand, during the subsequent singulation step, cleavage can be performed along the cleavage region SR. In some embodiments, a plurality of electronic elements (not shown) may be formed in and/or on the substrate 100 in the chip region CR. Electronic components may include active components and passive components. Active components are, for example, transistors, diodes, and the like. Passive components are, for example, resistors, capacitors, inductors and the like.

Step S102 is performed to form a first metal pattern M1 on the substrate 100 . Before forming the first metal pattern M1 , a dielectric layer D1 may be formed on the substrate 100 . The dielectric layer D1 may be formed in the chip region CR and the cutting region SR. Next, the dielectric layer D1 may be patterned to form a plurality of openings V1 in the dielectric layer D1. A part of the plurality of openings V1 may be located in the chip region CR, and another part may be located in the cutting region SR. Subsequently, a first metal pattern M1 is formed within the plurality of openings V1. The method of forming the first metal pattern M1 may include filling a metal material in the plurality of openings V1. The metal material may extend to the top surface of the dielectric layer D1 (not shown). Next, a planarization process is performed to remove a portion of the metal material located on the top surface of the dielectric layer D1, thereby forming a first metal pattern M1. In some embodiments, the method of filling the metal material may include a plating process (such as electroplating or electroless plating), chemical vapor deposition, and the like. In addition, the planarization process can be a chemical mechanical polishing method. In some embodiments, the first metal pattern M1 may be a conductive plug or a conductive via. The material of the first metal pattern M1 may include tungsten.

Referring to FIG. 1 and FIG. 2B , step S104 is performed to form a metal material layer M2 a on the first metal pattern M1 . The metal material layer M2a covers the first metal pattern M1 and the dielectric layer D1 in the chip region CR and the cutting region SR. In some embodiments, the metal material layer M2a may be formed by a plating process or a chemical vapor deposition method. The material of the metal material layer M2a includes materials that are not easy to be etched or may produce etching by-products that are not easily removed when they are etched together with their silicon-based materials. For example, the material of the metal material layer M2a may include aluminum.

Referring to FIG. 1 and FIG. 2C to FIG. 2G , next, the metal material layer M2 a is patterned to form a second metal pattern M2 . Referring to FIG. 1 and FIG. 2C , in some embodiments, the method for patterning the metal material layer M2a may include performing step S106 to form a photoresist layer PR on the metal material layer M2a. The photoresist layer PR is formed in the chip region CR and the cutting region SR. In some embodiments, the photoresist layer PR includes a positive photoresist material. In other words, before exposure, the photoresist layer PR may be in an insoluble state.

Referring to FIG. 1 and FIG. 2D , step S108 is performed to perform a first exposure on the photoresist layer PR, so that the photoresist layer PR has a first soluble region DR1 . After the first exposure, the portion of the photoresist layer PR other than the first soluble region DR1 is still in an insoluble state, or referred to as an insoluble region IDR. In some embodiments, the first exposure may be performed through the first photomask PM1. The first photomask PM1 covers the chip region CR and the cutting region SR, and has an opening P1 intended to define the first soluble region DR1 . In other words, the opening P1 of the first photomask PM1 can expose the first soluble region DR1 , and the main body of the first photomask PM1 can vertically overlap the insoluble region IDR. After the portion of the photoresist layer PR exposed by the opening P1 is irradiated by the light L, it can change from an insoluble state to a soluble state, thereby forming the first soluble region DR1 . On the other hand, the part of the photoresist layer PR not irradiated by the light L is the insoluble region IDR. A part of the plurality of openings P1 of the first photomask PM1 overlaps the chip region CR, and another part overlaps the cutting region SR. It can be known that the distribution range of the first soluble region DR1 overlaps the chip region CR and the dicing region SR.

Referring to FIG. 1 and FIG. 2E , step S110 is performed to perform a second exposure on the photoresist layer PR, so that the photoresist layer PR also has a second dissolvable region DR2 located in the cutting region SR. In some embodiments, the distribution range of the second soluble region DR2 does not overlap with the chip region CR. Specifically, performing the second exposure may convert at least a portion of the insoluble region IDR of the photoresist layer PR overlapping the cutting region SR into the second soluble region DR2. In some embodiments, all the insoluble regions IDR located in the cutting region SR shown in FIG. 2D may be transformed into the second soluble region DR2. In some embodiments, the second exposure may be performed through a second photomask PM2. The main body of the second photomask PM2 covers the chip region CR, and the second photomask PM2 has an opening P2 substantially completely exposing the cutting region SR. In other words, the opening P2 of the second photomask PM2 exposes the first soluble region DR1 and the insoluble region IDR in the cutting region SR shown in FIG. 2D . The light L passes through the opening P2 of the second photomask PM2 to irradiate the photoresist layer PR, so that the insoluble region IDR of the photoresist layer PR located in the cutting region SR can be transformed into the second soluble region DR2 , while the first soluble region DR1 in the cutting region SR still maintains a soluble state.

Please refer to FIG. 2E, after the first exposure and the second exposure, substantially all parts of the photoresist layer PR in the cutting region SR are transformed into a soluble state (including the first soluble portion in the cutting region SR). Region DR1 and the second soluble region DR2). In some embodiments, the first soluble region DR1 does not overlap the second soluble region DR2. Furthermore, in some embodiments, the area of the cutting region SR is substantially equal to the sum of the area of the portion of the first soluble region DR1 located in the cutting region SR and the area of the second soluble region DR2 . On the other hand, a part of the photoresist layer PR in the chip region CR (that is, the first soluble region DR1 in the chip region CR) is transformed into a soluble state, while the other part (that is, the first soluble region DR1 shown in FIG. 2E The insoluble region (IDR) maintains an insoluble state.

Referring to FIG. 1 and FIG. 2F , proceed to step S112 for developing. In this way, all soluble regions of the photoresist layer PR (including the first soluble region DR1 and the second soluble region DR2 ) can be removed, while the photoresist layer PR located in the chip region CR remains The insoluble region within the IDR. In this way, the remaining part of the photoresist layer PR (that is, the insoluble region IDR) overlaps a part of the metal material layer M2a located in the chip region CR, and exposes the rest of the metal material layer M2a. In some embodiments, the developing process can be performed with a suitable developer, and the invention is not limited to the type of developer.

Referring to FIG. 1 and FIG. 2G, step S114 is performed, using the remaining part of the photoresist layer PR (that is, the insoluble region IDR) as a mask to remove the exposed part of the metal material layer M2a, thereby forming a second metal pattern M2. The location of the second metal pattern M2 corresponds to the location of the remaining portion of the photoresist layer PR (ie, the insoluble region IDR). It can be seen that the second metal pattern M2 is located in the chip region CR, and there is substantially no second metal pattern M2 in the cutting region SR. In some embodiments, the second metal pattern M2 may serve as a connection structure in the horizontal direction.

Subsequently, the remaining portion of the photoresist layer PR (ie, the insoluble region IDR) is removed. In some embodiments, the remaining portion of the photoresist layer PR may be removed by an ashing process.

Referring to FIG. 1 and FIG. 2H , step S116 is performed to form a third metal pattern M3 . Similar to the method of forming the first metal pattern M1, a dielectric layer D2 may be formed on the substrate 100 before forming the third metal pattern M3. Next, the dielectric layer D2 is patterned to form a plurality of openings V2. A part of the plurality of openings V2 is located in the chip region CR and exposes the second metal pattern M2, and another part is located in the cutting region SR. In some embodiments, the second opening V2 located in the cutting region SR may expose the first metal pattern M1. In other embodiments, the second opening V2 located in the cutting region SR may only expose the dielectric layer D1 without exposing the first metal pattern M1. Subsequently, a third metal pattern M3 is formed in the plurality of openings V2. It can be seen that a part of the third metal pattern M3 covers the top surface of the second metal pattern M2 in the chip region CR, and is electrically connected to the second metal pattern M2. Another part of the third metal pattern M3 is located in the cutting region SR and on the first metal pattern M1. The third metal pattern M3 may cover the top surface of the first metal pattern M1, or may not overlap the first metal pattern M1. In some embodiments, the third metal pattern M3 and the first metal pattern M1 may be made of the same or different materials, and the invention is not limited thereto. For example, the material of the third metal pattern M3 may include tungsten. In addition, similar to the first metal pattern M1, the third metal pattern M3 may also be a conductive plug or a conductive via.

Referring to FIG. 1 and FIG. 2I , step S118 may be optionally performed to form a fourth metal pattern M4 on the third metal pattern M3 in the chip region CR. In some embodiments, the method of forming the fourth metal pattern M4 is similar to the method of forming the second metal pattern M2 (as shown in FIG. 2B to FIG. 2G ), and will not be repeated here. The fourth metal pattern M4 is located in the chip region CR, and there is substantially no fourth metal pattern M4 in the cutting region SR. In some embodiments, the fourth metal pattern M4 covers the top surface of the third metal pattern M3 and is electrically connected to the third metal pattern M3. The material of the fourth metal pattern M4 includes a material that is not easy to etch or may produce etching by-products that are not easy to remove when it is etched together with its silicon-based material. For example, the material of the fourth metal pattern M4 may include aluminum. In addition, the fourth metal pattern M4 can serve as a connection structure in the horizontal direction.

In some embodiments, the same second photomask PM2 may be used in the processes of forming the second metal pattern M2 and forming the fourth metal pattern M4. In other words, in the above two stages of the process, substantially all parts of the metal material layer located in the cutting region SR are removed. In this way, both the formed second metal pattern M2 and the fourth metal pattern M4 are located in the chip region CR. On the other hand, the same or different first photomask PM1 can be used in the above two stages of manufacturing process. Therefore, the shape of the second metal pattern M2 may be equal to or different from the shape of the fourth metal pattern M4.

In some embodiments, the structures located in the chip region CR and including the first metal pattern M1 to the fourth metal pattern M4 may serve as components such as an interconnection structure, a seal ring, or a redistribution structure. On the other hand, the structure including the first metal pattern M1 and the third metal pattern M3 located in the cutting area SR may be a broken part of a test element group. The complete structure of the test device group may include the first metal pattern M1 and the third metal pattern M3 in the cutting area SR, and may further include the removed second metal pattern M2 and fourth metal pattern M4. It can be seen that the structure including the first metal pattern M1 and the third metal pattern M3 located in the cutting region SR shown in FIG. 2I may not be used as a test element group, or may only have a partial test function.

Referring to FIG. 1 and FIG. 2J , step S120 may be optionally performed to form a protection layer PL on the substrate 100 . The protection layer PL may be formed in the chip region CR and the cutting region SR. In some embodiments, a part of the protection layer PL located in the chip region CR covers the fourth metal pattern M4 and the top surface of the dielectric layer D2, and another part of the protection layer PL located in the cutting region SR covers the third metal pattern. M3 and the top surface of the dielectric layer D2. In some embodiments, the material of the protective layer PL may include silicon nitride, silicon oxide, silicon oxynitride and other insulating materials. A method of forming the protective layer PL may include a chemical vapor deposition method.

Referring to FIG. 1 and FIG. 2K , step S122 is performed to perform singulation along the dicing region SR to form the semiconductor chip 10 . In some embodiments, the singulation method includes a plasma dicing process. The plasma dicing process may include multiple etch-deposition-clean cycles, or may be referred to as a Bosch process. Since the materials (such as the second metal pattern M2 and the fourth metal pattern M4 ) that may hinder the etching process in the cutting region SR have been removed, the singulation process can be successfully completed through the plasma cutting process. In some embodiments, the edge E of the semiconductor chip 10 obtained by singulating can be the interface between the chip region CR and the cutting region SR shown in FIGS. 2A to 2J .

In summary, the embodiment of the present invention simultaneously removes the material layer in the dicing region that may hinder the etching process when forming the components in the semiconductor chip, so that the singulation step such as the plasma dicing process can be smoothly performed. In this way, the yield rate and production capacity of semiconductor chip packaging can be improved. In some embodiments, the method of simultaneously removing the material layer in the dicing area that may hinder the etching process while forming the components in the chip area includes exposing twice the photoresist used to pattern the material layer. The first exposure is used to define the predetermined pattern of the material layer in the chip region and the cutting region, and the second exposure is used to remove the predetermined pattern of the material layer in the cutting region. In this way, the material layer only forms a predetermined pattern in the chip area, and is substantially completely removed in the cutting area. In these embodiments, it is only necessary to add an additional exposure process in the predetermined process to remove the part of the material layer located in the cutting area without affecting the desired pattern of the material layer in the chip area, and without Need to change the mask design of the predetermined process. In other words, a significant increase in manufacturing cost can be avoided.

In some embodiments, the steps of forming the above-mentioned pattern only in the chip area can be repeated multiple times, and multiple second exposures in these steps can be performed through the same photomask (as shown in FIG. 2E ). Before the manufacturing process of the semiconductor chip reaches a stable state (that is, before the indicators such as yield, performance, and reliability meet the requirements), the above-mentioned second exposure step (as shown in FIG. 2E ) can be omitted, and a complete chip is formed in the cutting area. Test element set. In this way, the semiconductor chip can be inspected. Once the manufacturing process of the semiconductor chip reaches a steady state, the step of inspecting the semiconductor chip can be omitted. In other words, the method for manufacturing a semiconductor chip may include performing one or more steps of the above-mentioned second exposure (as shown in FIG. 2E ), so as to remove the material layer that may hinder the etching process in the cutting area, so as to improve the efficiency of the plasma cutting process. yield. In addition, the same photomask can be used for multiple second exposure steps, which avoids greatly increasing the manufacturing cost.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (11)

1. A method of manufacturing a semiconductor chip, comprising:

forming a dielectric layer on a chip region and a cutting region of a substrate, wherein the cutting region surrounds the chip region;

forming a first metal pattern in the dielectric layer, wherein the first metal pattern has the same height in the chip region and the cutting region;

forming a metal material layer on the dielectric layer and the first metal pattern, wherein the metal material layer completely covers the dielectric layer and the first metal pattern;

patterning the metal material layer to remove substantially all of the metal material layer within the cut region and a portion within the chip region, thereby forming a second metal pattern within the chip region;

forming a third metal pattern, wherein a first part of the third metal pattern covers the second metal pattern in the chip area, a second part of the third metal pattern is positioned on the first metal pattern in the cutting area, and the bottom surface of the first part is higher than the bottom surface of the second part; and

singulation is performed along the dicing regions to form the semiconductor chips,

wherein patterning the metal material layer comprises two exposures of a photoresist layer formed on the metal material layer using two different photomasks, and comprises a single removal of the metal material layer.

2. The method of manufacturing a semiconductor chip according to claim 1, wherein the method of patterning the metal material layer comprises:

forming a photoresist layer on the metal material layer;

performing first exposure on the photoresist layer to enable the photoresist layer to have a first soluble area, wherein the distribution range of the first soluble area is overlapped with the chip area and the cutting area;

performing a second exposure on the photoresist layer so that the photoresist layer also has a second soluble region, wherein the second soluble region is located within the cut region;

developing to remove the first soluble region and the second soluble region of the photoresist layer to expose the metal material layer;

removing the exposed part of the metal material layer by taking the residual part of the photoresist layer as a mask to form the second metal pattern; and

the remaining portion of the photoresist layer is removed.

3. The method of manufacturing a semiconductor chip according to claim 2, wherein the photoresist layer comprises a positive photoresist material.

4. The method for manufacturing a semiconductor chip according to claim 2, wherein the first soluble region does not overlap with the second soluble region.

5. The method of manufacturing a semiconductor chip according to claim 2, wherein a distribution range of the second soluble region does not overlap with the chip region.

6. The method for manufacturing a semiconductor chip according to claim 2, wherein an area of the dicing area is substantially equal to a sum of an area of a portion of the first soluble area located within the dicing area and an area of the second soluble area.

7. The method of manufacturing a semiconductor chip according to claim 1, wherein the first portion of the third metal pattern is electrically connected to the second metal pattern in the chip region.

8. The method of claim 1, wherein the singulation process comprises a plasma dicing process.

9. The method of manufacturing a semiconductor chip according to claim 1, wherein the material of the second metal pattern includes aluminum.

10. The method according to claim 1, wherein a material of the first metal pattern and the third metal pattern comprises tungsten.

11. The method of manufacturing a semiconductor chip according to claim 2, further comprising repeating the step of forming the metal material layer and the step of patterning the metal material layer a plurality of times, wherein the plurality of second exposures use the same photomask.

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