CN111033694B - Memory cell with oxide cap and spacer layer to protect floating gate from source implant - Google Patents

Abstract

A method of forming a memory cell, such as a flash memory cell, may include: (a) depositing polysilicon over a substrate; (b) depositing a mask over the polysilicon; (c) etching openings in the mask to expose the surface of the polysilicon (d) growing a floating gate oxide at the exposed polysilicon surface; (e) depositing an additional oxide over the floating gate oxide such that the floating gate oxide and the additional oxide together define an oxide cap; (f) shifting removing the masking material adjacent to the oxide mask; (g) etching away the remaining portion of the polysilicon not covered by the oxide mask, wherein the remaining portion of the polysilicon defines the floating gate; and (h) depositing a spacer layer between the oxide mask and above the floating gate. The spacer layer may include a shielding region aligned over at least one upwardly pointing tip region of the floating gate, which helps protect such tip region from subsequent source implantation processes.

Description

Features an oxide cap and spacer layer to protect the floating gate from source implants memory unit

Related Patent Applications

This patent application claims priority to commonly owned US Provisional Patent Application 62/564,174, filed September 27, 2017, which is hereby incorporated by reference in its entirety for all purposes.

technical field

The present disclosure relates to memory cells (eg, flash memory structures) that include at least one floating gate having an oxide cap (eg, flat top oxide cap) and an overlying spacer layer to protect the floating gate from Affected by the source implant process.

Background technique

Certain memory cells, such as flash memory cells, include at least one floating gate that is programmed and erased by one or more program/erase gates, word lines, or other conductive elements. Some memory cells use a common program/erase gate extending over the floating gate to program and erase the cell. In some implementations, the floating gate is formed from a Poly1 (Polysilicon 1) layer, while the program/erase gate is formed from a Poly2 (Polysilicon 2) layer that partially overlaps the underlying Poly1 floating gate in the lateral direction. For some memory cells, the fabrication process includes a floating gate thermal oxidation process that forms a football-shaped oxide over the Poly1 floating gate as discussed below.

1 illustrates a partial cross-sectional view of an example memory cell 10A, such as a flash memory, including a Poly1 floating gate 14 and an overlying football-shaped oxide region (“soccer-shaped oxide”) 16 formed over a substrate 12, and Poly2 gate 18 (eg, word line, erase gate or common program/erase gate) extending partially above floating gate 14 . A football-shaped oxide 16 is formed over the floating gate 14 by performing a thermal oxidation process on the floating gate 14 , which defines an upwardly pointing tip 15 at the edge of the floating gate 14 . One or more of these FG tips 15 may define a conductive coupling to an adjacent program/erase gate. For example, the FG tip 15 on the right side of the FG 14 shown in FIG. 1 may define a conductive coupling to the adjacent Poly2 gate 18 .

After forming the floating gate 14 and football-shaped oxide 16, a self-aligned source dopant implant through the lateral edges of the floating gate 14 may be performed, followed by an anneal process that outdiffuses the source dopant such that the resulting source region It extends partially below the floating gate 14 as shown in FIG. 1 . However, during source dopant implantation, a portion of the dopant may penetrate the football-shaped oxide 16 and into the underlying floating gate 14, which may result in one or more floating gate tips 15, for example, in a subsequent oxidation step (where Absorbed dopants in the floating gate 14 can promote oxidation) of the floating gate tip 15) followed by passivation or passivation. Such dulling or passivation of floating gate tip 15 may reduce the efficiency of erase and/or program operations of memory cell 10A.

2A and 2B illustrate example cross-sections taken at selected times during a conventional fabrication process of a conventional flash memory cell including multiple floating gates. As shown in Figure 2A, a Poly1 layer 30 may be deposited over a silicon substrate. A nitride layer may then be deposited and patterned using known techniques to form hard mask 32 . As shown in FIG. 2B , a floating gate oxidation process may then be performed, which forms a football-shaped oxide 16 (which in turn defines the floating gate 30 ) over the areas of the Poly1 layer 30 exposed through the nitride mask 32 . The nitride mask 32 can then be removed, followed by a plasma etch to remove the portion of Poly1 layer 30 not covered by each football ball oxide 16 and defining the lateral extent of each floating gate. This may be followed by source implantation and/or formation of the Poly2 layer (eg, to form word lines, erase gates, coupling gates, etc.) depending on the specific implementation.

3 shows an example mirrored memory cell 10B (eg, a SuperFlash ESF1 cell) that includes two spaced apart floating gates 14, a word line 20 formed over each floating gate 14, and a word line 20 formed between the two floating gates. And laterally extending source regions under the two floating gates, and bitlines 18 on each side of the cell and each contactable by a bitline contact (not shown). In this cell, the source may be formed after wordline 20 is formed, for example by a HVII implant followed by a diffusion process. During source implantation, the floating gate tip 15A, which is conductively coupled to the corresponding word line 20, is protected from the source dopant by the overlying word line 20. The inner floating gate tip 15B is relatively unprotected by the football-shaped oxide 16 and thus, as discussed above, may be passivated or passivated by dopants and subsequently oxidized. However, the inner floating gate tip 15B is not used for conductive coupling, and thus dulling/passivation of the floating gate tip 15B generally does not affect the operation of the cell.

Other types of cells include gates or other operational structures formed over the source region that utilize internal floating gate tip 15B for conductive coupling to floating gate 14 such as the cell shown in FIG. 4 .

FIG. 4 shows another example mirrored memory cell 10B (e.g., a SuperFlash ESF1+ cell) that includes two spaced apart floating gates 14, a word line 14 formed over each floating gate 14, and a word line formed between the two floating gates 14. A common erase gate or "coupling gate" 22 extending between the gates 14 and over the two floating gates 14 (so that the program and erase coupling to each respective floating gate 14 can be decoupled), and formed in the common erase source region under the gate. Inclusion of an erase gate may improve the cell shown in FIG. 3, for example, by providing lower operating voltages and enhanced scalability. The word lines 20 and the erase gate 22 may be simultaneously formed from a common polysilicon layer. With this cell structure, implanting the source region before forming word line 20 and erase gate 22 can result in passivation/passivation of all floating gate tips 15A and 15B since the tips can only be protected by football-shaped oxide 16 . Alternatively, implanting the source region after wordline 20 and erase gate 22 may require a very high kinetic implant in order to penetrate erase gate 22 and into substrate 12 . Such high power injections are generally expensive and may also lead to blunting/passivation of the floating gate tips 15A and/or 15B.

One proposed technique to protect the floating gate tip during source implantation performed before forming word lines and erase gates involves modifying typical source implant masks so that the implants are spaced slightly away from the floating gate edges. However, such techniques have disadvantages. First, the scaling of this type of memory cell is usually limited due to lithographic limitations. For example, for source injection, the space must be large enough to open reliably. Second, the overlapping alignment of the source implant masks is often imperfect, which introduces asymmetry into cell pairs.

Contents of the invention

Some embodiments of the present invention provide an oxide cap formed over a floating gate structure, and a spacer layer (eg, a nitride spacer) formed over the oxide cap and corresponding manufacturing methods, the spacer The layers help to protect the floating gates, in particular at least one of the floating gates pointing upwards to the tip region, during the subsequent source implantation process. In some embodiments, the oxide cap is relatively thick in the vertical direction and has a flat top, eg, as a result of a CMP process.

Some embodiments provide memory cells and corresponding fabrication methods incorporating such floating gate/oxide cap structures, such as nonvolatile memory cells (e.g., flash memory) that include a pair of floating gates, word lines formed over the gates, and a common erase/coupling gate formed between the floating gates and over the source regions. A pair of floating gate/oxide cap structures can be formed over the substrate, followed by spacer layer formation over the oxide cap, followed by source implantation (before forming word lines and erase/coupling gates) to form the source region. The spacer layer helps protect the upwardly pointing tip from source injection, reducing or eliminating the dulling or rounding of the tip that causes many conventional cells. Word lines and erase/coupling gates can then be formed over the structure, eg, by depositing and etching a poly-2 layer.

In some embodiments, the memory cell may be a SuperFlash non-volatile memory cell or a variant thereof (e.g., comprising a floating gate ESF1-type cells or variants thereof with erase/coupling gates formed between them).

Description of drawings

Exemplary aspects of the disclosure are described below with reference to the accompanying drawings, in which:

1 shows a partial cross-sectional view of an example memory cell, such as a flash memory, including a Poly1 floating gate with an overlying football-shaped oxide, and a Poly2 gate (e.g., word line, erase gate, etc.) extending over the floating gate. or common program/erase gate).

2A and 2B illustrate example cross-sections taken at selected times during a conventional fabrication process for a conventional flash memory cell including multiple floating gates;

3 illustrates an example mirrored memory cell including a pair of floating gates, a word line formed over each floating gate, and a source region formed between and extending below the floating gates.

Figure 4 shows another example mirrored memory cell comprising a pair of floating gates, a word line formed over each floating gate, and a common erase gate or " coupling grid";

5 illustrates a cross-section of an example memory cell structure including a flat-topped floating gate with an overlying flat-topped oxide region, according to an embodiment of the invention;

6A-6F illustrate an example flow for forming a flat top floating gate structure with protective nitride spacers as shown in FIG. 5, according to one embodiment of the present invention;

FIG. 7 illustrates an example flow for forming a flat top floating gate structure with protective nitride spacers as shown in FIG. 5 and performing source implantation in accordance with one embodiment of the present invention; and

8A and 8B illustrate a method for forming a flash memory having a pair of floating gates, a pair of word lines, and a common erase/coupling gate formed between the floating gates and over the source region, according to one embodiment of the present invention. An example flow of memory that includes the techniques shown in Figures 6A-6F.

Detailed ways

Figure 5 shows a cross-section of an example memory cell structure 100 including a flat-topped floating gate with an overlying flat-topped oxide region, according to an embodiment of the invention. The memory cell structure 100 includes a floating gate 104 formed over a substrate 102, a flat top oxide region or "oxide cap" 106 formed over the floating gate 104, and a spacer formed over the floating gate 104/oxide 106 structure. material layer 108 (eg, a nitride layer). The flat-top oxide region 106 may be formed by, for example, forming a "soccer-shaped oxide" over the floating gate structure using the processes shown in FIGS. 6A-6F discussed below or other similar or suitable processes followed by oxide deposition and processing, to jointly define a mesa region 106 . In some implementations, as discussed in more detail below with reference to FIG. 6F , the oxide region 106 may be relatively thick (in the vertical direction) compared to the underlying floating gate 104 .

Due to the shape of the floating gate structure, the spacer layer 108 may include a generally vertically extending region 108A aligned over the floating gate tip 15 . These vertically extending spacer layer regions 108A and thick oxide cap 106 can help protect the underlying floating gate tip 15 from receiving dopants during source implantation or other related dopant implantation processes, which can prevent or reduce Any blunting or degree of passivation of the floating gate tip 15 resulting from a doping process (eg, after a subsequent oxidation process), such as that discussed above in the Background. Additionally, the oxide cap 106 and spacers 108 can avoid any cell asymmetry issues by allowing the source implant to self-align the floating gate.

The example structure shown in FIG. 5 may be applied or incorporated into any suitable memory cell, such as a SuperFlash or other flash memory having one or more floating gates 104 . For example, FIGS. 7A and 7B discussed below illustrate an example process for forming a flash memory cell that includes forming a pair of floating gates formed as shown in FIG. The spacer layer region 108A adds protection to the underlying floating gate tip 15 from the doping process.

6A-6F illustrate an example flow for forming the flat top floating gate structure shown in FIG. 5 according to one embodiment of the present invention.

As shown in FIG. 6A , a gate oxide layer 202 may be grown or otherwise formed on a wafer substrate 202 . After further processing, a floating gate-defining polysilicon layer 204 may be deposited over gate oxide 202 . A masking layer 206 may be deposited over the polysilicon layer 204 , and the masking layer 206 may be patterned and etched to define an opening 210 exposing a top surface 212 of the polysilicon layer 204 . In this example embodiment, masking layer 206 includes silicon nitride.

As shown in FIG. 6B , floating gate oxide 220 is grown at exposed surface 210 of polysilicon 204 in silicon nitride opening 210 . As shown, floating gate oxide 220 may be grown in the shape of an ellipse or a football, and thus may be referred to as a "soccer-shaped oxide". Furthermore, floating gate oxide 220 may extend partially under silicon nitride region 206, eg, as indicated at 220A.

As shown in FIG. 6C , the region above floating gate oxide (soccer oxide) 220 and between silicon nitride region 206 may be filled with oxide 240 , eg, by HDP oxide deposition. Chemical mechanical planarization (CMP) may then be performed to remove the oxide from the top surfaces of the silicon nitride regions 206 , leaving HDP oxide only in the openings between the silicon nitride regions 206 as shown in FIG. 6 . Floating gate oxide (soccer oxide) 220 and HDDP oxide 240 may collectively define a mesa oxide region or “cap” 240 .

As shown in FIG. 6D , the remaining portions of the silicon nitride layer 206 may be removed, for example, by any suitable nitride removal process.

As shown in FIG. 6E , a floating gate etch may be performed to remove regions of the polysilicon layer 240 not covered by the oxide region 240 and thereby define a floating gate structure 244 at the lateral edges or perimeter of the floating gate structure 244. The prong has an upwardly directed tip region 246 . One or more of such floating gate tip regions 246 may define a conductive path to an adjacent gate, word line, etc. during operation of the memory cell comprising floating gate 244 . In some implementations, the floating gate etch can include a plasma etch process.

As shown in Figure 6F, a spacer film or layer 250, such as a silicon nitride spacer film, may be deposited over the structure. Due to the shape of floating gate 244 and overlying mesa region 240 , spacer layer 250 may define a vertically extending region or “shield region” 250A aligned over each floating gate tip region 246 . As discussed above with respect to FIG. 5, these vertical extensions 250A may add protection against doping of the underlying floating gate tip 246 during subsequent dopant implants (eg, during HVII source implants), which may prevent or reduce the Blunting of floating gate tip 246 occurs during conventional fabrication processes. In some implementations, the spacer layer 250 can be removed after dopant implantation. In other embodiments, the spacer layer 250 can be left in place.

Referring to FIG. 6F , in some embodiments, the process may be performed such that the oxide cap 240 is relatively thick (in the vertical height direction) compared to the underlying floating gate 240 . For example, in some embodiments, the maximum thickness or height H _OC of oxide cap 240 is greater than the maximum thickness or height _HFG of floating gate 244 . In some embodiments, the oxide cap height H _OC is at least 1.5 times the floating gate height _HFG . In a specific embodiment, the oxide cap height _HOC is at least 2 times the floating gate height _HFG .

Referring to FIG. 6F , in some embodiments, the process may be performed such that the vertical height of each masked region 250 of the spacer layer 250A indicated at H _SR is greater than the lateral width of the corresponding shielded region 250A indicated at W _SR . In some embodiments, the shield height H _SR is at least 1.5 times the shield width W _SR . In some embodiments, the shielding region height H _SR is at least 2 times the shielding region width W _SR . In some embodiments, the shield height H _SR is at least 3 times the shield width W _SR .

FIG. 7 shows an example flowchart 300 for forming a flat-top floating gate structure with protective nitride spacers as shown in FIG. 5 and performing source implants, according to one embodiment of the present invention. At 302, gate cleaning and oxidation are performed on the top surface of the wafer substrate. At 304, a layer of FG polysilicon (Poly1) is deposited over the substrate. At 306, a FG polysilicon implant is performed. At 308, FG nitride cleaning and deposition is performed. At 310, a FG photoresist is formed and patterned, and a FG nitride etch is performed. At 312, photoresist stripping is performed. At 314, the structure is cleaned and FG oxidation is performed.

At 316, an HDP oxide deposition is performed over the floating gate structure, wherein the oxide thickness is selected, for example, at to /> within the range of the /> to /> to, or within /> to In the range. At 318, FG oxide CMP is performed, for example, to leave approximately The depth of the nitride layer. At 320, FG nitride removal, such as a dry or wet removal process, may be performed. In one embodiment, for example, a plasma etch is performed to remove about the nitride thickness. At 322, a photoresist (eg, polyoxide polysilicon or "POP" photoresist) is formed and patterned, and a FG etch is performed. At 324, photoresist stripping is performed.

At 326, the structure is cleaned and a second gate oxide oxidation is performed. At 328, channel oxide deposition (HTO) is performed. At 330, an HTO anneal is performed. At 332, a medium voltage (MV) gate oxide photoresist is formed. At 334, the photoresist is stripped, and the structure is cleaned. In some implementations, an oxide "leaching" process may be performed to remove remaining oxide, such as using hydrofluoric acid, so that the exposed silicon surface can be oxidized again.

At 336, MV gate oxidation is performed. At 338, FG spacer nitride is deposited. At 340, the FG spacer nitride can be etched. At 342, source photoresist can be deposited, patterned, and etched to protect selected areas of the structure, and HVII source implantation is performed. As discussed above, the FG nitride spacers may include vertical extensions aligned over the upper corners or tips of the floating gate, which act as a shield to prevent HVII dopants from penetrating down into the FG polysilicon, thereby maintaining the floating gate Sharpness of the tip. Photoresist stripping can then be performed. At 344, the FG nitride spacer can be removed for subsequent processing of the cell. For example, a channel oxide layer may be grown over the structure, followed by subsequent deposition and etching of a poly2 layer to form word lines, erase gates, and/or other program or erase nodes.

FIGS. 8A and 8B illustrate a method for forming a flash memory having a pair of floating gates, a pair of word lines, and a common erase/coupling gate formed between the floating gates and over the source region, according to one embodiment of the present invention. The steps of an example flow of the memory include the techniques shown in FIG. 6A to FIG. 6F and/or FIG. 7 .

As shown in FIG. 8A, a pair of floating gates 444 having an overlying flat-topped oxide region 440 are formed over substrate 400, and spacers are deposited over the flat-topped floating gate structure, eg, using any of the techniques disclosed herein. layer (eg silicon nitride layer) 450 . A source implant (eg, HVII implant) can then be performed as shown to define the source region (eg, after source dopant diffusion through the substrate). As discussed above, spacer layer region 450A aligned over floating gate tip 446 can help protect floating gate tip 446 from source implants, which can prevent or reduce blunting of floating gate tip 446 as discussed above.

As shown in FIG. 8A, a pair of floating gates 444 having an overlying flat-topped oxide region 440 are formed over substrate 400, and spacers are deposited over the flat-topped floating gate structure, eg, using any of the techniques disclosed herein. layer (eg silicon nitride layer) 450 . A source implant (eg, HVII implant) can then be performed as shown to define the source region (eg, after source dopant diffusion through the substrate). As discussed above, spacer layer region 450A aligned over floating gate tip 446 and thick oxide cap 440 can protect floating gate tip 446 from source implants, which can prevent or reduce floating gate tip 446 as discussed above. blunt.

As shown in FIG. 8B , after removal of the nitride spacer layer 450 , a polysilicon layer (eg, poly=2 layer) may be deposited and etched to define a corresponding wordline (WL ), and an erase gate or "coupled gate (EG/CG)" is defined over the inner edge of the floating gate and over the underlying source region. The structure shown in FIG. 8B may be defined by or associated with a SuperFlash memory cell (eg, SuperFlash EFS1+ cell, or EFS1 erase cell) of Microchip Technology, Inc., headquartered at 2355W Chandler Blvd, Chandler, AZ 85224. In this way, source implantation may be performed prior to forming the polysilicon 2 layer, for example including word lines WL and/or erase/coupling gates. This may allow lower source implant energies and also allow process tuning for variable width spacers. Allowing control of these process parameters may also add control over the source implant diffusion length (eg, lateral diffusion distance) below each respective floating gate, thereby controlling one or more operating parameters of the resulting memory cell.

Claims (15)

1. A method of forming a memory cell structure, the method comprising:

forming a polysilicon layer over a substrate;

depositing a mask material over the polysilicon layer;

etching an opening in the mask material to expose a top surface of the polysilicon layer;

growing a floating gate oxide at the exposed top surface of the polysilicon layer;

depositing an additional oxide in the openings in the mask material and over the floating gate oxide, wherein the floating gate oxide and the additional oxide together define an oxide cap;

removing masking material adjacent lateral sides of the oxide cap;

performing a floating gate etch to remove portions of the polysilicon layer not covered by the oxide cap, wherein a remaining portion of the polysilicon layer defines a floating gate structure comprising an upwardly directed floating gate tip;

depositing a spacer layer over the oxide cap and underlying floating gate structure, wherein the spacer layer includes a shielding region laterally aligned over the upwardly directed floating gate tip;

performing a source implant to form a source region in the substrate, wherein the shielding region of the spacer layer shields the underlying floating gate tip in the source implant; and

an erase gate or coupling gate formed over the source region in the substrate and adjacent to the upwardly directed floating gate tip is formed after the source implant.

2. The method of claim 1, wherein the oxide cap is formed with a flat top surface.

3. The method of claim 1, comprising performing Chemical Mechanical Planarization (CMP) on the additional oxide to define a flat top surface of the oxide cap.

4. The method of claim 1, wherein the spacer layer comprises silicon nitride.

5. The method of claim 1, wherein the shielding region of the spacer layer extends vertically.

6. The method of claim 5, wherein a vertical height of the vertically extending shielding region of the spacer layer is greater than a lateral width of the shielding region.

7. The method of claim 6, wherein the vertical height of the vertically extending shielding region of the spacer layer is at least twice the lateral width of the shielding region.

8. The method of claim 6, wherein the vertical height of the vertically extending shielding region of the spacer layer is at least three times the lateral width of the shielding region.

9. A method of forming a memory cell structure, the method comprising:

forming a polysilicon layer over a substrate;

depositing a mask material over the polysilicon layer;

etching a pair of openings in the mask material to expose a pair of top surface regions of the polysilicon layer;

growing a floating gate oxide at each exposed top surface of the polysilicon layer;

depositing an additional oxide in each of the pair of openings in the mask material and over each respective floating gate oxide, wherein each floating gate oxide and the additional oxide deposited over the floating gate oxide together define an oxide cap;

removing mask material adjacent to lateral sides of each oxide cap;

performing a floating gate etch to remove portions of the polysilicon layer not covered by each oxide cap, wherein a remaining portion of the polysilicon layer defines a pair of spaced apart floating gate structures, each floating gate structure of the pair of floating gate structures including an upwardly directed floating gate tip;

depositing a spacer layer comprising a shielding region laterally aligned over the upwardly directed floating gate tips of each floating gate structure;

performing a source implant between the pair of floating gate structures, wherein the shielding regions of the spacer layer aligned over each upwardly directed floating gate tip shield an underlying floating gate tip in the source implant; and

an erase gate or coupling gate is formed over the source region and adjacent to the upwardly directed floating gate tips of the pair of floating gate structures after the source implant.

10. The method of claim 9, wherein each oxide cap is formed with a flat top surface.

11. A method of forming a memory cell structure, the method comprising:

forming a floating gate over a substrate;

forming an oxide cap over the floating gate by:

growing an elliptical oxide region at a top surface of the floating gate, wherein growing the elliptical oxide region defines first and second upwardly-directed tip regions of the floating gate at opposite lateral sides of the floating gate; and

depositing an upper oxide region on top of the elliptical oxide region;

wherein the deposited upper oxide region has a smaller lateral width than an underlying floating gate at each of the opposite lateral sides of the floating gate such that at each of the opposite lateral sides of the floating gate, vertically extending sidewalls of the upper oxide region are offset from vertically extending sidewalls of the underlying floating gate in a direction toward a center of the floating gate.

12. The method of claim 11, wherein the upper oxide region of the oxide cap has a flat top surface.

13. The method of claim 11, further comprising forming a spacer layer over the oxide cap and underlying floating gate, wherein the spacer layer comprises a shielding region laterally aligned over an upwardly directed tip region of the floating gate, the shielding region configured to protect the floating gate tip region during a dopant implantation process.

14. The method of claim 11, further comprising:

forming a spacer layer over the oxide cap and underlying floating gate, wherein the spacer layer includes a shielding region laterally aligned over each of the first and second upwardly-directed tip regions of the floating gate, and the shielding region is configured to protect the first and second upwardly-directed tip regions during a dopant implantation process;

forming a word line adjacent to the first upwardly directed tip region, the word line configured for a read operation or a write operation by the first upwardly directed tip region and the word line; and

an erase gate is formed adjacent the second upwardly directed tip region, the erase gate configured for an erase operation by the second upwardly directed tip region and the erase gate.

15. A memory cell structure formed by the method of any of claims 1-14.