CN111030676A - Frequency division method and realization circuit for any integer clock with dynamically configurable coefficient - Google Patents
Frequency division method and realization circuit for any integer clock with dynamically configurable coefficient Download PDFInfo
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- CN111030676A CN111030676A CN201911380468.7A CN201911380468A CN111030676A CN 111030676 A CN111030676 A CN 111030676A CN 201911380468 A CN201911380468 A CN 201911380468A CN 111030676 A CN111030676 A CN 111030676A
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- H03K21/00—Details of pulse counters or frequency dividers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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Abstract
The invention discloses a clock frequency division circuit, which comprises a comparison unit, a frequency division coefficient synchronization unit, a modulus settable counter, a frequency division coefficient unit, an even frequency division unit, an odd frequency division unit and a combination unit, wherein the even frequency division unit and the odd frequency division unit respectively work independently and output a target clock after passing through the combination unit. The invention also provides a clock frequency division method, which comprises the following steps: when the frequency division coefficient configuration is changed, the frequency division coefficient configuration is synchronized and then transmitted into the module settable counter and the frequency division coefficient unit; the mode-settable counter can repeatedly count down by taking the mode as a mode, and updates and controls to write in the frequency division coefficient unit when the counter is zero; and carrying out burr-free combination on the odd frequency division clock and the even frequency division clock to obtain a target clock. The clock frequency division method and the circuit can carry out arbitrary integer frequency division on the reference clock, the frequency division coefficient can be dynamically configured at any time, the target clock has no burr and the duty ratio is 50%, the circuit structure is simple, and the occupied resources are less.
Description
Technical Field
The invention belongs to the field of clock frequency division in a digital integrated circuit, and particularly relates to a method for dividing frequency of any integer clock with dynamically configurable coefficient and a realization circuit.
Background
In digital system design, a clock signal is one of the most important signals, and a frequency divider is often used to divide a clock signal of a given frequency to obtain a clock signal of a desired frequency. In some designs, the system requires not only simple frequency division, but also dynamic adjustment of the frequency and glitch-free switching.
Therefore, in practical application, various clock dividing circuits need to be designed. According to the division result, it can be divided into odd division, even division and fractional division. The clock duty cycle resulting from fractional division is mostly not 50%, which may introduce difficulties for timing convergence. The odd-numbered frequency division with the duty ratio of 50% mostly adopts 2 modulo-N counters which are triggered by the rising edge and the falling edge of a clock respectively, and then 2 unequal duty ratio signals are subjected to phase inversion or phase inversion to realize equal duty ratio odd-numbered frequency division. The principle is simple but the signals generated by the combinational logic are prone to glitches, the so-called race hazard.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a clock frequency division method, which can implement any integer frequency division with dynamically configurable coefficients for a reference clock, wherein output clocks are switched without glitches under different frequency division coefficients, and the duty ratio is 50%.
Because the even frequency division is simple to realize and the odd frequency division is complex, the invention adopts a structure of separating the odd frequency division from the even frequency division. When the frequency divider is configured to divide by even numbers, the comparison result of the modulus settable counter and the frequency dividing coefficient is matched with a one-bit register to realize the frequency divider. When the frequency division coefficient changes among even numbers, the output even frequency division clock changes along with the change, and the even frequency division clock always has equal duty ratio. At this time, the odd frequency dividing unit does not operate.
When odd frequency division is carried out, the traditional method that 2 modulus N counters are triggered by rising edges and falling edges of clocks respectively to output unequal duty ratio signal phase-AND is not adopted. The circuit structure comprising a control unit and two latches is designed to realize the operation, a first control signal and a second control signal are generated according to a specific algorithm by using the value of a modulo settable counter and a frequency division coefficient, wherein the first control signal is used as an enable signal of the first latch to deduct specific pulses of a reference clock, the clock signal output by the first latch is deducted specifically by the second control signal, and finally an odd frequency division clock with equal duty ratio is obtained. When the frequency division coefficient is changed between odd numbers, the odd frequency division clock can be changed without burrs. At this time, the even-numbered frequency-dividing unit does not operate.
When the frequency division coefficient is randomly changed among any integer, the combination unit can control the glitch-free switching output of the odd frequency division clock and the even frequency division clock, and finally the glitch-free frequency division clock with the same duty ratio is output.
Another objective of the present invention is to provide an integer frequency divider circuit, which can divide the frequency of a reference clock with a small amount of logic resources, and has a simple circuit structure and a low system cost. The clock frequency dividing circuit structure of the invention comprises:
and the comparison unit is used for comparing the input frequency division coefficient with the current frequency division coefficient and outputting an indication signal when the input frequency division coefficient and the current frequency division coefficient are different.
The frequency division coefficient synchronizer is used for synchronously processing the input frequency division coefficient, synchronizing the frequency division coefficient which is possibly asynchronously configured to a reference clock domain and preventing a metastable state;
the module-settable counter is used for counting based on an input reference clock, and reading the frequency division coefficient again to start counting down after the module value (namely the frequency division coefficient) is reduced to zero from the set module value;
a frequency division coefficient unit for storing the synchronized frequency division coefficient and controlling the writing time by the modulo settable counter 2;
the even number frequency division unit is used for controlling the turnover of the output signal according to the count value of the counter and outputting an even number frequency division clock;
the odd frequency division unit is used for generating an odd frequency division clock with equal duty ratio according to the frequency division coefficient and the count value control, and is used for outputting sequential logic without burrs;
and the combination unit is used for outputting the combination of the input odd frequency division clock and the input even frequency division clock without burrs.
Wherein, the odd frequency division unit internally includes:
the control unit carries out multiple logic comparisons according to the modulus settable counter and the frequency division coefficient unit and outputs a first control signal and a second control signal;
the first latch, according to the clock signal of the deduction part pulse of the first control signal generation of input;
and the second latch generates an odd-frequency-division clock with the final equal duty ratio according to the input second control signal and the clock signal.
Compared with the prior art, the method for dividing the frequency of any integer clock with dynamically configurable coefficient and the implementation circuit have the following advantages:
(1) the circuit of the invention has simple structure and small occupied resource, and only uses less than 30 registers and a small amount of combinational logic within the frequency division range of 1-32. Only a small number of registers are added along with the expansion of the frequency division range;
(2) the frequency division coefficient of the invention can be dynamically configured, and the frequency division coefficient can be configured and modified at any time no matter the configuration is from a synchronous or asynchronous clock domain, and the frequency division coefficient synchronization unit can ensure that no burr exists in the configuration process;
(3) the odd frequency division unit outputs the odd frequency division clock by the time sequence device latch, so that the odd frequency division clock is ensured to be free of burrs;
(4) the odd frequency division unit of the invention adopts a clock pulse deduction method, so that any odd frequency division can output equal duty ratio of clocks;
(5) the design combination unit of the invention can ensure that two paths of clock signals are switched without burrs when the frequency division coefficient is randomly changed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a diagram of a clock divider circuit;
FIG. 2 is a diagram of the internal structure of an odd frequency-dividing unit;
FIG. 3 is a timing diagram of the final output clock of the present invention.
Description of reference numerals:
1-a comparison unit; 2-a division factor synchronization unit; 3-modulo settabie counter; 4-division factor unit; 5-an even frequency division unit; 6-odd frequency division unit; 61-a control unit; 62-a first latch; 63-a second latch; 7-a combination unit.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
As shown in fig. 1-3, the circuit and operation of the present invention are as follows:
after the reset, all register values in the units 1 to 7 are 0, so that the initial default frequency division coefficient is 1 frequency division, namely, the frequency division is not carried out, and the output clocks clk _ out are consistent with clk _ ref;
the first input end of the comparison unit 1 is connected with the multi-bit input signal div _ para [ N:0], the second input end is connected with the output of the frequency division coefficient synchronization unit 2, and the output end is connected with the first input end of the frequency division coefficient synchronization unit 2. When the frequency division coefficient configuration is changed, the multi-bit input signal div _ para [ N:0] is changed, and the output signal of the comparison unit 1 jumps;
the second input terminal of the division coefficient synchronization unit 2 is connected to the multi-bit input signal div _ para [ N:0 ]. After the division coefficient synchronization unit 2 performs synchronization processing on the indication signal transmitted from the comparison unit 1, the control internal register div _ sync [ N:0] is used to sample the signal div _ para [ N:0] at the second input end. div _ sync [ N:0] is connected as an output of the division coefficient synchronization unit 2 to the modulo settable counter 3 and the division coefficient unit 4.
The first output of the modulo settable counter 3 is connected to the second input of the frequency division coefficient unit 4, and the second output is connected to the first input of the even frequency division unit 5 and the odd frequency division unit 6. The modulo settable counter 3 samples the incoming div _ sync [ N:0] signal at the time when its value is zero and sends a pulse signal to the frequency division coefficient unit 4.
The output of the frequency division coefficient unit 4 is connected with the second input ends of the even frequency division unit 5 and the odd frequency division unit 6. The frequency division coefficient unit 4 samples the div _ sync [ N:0] signal at the first input under the control of the pulse signal of the modulo settable counter 3.
The even frequency division unit 5 judges that the frequency division is odd frequency division according to the input frequency division coefficient signal, the frequency division does not work, and the output length is 1; when the frequency is even frequency division, according to the comparison result of the real-time count value of the modulus settable counter 3 and the frequency division coefficient, when the half of the modulus is less than 0 and the half of the modulus is greater than 1, the output signal of the register in the even frequency division unit 5 forms an even frequency division clock. The output signal is connected to a first input of the combination unit 7.
The odd frequency division unit 6 judges whether even frequency division is performed according to the input frequency division coefficient signal, and does not work and outputs the length of 1; for odd frequency division, the control unit 61 outputs the first control signal and the second control signal according to the specific determination logic of the real-time count value of the modulo settable counter 3 and the frequency division coefficient of the frequency division coefficient unit 4. The first control signal is connected to an enable terminal of the first latch 62, a clock terminal of the first latch 62 is connected to the reference clock clk _ ref, and an output terminal is connected to a clock terminal of the second latch 63. The first control signal and the reference clock clk _ ref output a clock signal with partial pulse being latched after logic action occurs in the latch. The enable terminal of the second latch 63 is connected to the second control signal, and then performs specific subtraction on the input clock signal pulse, outputs the odd-numbered clock with equal duty ratio as the output signal of the odd-numbered frequency dividing unit 6, and is connected to the second input terminal of the combining unit 7.
The combining unit 7 is composed of two not gates and one nand gate, and combines the two input signals to output the final frequency division clock clk _ out.
When the division coefficient signal changes again, the above steps are repeated.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A clock divider circuit, comprising: the device comprises a comparison unit, a frequency division coefficient synchronization unit, a modulus settable counter, a frequency division coefficient unit, an even frequency division unit, an odd frequency division unit and a combination unit;
the comparison unit is connected with the frequency division coefficient synchronization unit and used for comparing the input frequency division coefficient with the current frequency division coefficient and outputting an indication signal when the input frequency division coefficient is different from the current frequency division coefficient;
the frequency division coefficient synchronization unit is connected with the modular configurable counter and the frequency division coefficient unit and is used for synchronously processing the input frequency division coefficient and synchronizing the frequency division coefficient which is possibly asynchronously configured to a reference clock domain;
the modular counter is connected with the frequency division coefficient unit, the even frequency division unit and the odd frequency division unit and used for counting down based on an input reference clock, and when the modular value is reduced to zero from the set modular value, the frequency division coefficient is read again and counting down is started;
the frequency division coefficient unit is connected with the even frequency division unit and the odd frequency division unit, is used for storing the synchronized frequency division coefficient, and controls the writing time by the modular settable counter;
the even number frequency division unit is connected with the combination unit and used for controlling the turnover of the output signal according to the count value of the counter and outputting an even number frequency division clock;
the odd frequency division unit is connected with the combination unit, is used for generating an odd frequency division clock with equal duty ratio according to the frequency division coefficient and the count value control, and is used for sequential logic output without burrs;
and the combination unit is used for outputting the combination of the input odd frequency division clock and the input even frequency division clock without burrs.
2. The clock divider circuit of claim 1, wherein: the odd frequency division unit includes:
the control unit is used for carrying out various logic comparisons according to the modulus settable counter and the frequency division coefficient unit and outputting a first control signal and a second control signal;
the first latch is used for generating a clock signal for deducting part of pulses according to an input first control signal;
and the second latch is used for generating the odd-frequency-division clock with the final equal duty ratio according to the input second control signal and the clock signal.
3. The clock divider circuit of claim 1, wherein: the comparison unit and the frequency division coefficient synchronization unit can reduce the occurrence probability of the metastable state.
4. A method of clock division, characterized by: the method comprises the following steps:
step S1: comparing the input frequency division coefficient with the current frequency division coefficient by using a comparison unit, and outputting an indication signal when the input frequency division coefficient is inconsistent with the current frequency division coefficient;
step S2: the frequency division coefficient synchronization unit is used for carrying out synchronous processing on the input frequency division coefficient, and synchronizing the frequency division coefficient which is possibly asynchronously configured to a reference clock domain;
step S3: adopting a method of controlling the writing-in of the frequency division coefficient by a modular settable counter, and updating a frequency division coefficient unit and a self module value when the counter is cleared;
step S4: respectively obtaining an even frequency division clock and an odd frequency division clock by adopting a method of separately realizing odd frequency division and even frequency division;
step S5: and performing glitch-free combination on the odd frequency division clock and the even frequency division clock obtained in the step S4 through a combination unit to obtain a target clock.
5. A clock division method according to claim 4, wherein: in step S3, only when the modulo settable counter ends one frequency division cycle, a new frequency division coefficient is written into the frequency division coefficient unit and the modulo settable counter, so as to ensure the integrity of the target clock cycle.
6. A clock division method according to claim 4, wherein: in step S4, when it is determined that the input frequency division coefficient is even frequency division, the even frequency division unit operates, and the odd frequency division unit outputs a length of 1; when the frequency division coefficient is judged to be odd frequency division, the odd frequency division unit works, and the even frequency division unit outputs the length of 1.
7. A clock division method according to claim 4, wherein: in step S4, the odd-numbered frequency division method for uniformly subtracting pulses on the falling edge of the reference clock by using two-stage latches includes the following steps:
s401: generating a first control signal and a second control signal by using the frequency division coefficient and the real-time changing counting value;
s402: uniformly deducting specific pulses from a reference clock by using a first control signal as an enabling signal of a first latch;
s403: and (4) taking the output signal of the step (S402) as a clock signal of the second-stage latch, deducting the clock signal by using a second control signal, and finally outputting the odd-numbered frequency division clock by using the second latch to ensure no burr.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580279A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
| CN114518781A (en) * | 2022-01-07 | 2022-05-20 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN114756419A (en) * | 2022-06-15 | 2022-07-15 | 南京芯驰半导体科技有限公司 | Reference clock abnormity self-checking circuit and method |
| CN118487593A (en) * | 2024-07-10 | 2024-08-13 | 此芯科技(无锡)有限公司 | Clock frequency division circuit, system on chip and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1485985A (en) * | 2002-09-24 | 2004-03-31 | 华为技术有限公司 | Clock frequency dividing method and its implementation circuit |
| CN101997540A (en) * | 2009-08-11 | 2011-03-30 | 深圳市英威腾电气股份有限公司 | FPGA (Field Programmable Gata Array) based method for realizing fractional frequency division and fractional frequency divider |
| CN102035540A (en) * | 2010-11-19 | 2011-04-27 | 长沙景嘉微电子有限公司 | Programmable 50%-duty cycle frequency divider |
| US20130243148A1 (en) * | 2010-09-28 | 2013-09-19 | Texas Instruments Incorporated | Integer and Half Clock Step Division Digital Variable Clock Divider |
| JP2015139103A (en) * | 2014-01-22 | 2015-07-30 | 学校法人東海大学 | variable frequency divider |
| CN107563020A (en) * | 2017-08-17 | 2018-01-09 | 郑州云海信息技术有限公司 | A kind of clock frequency division module design method based on CPLD/FPGA |
-
2019
- 2019-12-27 CN CN201911380468.7A patent/CN111030676A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1485985A (en) * | 2002-09-24 | 2004-03-31 | 华为技术有限公司 | Clock frequency dividing method and its implementation circuit |
| CN101997540A (en) * | 2009-08-11 | 2011-03-30 | 深圳市英威腾电气股份有限公司 | FPGA (Field Programmable Gata Array) based method for realizing fractional frequency division and fractional frequency divider |
| US20130243148A1 (en) * | 2010-09-28 | 2013-09-19 | Texas Instruments Incorporated | Integer and Half Clock Step Division Digital Variable Clock Divider |
| CN102035540A (en) * | 2010-11-19 | 2011-04-27 | 长沙景嘉微电子有限公司 | Programmable 50%-duty cycle frequency divider |
| JP2015139103A (en) * | 2014-01-22 | 2015-07-30 | 学校法人東海大学 | variable frequency divider |
| CN107563020A (en) * | 2017-08-17 | 2018-01-09 | 郑州云海信息技术有限公司 | A kind of clock frequency division module design method based on CPLD/FPGA |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580279A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
| CN114518781A (en) * | 2022-01-07 | 2022-05-20 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN114518781B (en) * | 2022-01-07 | 2024-05-14 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN114756419A (en) * | 2022-06-15 | 2022-07-15 | 南京芯驰半导体科技有限公司 | Reference clock abnormity self-checking circuit and method |
| CN118487593A (en) * | 2024-07-10 | 2024-08-13 | 此芯科技(无锡)有限公司 | Clock frequency division circuit, system on chip and electronic equipment |
| CN118487593B (en) * | 2024-07-10 | 2024-11-08 | 此芯科技(无锡)有限公司 | Clock frequency division circuit, system on chip and electronic equipment |
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