CN111025130A - A SMT detection method for multi-layer interconnected FPC - Google Patents
A SMT detection method for multi-layer interconnected FPC Download PDFInfo
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- CN111025130A CN111025130A CN202010013513.1A CN202010013513A CN111025130A CN 111025130 A CN111025130 A CN 111025130A CN 202010013513 A CN202010013513 A CN 202010013513A CN 111025130 A CN111025130 A CN 111025130A
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- 238000001514 detection method Methods 0.000 title claims abstract description 11
- 238000012360 testing method Methods 0.000 claims abstract description 120
- 238000003466 welding Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000002159 abnormal effect Effects 0.000 claims abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract 1
- 102100035731 Protein-arginine deiminase type-4 Human genes 0.000 description 46
- 101100272964 Arabidopsis thaliana CYP71B15 gene Proteins 0.000 description 8
- 101100406797 Arabidopsis thaliana PAD4 gene Proteins 0.000 description 8
- 101150030164 PADI3 gene Proteins 0.000 description 8
- 101150094373 Padi4 gene Proteins 0.000 description 8
- 102100035734 Protein-arginine deiminase type-3 Human genes 0.000 description 8
- 101150097440 PADI6 gene Proteins 0.000 description 5
- 102100035732 Protein-arginine deiminase type-6 Human genes 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012956 testing procedure Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The SMT detection method for the multilayer interconnected FPC, provided by the invention, has the advantages of simple steps, convenience and rapidness in operation and good safety isolation effect on circuits on the board. The method comprises the following steps: a. at least two main test PADs (3) and auxiliary test PADs (4) which are correspondingly superposed one by one are respectively arranged at the periphery of the main connection PAD and the auxiliary connection PAD; b. the main test PAD and the main connection PAD and the auxiliary test PAD and the auxiliary connection PAD are arranged in an isolated non-electrical connection mode; c. a resistance testing device (5) is connected between the main testing PAD and the auxiliary testing PAD to read the resistance value between the main testing PAD and the auxiliary testing PAD; d. and c, comparing the resistance value measured in the step c with the known resistance value under the normal welding condition, and judging whether the PAD welding is abnormal or not. The invention is used in the field of circuit boards.
Description
Technical Field
The invention relates to the field of circuit board detection, in particular to an SMT detection method for a multilayer interconnected FPC (flexible printed circuit).
Background
SMT (abbreviation of Surface Mounted Technology) is an abbreviation for Surface mount Technology. With the development of electronic technology, especially small electronic products, circuit boards, especially FPC boards (flexible circuit boards) that can save space, are increasingly used. FPCs have also evolved into multi-layer interconnect structures. At present, the connection between the FPC and the FPC is generally realized by external electrical connection to achieve electrical conduction. However, this method requires a large space and is difficult to mass-produce in a very small space. The above problems are well solved by SMT technology. In the current SMT chip mounting technology, after the chip mounting is completed, the welding conduction operation between the pads needs to be performed. After the SMT soldering of the multi-layer FPC is completed, a cold solder or incomplete solder (soldering defect) may occur due to the maturity of the technology and problems of the operator or the automatic soldering apparatus. Therefore, it is necessary to check the connection state of the multi-layer FPC after soldering. At present, the welded FPC is generally directly subjected to pad electrifying detection. However, the mode has potential safety hazards, for example, due to the welding problems, the whole electrified FPC board has short circuit or other faults, and the whole FPC board has more faults or even is scrapped. At present, no effective method is available for ensuring the welding quality of the welding pad of the FPC rapidly under the condition of ensuring the safety of the FPC product.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide the SMT detection method for the multilayer interconnected FPC, which has simple steps, is convenient and fast to operate and plays a good role in safely isolating circuits on a board.
The technical scheme adopted by the invention is as follows: in the method of the present invention, the multilayer interconnected FPC includes a main FPC provided with a main connection PAD (PAD) and at least one auxiliary FPC provided with an auxiliary connection PAD, the main connection PAD and the auxiliary connection PAD are correspondingly fitted, and the method includes the steps of:
a. at least two main test PADs and at least two auxiliary test PADs which are correspondingly superposed one by one at the positions of the main FPC and the auxiliary FPC after the main FPC and the auxiliary FPC are jointed are respectively arranged at the peripheries of the main connection PADs and the auxiliary connection PADs;
b. the main test PAD and the main connection PAD and the auxiliary test PAD and the auxiliary connection PAD are arranged in an isolated non-electrical connection mode, and the set distance of each main test PAD relative to the main connection PAD and the set distance of each auxiliary test PAD relative to the auxiliary connection PAD are fixed values;
c. connecting a resistance testing device between the main testing PAD and the auxiliary testing PAD, and reading the resistance value between the main testing PAD and the auxiliary testing PAD through the resistance testing device;
d. and c, comparing the resistance value measured by the resistance testing device in the step c with the known resistance value under the normal welding condition, judging that the PAD welding abnormity exists when the resistance value measured by the resistance testing device is larger than the known resistance value under the normal welding condition, and if not, indicating that the welding is normal.
According to the scheme, when the PADs of the FPC are detected, the main test PADs and the auxiliary test PADs which are coincided one by one in a one-to-one correspondence mode are respectively arranged on the peripheries of the main connection PADs and the auxiliary connection PADs on the FPC, and the main test PADs and the main connection PADs and the auxiliary test PADs and the auxiliary connection PADs are in isolated non-electrical connection arrangement, so that the test PADs are isolated from the original main connection PADs and the original auxiliary connection PADs on the PFC; the setting distance of each main test PAD relative to the main connection PAD and the setting distance of each auxiliary test PAD relative to the auxiliary connection PAD are fixed values, this ensures that the distance between the main test PAD and the main connection PAD, and the distance between the auxiliary test PAD and the auxiliary connection PAD are a standard fixed value, and by detecting the alignment conduction condition between the main test PAD and the auxiliary test PAD, according to the determined position relationship between the main test PAD and the main connection PAD, and the auxiliary test PAD and the auxiliary connection PAD, the alignment conduction condition of the main connection PAD and the auxiliary connection PAD can be determined, by detecting the resistance value between the main test PAD and the auxiliary test PAD and comparing with the known standard resistance value, the method has the advantages that the welding quality can be determined, so that the method has simple steps and convenient operation, plays a good role in safety isolation on circuits on the board, and ensures the connection of the main connection PAD and the auxiliary connection PAD and the safety of the circuits inside the main FPC and the auxiliary FPC.
Further, the number of the main test PADs and the number of the auxiliary test PADs are set to be four, the four main test PADs are respectively arranged in four mutually perpendicular directions of the main connection PADs, and the four auxiliary test PADs are arranged in four mutually perpendicular directions of the auxiliary connection PADs.
The above scheme is visible, through setting up four main test PADs and assisting the test PAD, and set up these four test PADs respectively on four mutually perpendicular's of corresponding connection PAD directions to guaranteed that the connection PAD is located the central point that is enclosed by four test PADs all the time and put, through the relation of switching on that detects the test PAD, can guarantee accurately that main connection PAD and assistance connect the relation of switching on between PAD, make the test result more accurate.
Still further, the resistance testing device is a customized high-precision resistance testing device or a high-precision multimeter.
The scheme can be seen, the customized high-precision resistance testing equipment or the high-precision multimeter and the like are adopted to detect the resistance value between the main testing PAD and the auxiliary testing PAD, and the detection precision is guaranteed.
Drawings
FIG. 1 is a schematic diagram of a PAD design of a conventional FPC of the prior art;
fig. 2 is a simplified structural diagram of a PAD on the main FPC;
FIG. 3 is a simplified schematic diagram of the alignment and matching of PADs of the main FPC and the auxiliary FPC;
fig. 4 is a simple connection diagram of the resistance testing device.
Detailed Description
As shown in fig. 2 to 4, the multi-layer interconnection FPC of the present invention includes a main FPC1 provided with main connection PADs and at least one auxiliary FPC2 provided with auxiliary connection PADs, and the main connection PADs and the auxiliary connection PADs are correspondingly fitted and attached. The testing procedure of the multilayer interconnected FPC is as follows.
a. And at least two main test PADs 3 and auxiliary test PADs 4 which are correspondingly superposed one by one at the positions of the main FPC1 and the auxiliary FPC2 after being jointed are respectively arranged at the peripheries of the main connection PAD and the auxiliary connection PAD.
b. The main test PAD3 with between the main PAD of connecting and the auxiliary test PAD4 with between the auxiliary PAD of connecting be isolated no electric connection setting, every the main test PAD3 is relative the main distance of connecting the PAD with every the auxiliary test PAD4 is relative the distance of setting of auxiliary connection PAD is fixed value.
c. A resistance test device 5 is switched in between the main test PAD3 and the auxiliary test PAD4, the resistance value between the main test PAD3 and the auxiliary test PAD4 being read by the resistance test device 5. Here, the resistance testing device 5 is a customized high-precision resistance testing apparatus or a high-precision multimeter. At present, customized resistance testing equipment is a conventional choice, and high-precision resistance testing equipment can be purchased and obtained from general resistance testing equipment manufacturers.
d. And c, comparing the resistance value measured by the resistance testing device 5 in the step c with the known resistance value under the normal welding condition, and when the resistance value measured by the resistance testing device 5 is larger than the known resistance value under the normal welding condition, judging that the PAD welding is abnormal, and if not, indicating that the welding is normal.
As shown in fig. 2, the number of the main test PAD3 and the auxiliary test PAD4 is set to four, four main test PADs 3 are respectively disposed in four mutually perpendicular directions of the main connection PADs, and four auxiliary test PADs 4 are disposed in four mutually perpendicular directions of the auxiliary connection PADs. Of course, in this embodiment, the number of the main test PADs 3 and the auxiliary test PADs 4 may also be set to other numbers, such as three, five, six, etc., depending on the specific PAD arrangement on the main FPC and the auxiliary FPC.
On the main FPC1, the main connection PAD includes an input main connection PAD6 and an output main connection PAD7, and the main test PAD3 is disposed at the periphery of both the input main connection PAD6 and the output main connection PAD 7. On assisting FPC2, the supplementary PAD of connecting includes that the output is assisted and is connected PAD8 and the PAD9 is assisted in the input, the PAD8 is assisted in the output with the periphery that the PAD9 was assisted in the input all is provided with assist test PAD4, input owner connect PAD6 with the output is assisted and is connected PAD8 looks adaptation laminating and this cooperation department main test PAD3 with assist test PAD4 one-to-one coincidence. The output main connection PAD7 is in fit with the input auxiliary connection PAD9, and the main test PAD3 and the auxiliary test PAD4 at the matched position are in one-to-one correspondence coincidence. The input main connection PAD6 and the output main connection PAD7 are respectively configured to be in matching connection with an input port and an output port of a circuit in the main FPC1, and the output auxiliary connection PAD8 and the input auxiliary connection PAD9 are respectively configured to be in matching connection with an output port and an input port of a circuit in the auxiliary FPC 2. The number of the input main connection PAD6, the output main connection PAD7, the output auxiliary connection PAD8 and the input auxiliary connection PAD9 is set to be identical.
According to the invention, the main test PAD and the auxiliary test PAD which are coincided one by one correspondingly are respectively arranged on the peripheries of the main connection PAD and the auxiliary connection PAD on the FPC, and the main test PAD and the main connection PAD and the auxiliary test PAD are arranged in an isolated manner, so that no electrical connection relation is generated between the main test PAD and the main connection PAD and between the auxiliary test PAD and the auxiliary connection PAD. And the setting distance of each main test PAD relative to the main connection PAD and the setting distance of each auxiliary test PAD relative to the auxiliary connection PAD are fixed values, so that the distance between the main test PAD and the main connection PAD and the distance between the auxiliary test PAD and the auxiliary connection PAD are fixed values of a standard, the alignment conduction condition of the main connection PAD and the auxiliary connection PAD can be determined by detecting the alignment conduction condition between the main test PAD and the auxiliary test PAD according to the determined position relation between the main test PAD and the main connection PAD and the determined position relation between the auxiliary test PAD and the auxiliary connection PAD, and the connection of the main connection PAD and the auxiliary connection PAD and the safety of the internal circuits of the main FPC and the auxiliary FPC are ensured.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those of ordinary skill in the art can readily practice the present invention as described herein; however, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention; meanwhile, any changes, modifications, and evolutions of the equivalent changes of the above embodiments according to the actual techniques of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010013513.1A CN111025130B (en) | 2020-01-07 | 2020-01-07 | A SMT detection method for multi-layer interconnected FPC |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010013513.1A CN111025130B (en) | 2020-01-07 | 2020-01-07 | A SMT detection method for multi-layer interconnected FPC |
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| CN111025130A true CN111025130A (en) | 2020-04-17 |
| CN111025130B CN111025130B (en) | 2021-07-16 |
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Address after: 611731, No. 2006, West Avenue, Chengdu hi tech Zone (West District, Sichuan) Patentee after: University of Electronic Science and Technology of China Patentee after: Zhuhai Zhongjing Yuansheng Electronic Technology Co., Ltd; Address before: 611731, No. 2006, West Avenue, Chengdu hi tech Zone (West District, Sichuan) Patentee before: University of Electronic Science and Technology of China Patentee before: Zhuhai Yuansheng Electronic Technology Co., Ltd; |