CN111017868B - Preparation method and application of array structure silicon-based lattice - Google Patents

Abstract

The invention discloses a preparation method and application of an array structure silicon-based lattice, wherein the preparation method comprises the following steps: spin coating photoresist on the surface of a silicon wafer; forming a sample application area with a specific size on the surface of the silicon wafer by adopting a photoetching method; self-assembling micro-nanospheres on the surface of the silicon wafer containing the sample application area by adopting a solution method; etching the silicon wafer deposited with the micro-nano spheres to form a micro-nano structure array in the sample application area; removing the photoresist on the surface of the silicon wafer; and removing the micro-nanospheres on the surface of the silicon wafer. The silicon-based lattice prepared by the preparation method of the array structure silicon-based lattice is applied to mass spectrum detection, raman detection, a biosensor or a photoelectric detector. The silicon-based dot matrix has potential application prospect in the fields of physics, chemistry, energy, catalysis, life science, information and the like.

Description

Preparation method and application of a silicon-based lattice with an array structure

technical field

The invention relates to a silicon-based lattice, in particular to an array silicon-based lattice with a micro-nano structure and a preparation method thereof.

Background technique

With the continuous development of micro-nano processing technology, the structures and devices used in microelectronics, information technology and life science are developing towards smaller scale, thinner and more precise, which plays an important role in microelectronic technology and biomedical microsystem . Micro-nano technology covers a wide range of more than 60 types, which can prepare various micro-nano structures and devices, mainly including planar technology, probe technology and model technology.

Planar technology is currently the most widely used micro-nano processing technology, including thin film deposition, patterning, doping and heat treatment. Planar micro-nano processing technology is mainly used in integrated circuit manufacturing, but in recent years it has also been applied Mechanical, microfluidic and micro-optical devices.

The probe process is developed based on traditional mechanical processing. Micro-nano probes include atomic force microscope probes, focused ion beams, laser beams, atomic beams, and spark discharge micro-probes. These probes can directly produce electron exposure or in The surface of the substrate forms a two-dimensional planar lattice, a pattern or a three-dimensional micro-nano structure.

The model process is to use the micro-nano-sized mold to replicate the corresponding micro-nano structure, including top-down processing technology and bottom-up technology. Top-down processing techniques include nanoimprinting, plastic molding, and die casting; bottom-up methods generally involve molecular self-assembly processes involving biochemical reactions. The structures and devices manufactured by micro-nano processing technology have broad application prospects in physics, chemistry, optoelectronic information, energy and life sciences due to their unique structure and special physical and chemical properties.

Invention content:

The main purpose of the present invention is to provide an arrayed silicon-based lattice with a three-dimensional micro-nano structure and a preparation method thereof, so that it has potential applications in physics, chemistry, photoelectric information, energy and life sciences.

The invention provides a method for preparing a silicon-based lattice with an array structure, the preparation method comprising: spin-coating a photoresist on the surface of a silicon wafer; forming a spotting area of a specific size on the surface of the silicon wafer by photolithography; Using a solution method to self-assemble micro-nanospheres on the surface of the silicon wafer containing the spotting area; etching the silicon wafer on which the micro-nanospheres are deposited, so that the spotting area forms a micro-nano structure array; removing the the photoresist on the surface of the silicon wafer; and removing the micro-nano balls on the surface of the silicon wafer.

In one embodiment, after forming a spotting area of a specific size on the surface of the silicon wafer by photolithography, the method further includes: etching the surface of the silicon wafer in the spotting area to form a groove.

In one embodiment, the step of adopting a solution method to self-assemble micro-nanospheres on the surface of the silicon wafer includes a pulling method and a LB (Langmuir-Blodgett) membrane method.

In one embodiment, the step of etching the silicon wafer deposited with micro-nanospheres adopts an inductively coupled plasma (ICP) system, wherein the etching gas is SF ₆ or O ₂ , and the etching gas The flow rate is 5-40sccm (Standard Cubic Centimeter per Minute), the etching time is 5-3000s, the ICP power is 200-300W, and the radio frequency (RF) power is 10-30W.

In one embodiment, the shape of the spotting area is a concave or convex circle or a regular polygon, wherein the regular polygon includes a square, a regular triangle or a regular hexagon; the side length of the regular polygon spotting area is 10 μm-5mm , the diameter of the circular spotting area is 10 μm-5 mm; the depth of the depression or the height of the protrusion is 10 nm-100 μm; the distance between the adjacent spotting areas is 10 μm-10 mm.

In one embodiment, the step of removing the photoresist on the surface of the silicon wafer is to place the silicon wafer in an acetone solution and vibrate for 10 minutes; remove the micro-nanospheres on the surface of the silicon wafer The step is to place the silicon chip in tetrahydrofuran solution or strong alkali solution or anneal at high temperature to remove the micro-nano balls.

In one embodiment, after removing the micro-nanospheres on the surface of the silicon wafer, it further includes: depositing a material layer on the surface of the silicon wafer, the material can be a single layer or multiple layers, and the material layer The thickness is 5nm-1μm; and the silicon wafer is scribed.

In an embodiment, the material of the material layer may be metal, metal oxide, metal nitride, or high molecular polymer, or a combination of the above materials.

In one embodiment, the metal includes but not limited to at least one of Au, Ag, Cu, Al, Ti, Rh, Ni, Pt or a combination thereof; the metal oxide includes but not limited to Al ₂ O ₃ , at least one of ZnO, TiO ₂ , ZrO ₂ or a combination thereof; the metal nitride includes but not limited to at least one of TiN, GaN, AlN or a combination thereof; the polymer includes but not limited to At least one of polyethylene, polyvinyl chloride, phenolic resin or a combination thereof.

In one embodiment, the micro-nano spheres include polystyrene spheres or silica spheres.

The present invention also provides a silicon-based lattice with an array structure, which is made by the aforementioned preparation method. The silicon-based lattice includes the spotting area and the peripheral area, wherein the spotting area includes the micro-nano structure array and is wrapped in The material layer on the surface of the micro-nano structure; the micro-nano structure array includes several micro-nano structures; the height of the micro-nano structure is 10nm-100μm, and its equivalent diameter or equivalent side length is 10nm-100μm, so The distance between adjacent micro-nano structures, that is, the pitch of the array structure, is 10 nm-10 μm; the thickness of the material layer is 5 nm-1 μm.

In one embodiment, the shape of the spotting area is a concave or convex circle or a regular polygon, wherein the regular polygon includes a square, a regular triangle or a regular hexagon; the side length of the spotting area of the regular polygon is 10 μm -5 mm, the diameter of the circular spotting area is 10 μm-5 mm; the depth of the depression or the height of the protrusion is 10 nm-100 μm, and the distance between the adjacent spotting areas is 10 μm-10 mm.

In one embodiment, the sum of the height of the micro-nano structure and the depth of the groove in the spotting area is the depression depth of the spotting area.

In one embodiment, the shape of the micro/nano structure includes one of cone, column, barrel, bottle, bowl, spherical, and hemispherical.

In another embodiment, the present invention provides a method for fabricating an array silicon-based lattice having a three-dimensional micro-nano structure, comprising the steps of:

S1. Provide single-sided or double-sided polished silicon wafers;

S2. Using RCA (Radio Corporation of America) standard to clean the silicon wafer;

S3. Spin-coat photoresist on the surface, and then use photolithography to form a spot area of a specific size on the surface of the silicon wafer;

S4. Using a solution method to self-assemble micro-nanospheres on the surface of the silicon wafer containing the spotting area;

S5. Using self-assembled micro-nanospheres as a mask, the silicon wafer is etched by an inductively coupled plasma (ICP) system, thereby forming an array of micro-nano structures in the spotting area;

S6. placing the silicon wafer in an acetone solution and shaking for 10 minutes to remove the photoresist on the surface of the silicon wafer;

S7. placing the silicon wafer in a tetrahydrofuran solution or a strong alkali solution or annealing at a high temperature to remove the micro-nanosphere mask on the surface of the silicon wafer;

S8. forming other material layers on the surface of the silicon wafer;

S9. Scribing the silicon wafer.

In one embodiment, after forming a spotting area of a specific size on the surface of the silicon wafer by photolithography, the method further includes: etching the surface of the silicon wafer in the spotting area to form a groove.

In one embodiment, the resistivity of the single crystal silicon wafer is 0.001-0.1Ω·cm.

In one embodiment, the micro/nano mask adopts 100-1000 nm polystyrene balls.

In one embodiment, the plasma etching method may use ICP etching or deep silicon etching.

In one embodiment, the micro-nano mask is removed by annealing.

In one embodiment, the material layer formed on the surface of the silicon wafer may be one or a combination of Au, Ag, Al, TiO ₂ , Al ₂ O ₃ .

In one embodiment, the method for forming the material layer may be thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), magnetron sputtering, atomic layer deposition (ALD) deposition any of the methods.

In one embodiment, the thickness of the material layer may be 5 nm-1 μm, preferably the thickness of the material layer is 5-200 nm.

In one embodiment, the scribing method is grinding wheel scribing or laser scribing.

In one embodiment, an ICP etching system or a deep silicon etching system is used, and the etching gas is SF ₆ or O ₂ ; the flow rate of the etching gas SF ₆ is 10-20 sccm, and the flow rate of O ₂ is 20-40 sccm. The time is 5-3000s, the ICP power is 200-250W, and the RF power is 10-20W.

The third aspect of the present invention provides an application of a silicon-based lattice with an array structure in mass spectrometry detection. The silicon-based lattice with an array structure is made by the method for preparing a silicon-based lattice with an array structure according to the present invention.

In the embodiment of the present invention, the mass spectrometry is electron bombardment mass spectrometry (EI-MS), field desorption mass spectrometry (FD-MS), fast atom bombardment mass spectrometry (FAB-MS), matrix-assisted laser desorption ionization time-of-flight mass spectrometry ( MALDI-TOF MS) or electron spray mass spectrometry (ESI-MS).

After the array structure silicon-based lattice is prepared according to the method of the present invention, the matrix and the detection sample can be added dropwise to the spotting area, and then placed in a mass spectrometer, such as MALDI-TOF MS, for detection.

Preferably, the matrix includes, but is not limited to, commonly used matrices for MALDI-TOF MS, for example, 3-hydroxypicolinic acid, α-cyano-4-hydroxycinnamic acid, 2,5-dihydroxybenzoic acid, picolinic acid, 3-amino Picolinic acid, 3-picolinic acid, anthranilic acid, nicotinic acid, etc.

The detection samples applicable to the mass spectrometry detection of the present invention include but are not limited to various organic and inorganic small molecules, polymer compounds, viruses, microorganisms, nucleotides, nucleosides, oligonucleotides, nucleic acids, amino acids, peptides, proteins, lipids, At least one of sugars, carbohydrates, antigens, antibodies, cells and cell metabolites, but not limited thereto.

The silicon-based lattice with an array structure of the present invention can also be used in Raman spectrum detection.

The silicon-based lattice with the array structure of the present invention can also be used in photodetectors.

The array structure silicon-based lattice of the present invention can also be used in biosensors.

The silicon-based lattice with an array structure of the present invention can also be used in catalytic performance characterization instruments.

Beneficial effect

Compared with the self-assembled micro-nanosphere mask by the spin coating method, the self-assembled micro-nano mask method adopted in the present invention has simple process and less consumables, and it can only have a three-dimensional micro-nano structure array in a specific spot area, resulting in The properties of the spotting area and the non-spotting area are different, and due to the difference in the reflection of light between the spotting area and the non-spotting area of the silicon-based lattice, it can be directly distinguished by the naked eye without adding other marking substances to the spotting area. This makes it easier to sample.

The preparation method of the present invention can form circular, square or regular triangular sampling area holes and outer areas of the titration samples on the surface of the silicon-based dot matrix of the array structure. Among them, the spotting area is prepared with special three-dimensional micro-nano structure arrays of different sizes such as cones, columns, barrels or hemispheres according to needs. A series of three-dimensional micro-nano structure arrays can be prepared in the silicon-based lattice spot area through plasma etching, photolithography, chemical vapor deposition, magnetron sputtering and other semiconductor micro-nano processing techniques. On the one hand, the regular three-dimensional structure array , which can make the analyte distribution in the sample area more uniform; on the other hand, the silicon-based three-dimensional structure array is conducive to the formation of a coupled electric field and promote the ionization of molecules. In addition, metal nanoparticles such as Au and Ag can be sputtered on the surface of the structure array, and the local surface plasmon resonance characteristics of the metal nanostructure can be used to promote the desorption ionization of the analyzed sample, so that it can be used in biochemical sample analysis, photoelectric information, etc. The field has potential application prospects.

The present invention prepares a silicon-based lattice with a three-dimensional micro-nano structure array by adopting a micro-nano processing technology, and then utilizes the advantages of the micro-nano structure array and its unique photoelectric properties, so as to be applied to biochemical analysis and detection, such as mass spectrometry detection applications and Raman detection It can be used in biosensors or photodetectors to improve the detection effect of samples.

Description of drawings

The provided drawings can further understand the present invention, and constitute a part of the description, and are used to explain the present invention together with the embodiments of the present invention, and do not constitute a limitation to the present invention. In addition, the drawing data are descriptive summaries and are not drawn to scale.

Figure 1: A schematic top view of a silicon-based lattice provided in the present invention.

Figure 2: Schematic diagram of the structure of the spotting area in Figure 1.

Fig. 3: a flow chart of the preparation process provided by the present invention.

Figure 4: A diagram of the device for forming a self-assembled nanosphere mask in the present invention.

FIG. 5 : Schematic diagram of a mask plate for photolithography in Step S1 of Embodiment 1 of the present invention.

FIG. 6 : Microscopic plane scanning electron microscope (SEM) photo of the spotting area after step S4 of Example 1 of the present invention.

Fig. 7: SEM photograph of the microscopic section of the spotting area after step S4 of Example 1 of the present invention.

Fig. 8: SEM photograph of the microscopic plane of the spotting area after step S5 of Example 1 of the present invention.

Fig. 9: SEM photograph of the microscopic section of the spotting area after step S5 of Example 1 of the present invention.

FIG. 10 : SEM photograph of the microscopic plane of the spotting area after step S5 of Example 3 of the present invention.

FIG. 11 : SEM photo of the microscopic section of the spotting area after step S5 of Example 3 of the present invention.

Fig. 12: Schematic cross-sectional view of the spotting area after step S2 in Example 4 of the present invention.

Fig. 13: Schematic cross-sectional view of the spotting area after step S4 in Example 4 of the present invention.

Figure 14: Schematic cross-sectional view of the spotting area after step S3 in Example 5 of the present invention.

Detailed ways

The following will describe the technical solutions of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The invention proposes a silicon-based lattice with a micro-nano structure array and its preparation method. The invention utilizes semiconductor processing technologies such as plasma etching, magnetron sputtering and photolithography to prepare silicon with a regular micro-nano structure array. Based on the array structure, the sample can be uniformly dispersed by using the array structure, and the surface plasmon resonance effect of the metal nanostructure can be used to promote the desorption and ionization of the analyte sample.

The invention provides a method for preparing a silicon-based lattice with an array structure. Please refer to Figure 1, Figure 2 and Figure 3, Figure 1 is a schematic top view of a silicon wafer, in which the shaded part is the spotting area, Figure 2 is a structural schematic diagram of the spotting area in Figure 1, showing the silicon wafer made on the upper surface A plurality of spotting areas, wherein the multiple spotting areas are distributed in an array on the silicon wafer; Figure 3 shows the relevant process flow of the preparation method. The steps of the preparation method include:

(a) Spin-coat photoresist 1 on the surface of a silicon wafer 2;

(b) using photolithography to form a spot area of a specific size on the surface of the silicon wafer;

(c) using a solution method to self-assemble micro-nanospheres 3 on the surface of the silicon wafer containing the spotting area;

(d) Etching the silicon wafer on which the micro-nano balls 3 are deposited, forming an array of micro-nano structures in the spotting area;

(e) removing the photoresist 1 on the surface of the silicon wafer;

(f) removing the micro-nano balls 3 on the surface of the silicon wafer.

In one embodiment, after removing the micro-nanospheres 3 on the surface of the silicon wafer, the following steps are also included:

(g) Deposit a material layer 4 on the surface of the silicon wafer, the material layer 4 can be a single layer or multiple layers, and the thickness of the material layer 4 is a material layer of 5nm-1μm; then, the silicon wafer can be diced according to commercial needs .

In one embodiment, after forming a spotting area of a specific size on the surface of the silicon wafer by photolithography, the following step is further included: forming grooves by etching on the surface of the silicon wafer in the spotting area.

In one embodiment, the micro-nano spheres include polystyrene spheres or silica spheres.

In one embodiment, the step of self-assembling the micro-nanospheres 3 on the surface of the silicon wafer by the solution method includes the pulling method and the LB (Langmuir-Blodgett) membrane method.

In one embodiment, the step of etching the silicon wafer on which the micro-nanospheres 3 are deposited is etched using an inductively coupled plasma (ICP) system, wherein the etching gas is SF ₆ or O ₂ , and the etching gas The flow rate is 5-40sccm (Standard Cubic Centimeter per Minute), the etching time is 5-3000s, the ICP power is 200-300W, and the RF power is 10-30W.

In one embodiment, the step of removing the photoresist 1 on the surface of the silicon wafer is to place the silicon wafer in an acetone solution and shake it for 10 minutes; the step of removing the micro-nanospheres 3 on the surface of the silicon wafer is to place the silicon wafer in tetrahydrofuran solution or strong alkali solution or annealing at high temperature to remove micro-nanospheres 3 .

In an embodiment, the material of the material layer 4 may be metal, metal oxide, metal nitride or polymer, or any combination of the above materials. In one embodiment, the metal includes but not limited to at least one of Au, Ag, Cu, Al, Ti, Rh, Ni, Pt or a combination thereof; the metal oxide includes but not limited to Al ₂ O ₃ , at least one of ZnO, TiO ₂ , ZrO ₂ or a combination thereof; the metal nitride includes but not limited to at least one of TiN, GaN, AlN or a combination thereof; the polymer includes but not limited to At least one of polyethylene, polyvinyl chloride, phenolic resin or a combination thereof.

Please refer to Fig. 4, Fig. 4 shows the related device of self-assembling micro-nanospheres by the solution method in the present invention, wherein, the solution containing micro-nanospheres is slowly injected into the aqueous solution with a silicon substrate 6 using a micro-injector 8 to make the micro-nanospheres The nanospheres cover the water surface; then after opening the small hole 9 at the bottom of the water container 5, the water will flow slowly so that the micronanospheres are successfully covered on the surface of the silicon substrate 6, wherein the silicon substrate 6 is placed on the supporting cylinder platform 7; Finally, place it in a fume hood to allow it to air-dry naturally, and obtain the result shown in (c) in Fig. 3 .

The invention also provides a silicon-based lattice with an array structure, which is made by the aforementioned preparation method. The array of silicon-based lattices includes a spotting area and a peripheral area, wherein the spotting area includes a micro-nanostructure array and a material layer wrapped on the surface of the micro-nanostructure, and the micro-nanostructure array includes several micro-nanostructures, as shown in Figure 3 As shown in middle (f); wherein, the height of the micro-nanostructure is 10nm-100μm, its equivalent diameter or equivalent side length is 10nm-100μm, and the distance between adjacent micro-nanostructures, that is, the micro-nanostructure array spacing is 10nm -10 μm; the thickness of the material layer is 5 nm-1 μm.

In one embodiment, the shape of the spotting area is a concave or convex circle or a regular polygon, wherein the regular polygon can be a square, a regular triangle or a regular hexagon; the side length of the polygonal spotting area is 10 μm -5 mm, the diameter of the circular spotting area is 10 μm-5 mm; the depth of the depression or the height of the protrusion is 10 nm-100 μm, and the distance between the adjacent spotting areas is 10 μm-10 mm.

In one embodiment, the sum of the height of the micro-nano structure and the depth of the groove in the spotting area is the depression depth of the spotting area.

In one embodiment, the shape of the micro-nano structure includes one of cone, column, barrel, bottle, bowl, spherical and hemispherical.

In another embodiment, the method for fabricating an array structure silicon-based lattice provided by the present invention includes the steps of:

S1. Provide single-sided or double-sided polished silicon wafers;

S2. RCA standard cleaning is used to clean the silicon wafer;

S3. Spin-coat photoresist on the surface, and then use photolithography to form a spot area of a specific size on the surface of the silicon wafer;

S4. Using a solution method to self-assemble micro-nanospheres on the surface of the silicon wafer containing the spotting area;

S5. Using the self-assembled micro-nano spheres as a mask, an inductively coupled plasma (ICP) system is used to etch the silicon wafer on which the micro-nano spheres are deposited, so that the spotting area has a three-dimensional micro-nano structure array;

S6. the silicon wafer is placed in an acetone solution and shaken for 10 minutes to remove the surface photoresist;

S7. placing the silicon wafer in a tetrahydrofuran solution or a strong alkali solution or annealing at a high temperature to remove the micro-nanosphere mask on the surface of the silicon wafer;

S8. forming other material layers on the surface of the silicon wafer;

S9. The silicon wafer is diced.

Preferably, after photolithography, the surface of the silicon wafer forming the spotting area of a specific size is etched to form grooves.

Preferably, the silicon wafer has a thickness of 100 μm-2 mm, can be N-type doped or P-type doped, and has a resistivity of 0.001˜10 Ω·cm.

Preferably, the micro-nano spheres include polystyrene spheres or silica spheres; the size thereof is 100 nm-10 μm.

Preferably, the micro/nano spheres include polystyrene spheres or silica spheres, and the mass fraction of the micro/nano sphere dispersion solution is 2%-40%.

Preferably, the low speed of the spin coater is 300-500rpm (revolutions per minute), and the time is 1-10s; the high speed is 2000-3000rpm, and the time is 30-60s.

Preferably, an ICP plasma etching system or a deep silicon etching system is used, and the etching gas is SF ₆ , O ₂ .

Preferably, the flow rate of ICP etching gas SF ₆ is 10-20 sccm, the flow rate of O ₂ is 20-40 sccm, the etching time is 5-3000s, the ICP power is 200-250W, and the RF power is 10-20W.

Preferably, the micro-nano structure formed by etching includes a cylindrical shape, a conical shape or a truncated cone shape.

Preferably, the spotting area formed by photolithography is a regular polygon and a circle, and the regular polygon includes a square, a regular triangle or a regular hexagon, wherein the side length of the regular polygon ranges from 10 μm to 5 mm, and the diameter of the circle is 10 μm to 5 mm.

Preferably, the method of removing the micro-nanosphere mask includes annealing at 450-500° C. for 20-30 minutes, or soaking in tetrahydrofuran solution for 24 hours.

Preferably, metal Au, Ag, Al, Rh, Ni, Pt or any combination or metal nitrides such as TiN or metal oxides such as TiO ₂ , Al ₂ O ₃ etc. are sputtered on the surface of the silicon wafer after photolithography.

Preferably, the thickness of the sputtered material layer is 5 nm-1 μm.

The detailed production process and conditions of the preparation method provided by the present invention are illustrated below through five examples.

Example 1:

S1. Wafer preparation:

Select a double-sided polished silicon wafer, and perform RCA standard cleaning on the silicon wafer to remove various impurities and pollutants on the surface.

S2. Preparation of silicon-based lattice dot-like area with array structure

Use template photolithography to prepare dot-matrix sample areas. First, spin-coat positive photoresist on the surface of the cleaned silicon wafer. The parameters of the spin-coating machine are 2500 rpm and 30 seconds, and then heat it at 96 ° C. Bake the glue on the board for 4 minutes. (The cross-section is shown in (a) schematic diagram in Figure 3)

Place the silicon wafer coated with photoresist in a photolithography machine for photolithography. The photolithography mask used is a 5-inch cadmium plate. The schematic diagram of the mask is shown in Figure 5. The light-transmitting part is a square pattern with a side length of 2mm. , the distance between adjacent patterns is 2mm, and the exposure time is 12 seconds. Immediately after the exposure, it is placed in the developing solution and developed for 120 seconds to remove the photoresist in the exposed area, and then rinsed with deionized water for one minute and then blown dry with nitrogen gas , to obtain a square spotting area, and the distance between adjacent spotting areas is 2mm. (The cross-section is shown in the schematic diagram of (b) in Figure 3)

S3. Preparation of micro-nano structure array in the array structure silicon-based lattice spot area

Monolayer polystyrene (PS) micro-nanospheres were self-assembled on the surface of silicon wafer after photolithography by solution method. The specific steps are as follows: first prepare the PS micronanosphere dispersion, mix the suspension of 530nm PS micronanospheres with a mass fraction of 5% and n-butanol at a volume ratio of 1:1 to obtain a dispersion of 530nm PS micronanospheres Then as shown in Figure 4, adopt the microinjector to slowly inject the PS micronanosphere dispersion liquid of 40 μ L 530nm into the aqueous solution that is placed on the silicon chip to make the PS micronanosphere cover the water surface (the water submerges the silicon chip, the microinjector and the horizontal surface The included angle is 30-45 degrees, the needle tip of the syringe just touches the aqueous solution), then open the small hole at the bottom of the alumina crucible, let the water flow slowly, so that the PS micro-nano balls are successfully covered on the surface of the silicon wafer, and finally placed in the fume hood for use It was air-dried naturally, and the result shown in (c) in Fig. 3 was obtained.

The silicon wafer coated with PS micro-nanospheres on the surface is placed in an inductively coupled plasma etching system for etching. The etching time is 100 seconds and the etching depth is 600nm. The results are shown in Figure 3(d).

S4. Removing the photoresist and micro-nano balls on the surface of the array structure silicon-based lattice

Place the etched silicon wafer in an acetone solution and shake it for 10 minutes to remove the surface photoresist and PS micro-nanospheres on the surface of the photoresist, then rinse it with deionized water for 5 minutes, and dry it with nitrogen. The cross-section is shown in the figure 3(e).

Then place the silicon wafer in a muffle furnace for annealing to remove the PS micro-nanospheres in the spotting area of the silicon wafer. The annealing temperature is 500°C and the time is 30 minutes. At this time, the cross-sectional schematic diagram of the silicon wafer is shown in Fig. The surface microstructure of the lattice spot area is shown in Figure 6 and Figure 7. The micro-nanostructure of the silicon-based lattice spot area is columnar, with an average diameter of 400-500nm and a height of 550-600nm. The distance is 60-260nm.

S5. Depositing a metal layer on the surface of the array structure silicon-based lattice

The metal layer was deposited on the annealed silicon wafer using a magnetron sputtering coating system, the sputtering power was 200W, and the deposition thickness was 20nm. The microstructure of the sample area is shown in Figure 8 and Figure 9, where the Au layer can also be Ag, Cu, Al, Ti, Ni, Pt. The uniform micro-nano structure array is conducive to the uniform dispersion of surface samples. After depositing nanoparticles such as Au and Ag on the surface, a localized surface plasmon resonance effect is generated under light irradiation, and the plasmonic elements induce charge separation to make the metal surface Accumulate a large number of positive charges, increase the charge density and thus increase the electric field strength. The silicon-based lattice with an array structure prepared by the invention has potential applications in the fields of sample analysis and detection, photoelectric detection and the like.

Example 2:

According to the array structure silicon-based lattice that S1, S2, S3, S4 steps make among the embodiment 1, after S4, adopt magnetron sputtering coating system deposition material layer with the silicon slice of annealing, material layer is multi-layer structure, preferably is Double-layer structure, the first layer can be a metal layer, metal oxide layer or metal nitride layer, and the second layer can also be a metal layer, metal oxide layer or metal nitride layer, where the metal layer can also be Au, Ag, At least one of Cu, Al, Ni, Pt or a combination thereof, the metal oxide layer can be at least one of Al ₂ O ₃ , ZnO, TiO ₂ , ZrO ₂ or a combination thereof, and the metal nitride layer can be TiN , at least one of GaN, AlN or a combination thereof.

Example 3:

S1. Wafer preparation

Select a double-sided polished silicon wafer, and perform RCA standard cleaning on the silicon wafer to remove various impurities and pollutants on the surface.

S2. Preparation of silicon-based lattice dot-like area with array structure

Use template photolithography to prepare dot-matrix sample areas. First, spin-coat positive photoresist on the cleaned silicon wafer. The parameters of the spin-coating machine are 2500 rpm and 30 seconds, and then heat it at 96 ° C. Bake the glue on the board for 4 minutes. (The cross-section is shown in (a) schematic diagram in Figure 3)

Place the silicon wafer coated with photoresist in a photolithography machine for photolithography. The photolithography mask used is a 5-inch cadmium plate. The light-transmitting part of the mask is a circular pattern with a diameter of 10 μm, and the distance between adjacent patterns is 10 μm, the exposure time is 12 seconds, placed in the developer solution for 120 seconds to shake and develop for 120 seconds to remove the photoresist in the exposed area, and then rinsed with deionized water for one minute and then dried with nitrogen to obtain a circular spot area, and the distance between adjacent spotting areas is 10 μm, the cross-section is shown in the schematic diagram of (b) in Figure 3.

S3. Preparation of micro-nano structure array in the array structure silicon-based lattice spot area

Monolayer polystyrene (PS) micro-nanospheres were self-assembled on the surface of silicon wafer after photolithography by solution method. The specific steps are as follows: first prepare the PS micronanosphere dispersion, mix the PS micronanosphere suspension with a mass fraction of 5% and a diameter of 360nm with n-butanol at a volume ratio of 1:1 to obtain a 360nm PS micronanosphere dispersion Then as shown in Figure 4, the PS micro-nanosphere dispersion of 40 μ L of 360nm is slowly injected into the aqueous solution with silicon wafers using a micro-injector to make the PS micro-nano-spheres cover the water surface (water submerges the silicon wafer, and the micro-injector and the horizontal surface The included angle is 30-45 degrees, the needle tip of the syringe just touches the aqueous solution), then open the small hole at the bottom of the alumina crucible, let the water flow slowly, so that the PS micro-nano balls are successfully covered on the surface of the silicon wafer, and finally placed in the fume hood for use It was air-dried naturally, and the result shown in (c) in Fig. 3 was obtained.

Place the silicon wafer coated with PS micro-nanospheres on the surface in an inductively coupled plasma etching system for etching, the etching time is 60s, and the etching depth is 400nm. The results are shown in Figure 3(d).

S4. Removing the photoresist and micro-nano balls on the surface of the array structure silicon-based lattice

Place the etched silicon wafer in an acetone solution and shake it for 10 minutes to remove the surface photoresist and PS micro-nanospheres on the surface of the photoresist, then rinse it with deionized water for 5 minutes, and dry it with nitrogen. The cross-section is shown in the figure 3(e).

Then place the silicon wafer in tetrahydrofuran solution and soak for 24 hours to remove the PS micro-nanospheres in the spotting area of the silicon wafer. At this time, the cross-sectional schematic diagram of the silicon wafer is shown in Figure 3(f). , the average diameter is 300-350nm, the height is 350-400nm, and the distance between adjacent micro-nano structures is 10-120nm.

S5. Depositing a metal oxide layer on the surface of the array structure silicon-based lattice

Deposit the metal oxide layer on the silicon wafer after removing micro-nano balls by magnetron sputtering coating system, the deposition thickness is 50nm. At this time, the cross-sectional schematic diagram of the silicon wafer is shown in Figure ₃ (g). The microstructure of the spotting area is shown in Figure 10 and Figure 11, where the metal oxide layer can also be Al ₂ O ₃ , ZnO, TiO ₂ , ZrO ₂ .

Example 4:

S1. Wafer preparation

Select a double-sided polished silicon wafer, and perform RCA standard cleaning on the silicon wafer to remove various impurities and pollutants on the surface.

S2. Preparation of silicon-based lattice dot-like area with array structure

Use template photolithography to prepare dot-matrix sample areas. First, spin-coat positive photoresist on the cleaned silicon wafer. The parameters of the spin-coating machine are 2500 rpm and 30 seconds, and then heat it at 96 ° C. Bake the glue on the board for 4 minutes. (The cross-section is shown in (a) schematic diagram in Figure 3)

Place the silicon wafer coated with photoresist in a maskless laser direct writing lithography system for photolithography. The exposure pattern is an equilateral triangle pattern with a side length of 5mm, and the distance between adjacent patterns is 10mm. Place it in the developer solution immediately after exposure Shake and develop for 60 seconds to remove the photoresist in the exposed area, then rinse with deionized water for one minute and blow dry with nitrogen to obtain a regular triangle spotting area, the distance between adjacent spotting areas is 10mm, the cross section is shown in Figure 3 In (b) schematic diagram.

Then place the photoetched silicon wafer in an inductively coupled plasma etching system for etching. The etching time is 1000s and the etching depth is 10μm. The result shown in Figure 12 is obtained. At this time, the silicon-based lattice pattern area forms groove , the groove depth is 10 μm.

S3. Preparation of micro-nano structure array in the array structure silicon-based lattice spot area

Monolayer polystyrene (PS) micro-nanospheres were self-assembled on the surface of silicon wafer after photolithography by solution method. The specific steps are as follows: first prepare the PS micronanosphere dispersion, mix the PS micronanosphere suspension with a mass fraction of 5% and a diameter of 360nm with n-butanol at a volume ratio of 1:1 to obtain a 360nm PS micronanosphere dispersion Then as shown in Figure 4, the PS micro-nanosphere dispersion of 40 μ L of 360nm is slowly injected into the aqueous solution with silicon wafers using a micro-injector to make the PS micro-nano-spheres cover the water surface (water submerges the silicon wafer, and the micro-injector and the horizontal surface The included angle is 30-45 degrees, the needle tip of the syringe just touches the aqueous solution), then open the small hole at the bottom of the alumina crucible, let the water flow slowly, so that the PS micro-nano balls are successfully covered on the surface of the silicon wafer, and finally placed in the fume hood for use It is air dried naturally.

Place the silicon wafer coated with PS micro-nano spheres on the surface of the inductively coupled plasma etching system for etching, the etching time is 60s, and the etching depth is 400nm. The depression depth of the region is the sum of the height of the micro-nano structure and the depth of the groove.

S4. Removing the photoresist and micro-nano balls on the surface of the array structure silicon-based lattice

The etched silicon wafer was placed in an acetone solution and shaken for 10 minutes to remove the surface photoresist and PS micro-nanospheres on the surface of the photoresist, then rinsed with deionized water for 5 minutes, and dried with nitrogen.

Then place the silicon wafer in tetrahydrofuran solution and soak for 24 hours to remove the PS micro-nanospheres in the spotting area of the silicon wafer. The distance between them is 10-120 nm. At this time, the cross-sectional schematic diagram of the silicon wafer is shown in FIG. 13 .

S5. Depositing a metal nitride layer on the surface of the array structure silicon-based lattice

The silicon wafer after removing the micro-nano balls is deposited with a magnetron sputtering coating system with a thickness of 100nm to deposit a metal nitride layer, wherein the metal nitride layer can also be AlN or GaN.

Example 5:

S1. Wafer preparation:

Select a double-sided polished silicon wafer, and perform RCA standard cleaning on the silicon wafer to remove various impurities and pollutants on the surface.

S2. Preparation of silicon-based lattice dot-like area with array structure

Use template photolithography to prepare dot-matrix sample areas. First, spin-coat positive photoresist on the surface of the cleaned silicon wafer. The parameters of the spin-coating machine are 2500 rpm and 30 seconds, and then heat it at 96 ° C. Bake the glue on the board for 4 minutes. (The cross-section is shown in (a) schematic diagram in Figure 3)

Place the silicon wafer coated with photoresist in a photolithography machine for photolithography. The photolithography mask used is a 5-inch cadmium plate, and the light-transmitting part is a circular pattern with a diameter of 5 mm. The distance between adjacent patterns is 5 mm. The time is 12 seconds. Immediately after the exposure, it is placed in the developer solution and developed for 120 seconds to remove the photoresist in the exposed area. Then it is rinsed with deionized water for one minute and then dried with nitrogen to obtain a circular spotting area. The distance between the spotting areas is 5 mm, and the cross-section is shown in (b) schematic diagram in Figure 3.

S3. Preparation of micro-nano structure array in the array structure silicon-based lattice spot area

A solution method is used to self-assemble a single layer of silicon dioxide micro-nanospheres on the surface of a silicon wafer after photolithography. The specific steps are as follows: first prepare the silica micro-nanosphere dispersion, mix the silica micro-nanosphere suspension with a mass fraction of 10% and a diameter of 2 μm with n-butanol at a volume ratio of 1:1 to obtain a 2 μm silica Silicon micro-nanosphere dispersion; then as shown in Figure 4, the 2 μm silicon dioxide micro-nanosphere dispersion of 40 μ L is slowly injected into the aqueous solution with silicon wafers using a micro-injector to make the silicon dioxide micro-nanospheres cover the water surface ( The silicon wafer is submerged in water, the angle between the micro-injector and the horizontal plane is 30-45 degrees, and the needle tip of the syringe just touches the aqueous solution), and then the small hole at the bottom of the alumina crucible is opened to allow the water to flow slowly, so that the silica micro-nano balls are successfully covered On the surface of the silicon wafer, it is finally placed in a fume hood to let it dry naturally, and the result shown in (c) in Figure 3 is obtained.

The silicon wafer coated with silicon dioxide micro-nanospheres was placed in an inductively coupled plasma etching system for etching. The etching time was 400 seconds, and the etching depth was 2 μm. At this time, the depression depth of the silicon-based lattice spot area was 2 μm.

S4. Removing the photoresist and micro-nano balls on the surface of the array structure silicon-based lattice

First place the silicon wafer in a sodium hydroxide solution with a concentration of 1mol/L and shake it for 15 minutes to remove the silicon dioxide micro-nano balls on the surface. shape and size.

The etched silicon wafer was placed in an acetone solution and shaken for 10 minutes to remove the surface photoresist, then rinsed with deionized water for 5 minutes, and blown dry with nitrogen.

At this time, the micro-nanostructures in the silicon-based lattice spot area are cone-shaped, the diameter of the bottom circle is 2.0-2.1 μm, the height is 2 μm, and the distance between adjacent micro-nanostructures is 8-10 μm. The results shown in Figure 14 are obtained.

S5. Depositing a metal layer on the surface of the array structure silicon-based lattice

The silicon wafer from which the silica nanospheres have been removed is deposited by a magnetron sputtering coating system with a thickness of 20nm Au, where the Au layer can also be Ag, Cu, Al, Ti, Ni, Pt.

Compared with the self-assembled micro-nanosphere mask by the spin coating method, the self-assembled micro-nano mask method adopted in the present invention has simple process and less consumables, and it can only have a three-dimensional micro-nano structure array in a specific spot area, resulting in The properties of the spotting area and the non-spotting area are different, and due to the difference in the reflection of light in the array structure silicon-based lattice spotting area and the non-spotting area, it can be directly distinguished by naked eyes without adding other marking substances to the spotting area. This makes it easier to sample.

The preparation method of the present invention can form round, square or triangular spotting area holes and outer areas of the titration samples on the surface of the silicon-based dot matrix of the array structure. Among them, the spotting area is prepared with special three-dimensional micro-nano structures of different sizes such as cones, columns, barrels or hemispheres according to needs. A series of three-dimensional micro-nano structure arrays can be prepared in the silicon-based lattice spot area through plasma etching, photolithography, chemical vapor deposition, magnetron sputtering and other semiconductor micro-nano processing techniques. On the one hand, the regular three-dimensional structure array , which can make the analyte distribution in the sample area more uniform; on the other hand, the silicon-based three-dimensional structure array is conducive to the formation of a coupled electric field and promote the ionization of molecules. In addition, Au, Ag, Cu, Al, Ti, Ni, Pt and other metal nanoparticles can be sputtered on the surface of the structure array, and the local surface plasmon resonance characteristics of the metal nanostructure can be used to promote the desorption ionization of the analyzed sample. Therefore, it has potential application prospects in the fields of biochemical sample analysis and photoelectric information.

The present invention prepares a silicon-based lattice with an array structure of a three-dimensional micro-nano structure array by adopting a micro-nano processing technology, and further exerts the advantages of the micro-nano structure array and its unique photoelectric properties, so as to be applied to biochemical analysis and detection and improve the sample detection effect.

The present invention provides an application of a silicon-based lattice with an array structure in mass spectrometry detection. The silicon-based lattice with an array structure is made by the method in the embodiment of the present invention. Mass spectrometry was electron impact mass spectrometry (EI-MS), field desorption mass spectrometry (FD-MS), fast atom bombardment mass spectrometry (FAB-MS), matrix-assisted laser desorption ionization time-of-flight mass spectrometry (MALDI-TOF MS) or electron spray mass spectrometry ( ESI-MS). The detection samples applicable to the mass spectrometry detection of the present invention include but are not limited to various organic and inorganic small molecules, polymer compounds, viruses, microorganisms, nucleotides, nucleosides, oligonucleotides, nucleic acids, amino acids, peptides, proteins, lipids, At least one of sugars, carbohydrates, antigens, antibodies, cells and cell metabolites, but not limited thereto.

The silicon-based lattice with an array structure of the present invention can also be used in Raman detection, and the silicon-based lattice with an array structure of the present invention can be used as a Raman detection substrate. The method specifically includes: first configuring rhodamine (Rhodamine6G, R6G) reagent with a concentration of 10 ^-4 to 10 ^-8 mol/L as a probe molecule, and drip-coating it on the substrate of the array structure silicon-based lattice array chip The Raman spectrogram is tested on the XploRA Raman instrument, and the test conditions are: the incident light wavelength is 532nm, the laser power is 0.2mW, and the scanning time is 5s.

The silicon-based lattice with the array structure of the present invention can also be used in biosensors or photodetectors.

Compared with prior art, the beneficial effect of the present invention is:

(1) The present invention uses the solution method to self-assemble the micro-nanosphere mask. Compared with the self-assembled micro-nanosphere mask by the spin coating method, the process is simple and the consumables are less, and it can only have three-dimensional micro-nanospheres in the spotting area. Structural arrays, resulting in differences in the properties of the spotting area and the non-spotting area;

(2) Metal nanoparticles such as Au, Ag, Cu, Al, Ti, Ni, Pt, etc. are sputtered on the surface of the array structure of the spotting area of the present invention, and the local surface plasmon resonance characteristics of the metal nanostructure are used to promote the analysis of samples. Desorption and ionization; sputtering TiO ₂ , Al ₂ O ₃ , ZnO, ZrO ₂ layers on the surface can make the three-dimensional micro-nano structure array have photocatalytic properties; sputtering a polymer layer on the surface can make the surface of the array structure have excellent Hydrophobic. These properties make it a potential application prospect in biochemical sample analysis, photocatalysis and optoelectronic information.

(3) The preparation method provided by the present invention has a simple process, and an array structure silicon-based lattice with a three-dimensional micro-nano structure array can be prepared through a simple combination of semiconductor processing techniques. Compared with the traditional preparation of micro-nano structures on the surface of a flat substrate array, the present invention can prepare a three-dimensional micro-nano structure array array structure silicon-based lattice on the surface of a stepped substrate, and at the same time, the three-dimensional micro-nano structure array prepared by the present invention has the same appearance, tight and uniform arrangement.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Anyone skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (12)

1. a preparation method of array structure silicon-based lattice, is characterized in that, described preparation method comprises: Spin-coat photoresist on the surface of a silicon wafer; Forming a spotting area of a specific size on the surface of the silicon wafer by photolithography; Using a solution method to self-assemble micro-nanospheres on the surface of the silicon wafer containing the sample area; Etching the silicon wafer deposited with micro-nano spheres, so that the spotting area forms a micro-nano structure array, and the micro-nano structure array includes several micro-nano structures; removing the photoresist on the surface of the silicon wafer; and removing the micro-nano balls on the surface of the silicon wafer. 2. preparation method as claimed in claim 1 is characterized in that, after adopting photolithography method to form the pattern area of specific size on the surface of described silicon wafer, further comprising: engraving on the surface of silicon wafer of described area of pattern Etching forms grooves. 3. The preparation method according to claim 1, wherein the step of removing the photoresist on the surface of the silicon wafer is to place the silicon wafer in an acetone solution and vibrate for 10 minutes to remove the photoresist. The step of forming the micro-nano balls on the surface of the silicon chip is to place the silicon chip in a tetrahydrofuran solution or a strong alkali solution or anneal at a high temperature to remove the micro-nano balls. 4. The preparation method according to claim 1, characterized in that, after removing the micro-nanospheres on the surface of the silicon wafer, further comprising: depositing a material layer on the surface of the silicon wafer, the material layer adopts a single layer or multiple layers, the thickness of the material layer is 5 nm-1 µm; and dicing the silicon wafer. 5. A silicon-based lattice with an array structure, made by any one of the preparation methods in claims 1 to 4, characterized in that: the silicon-based lattice of the array includes a dotted area and a peripheral area, wherein the dots The sample area has a micro-nano structure array and a material layer wrapped on the surface of the micro-nano structure; the height of the micro-nano structure is 10 nm-100 µm, and the equivalent diameter or equivalent side length is 10 nm-100 µm. The distance between adjacent micro-nano structures is 10 nm-10 µm; the material is single-layer or multi-layer, and the thickness of the material layer is 5 nm-1 µm. 6. The array structure silicon-based lattice as claimed in claim 5, wherein the shape of the dotted area is a concave or raised circle or a regular polygon, wherein the regular polygon includes a square, a regular triangle or a regular hexagon ; The side length of the regular polygon spotting area is 10 µm-5 mm, and the diameter of the circular spotting area is 10 µm-5 mm; the depth of the depression or the height of the protrusion is 10 nm-100 µm, so The distance between the above-mentioned adjacent sample areas is 10 µm-10 mm. 7. The array structure silicon-based lattice as claimed in claim 6, characterized in that, after adopting a photolithography method to form a spotting area of a specific size on the surface of the silicon wafer, further comprising: silicon in the spotting area The surface of the sheet is etched to form grooves, and the sum of the height of the micro-nano structure and the depth of the grooves in the spotting area is the depression depth of the spotting area. 8. The silicon-based lattice with an array structure according to claim 5, wherein the material of the material layer can be metal, metal oxide, metal nitride or polymer, or a combination of the materials. 9. The array structure silicon-based lattice as claimed in claim 8, wherein said metal comprises at least one or a combination thereof in Au, Ag, Cu, Al, Ti, Rh, Ni, Pt; said metal The oxide includes at least one of Al ₂ O ₃ , ZnO, TiO ₂ , ZrO ₂ or a combination thereof; the metal nitride includes at least one of TiN, GaN, AlN or a combination thereof; the polymer It includes at least one of polyethylene, polyvinyl chloride, phenolic resin or a combination thereof. 10 . The silicon-based lattice with an array structure according to claim 5 , wherein the shape of the micro-nano structure includes one of cone, column, barrel, bottle, bowl, spherical, and hemispherical. 11. An application of a silicon-based lattice with an array structure in mass spectrometry detection or Raman detection or in a biosensor or photodetector, characterized in that, the silicon-based lattice with an array structure is based on any of claims 1 to 4 An array structure silicon-based lattice made by the method described in one item or an array structure silicon-based lattice according to any one of claims 6-10. 12. The application according to claim 11, wherein the mass spectrometry is electron bombardment mass spectrometry (EI-MS), field desorption mass spectrometry (FD-MS), fast atom bombardment mass spectrometry (FAB-MS), matrix Laser-Assisted Desorption Ionization Time-of-Flight Mass Spectrometry (MALDI-TOF MS) or Electron Spray Mass Spectrometry (ESI-MS).