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CN111009499A - 半导体器件和形成半导体器件的方法 - Google Patents

半导体器件和形成半导体器件的方法 Download PDF

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Publication number
CN111009499A
CN111009499A CN201910948702.5A CN201910948702A CN111009499A CN 111009499 A CN111009499 A CN 111009499A CN 201910948702 A CN201910948702 A CN 201910948702A CN 111009499 A CN111009499 A CN 111009499A
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region
semiconductor device
metal
metal layer
layer structure
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CN111009499B (zh
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S·拜尔
M·A·博代亚
黄佳艺
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

提供了一种半导体器件。半导体器件可以包括半导体衬底，该半导体衬底包括有源区域，在有源区域上方的金属层结构，其中，金属层结构被配置为形成电触点，该金属层结构包括焊接区域、缓冲区域及焊接区域和缓冲区域之间的阻挡区域，其中，在阻挡区域中，金属层结构比在焊接区域和缓冲区域中更远离有源区域，并且其中，焊接区域和缓冲区域中的每个与有源区域直接接触或者与在有源区域和金属层结构之间布置的布线层结构直接接触。

Description

半导体器件和形成半导体器件的方法
技术领域
各种实施例总体上涉及半导体器件和形成半导体器件的方法。
背景技术
最近刚刚开发了在晶体管外形(TO)封装中使用铜(Cu)夹，其中将软焊料、扩散焊料或焊膏用于夹子(clip)附接。在夹子附接期间，焊料覆盖(在夹子下面)是关键工艺，其被控制以确保夹子下方的大于约80％被焊料覆盖。
这对于获得低RDS(on)、高功率效率以及从源极焊盘到引线框架的良好互连是重要的。
然而，控制焊料渗出并同时确保夹子下的良好焊料覆盖是具有挑战性的。过量的焊料渗出可能污染焊盘，这可能在渗出的焊料到达附加的接合焊盘(触点)的情况下导致短路，并且可能在引线键合期间导致焊盘上的不粘焊。
在现有技术中，提供夹子和附加接合焊盘之间的间隙，以防止渗出的焊料到达附加的接合焊盘。
然而，这可能具有芯片尺寸增加的缺点。
相反，减小夹子尺寸导致高RDS(on)、通过夹子的芯片冷却更差、关于安全操作区域(SOA)的性能更差、以及成本效率降低。
发明内容
提供了一种半导体器件。半导体器件可以包括半导体衬底，该半导体衬底包括有源区域，在有源区域上方的金属层结构，其中，金属层结构被配置为形成电触点，该金属层结构包括焊接区域、缓冲区域及焊接区域和缓冲区域之间的阻挡区域，其中，在阻挡区域中，金属层结构比在焊接区域和缓冲区域中更远离有源区域，并且其中，焊接区域和缓冲区域中的每个与有源区域直接接触或者与在有源区域和金属层结构之间布置的布线层结构直接接触。
附图说明
在附图中，相似的附图标记在全部不同视图中通常指代相同的部件。附图不一定按比例绘制，而是通常将重点放在说明本发明的原理上。在以下描述中，参考以下附图描述本发明的各种实施例，其中：
图1示出了根据现有技术的半导体器件；
图2A至2C各自示出了根据各种实施例的半导体器件的示意性截面图；
图3示出了根据各种实施例的半导体器件的阻挡结构的放大视图；
图4示出了根据各种实施例的半导体器件的钝化层的示意性顶视图；
图5A和图5B各自示出了根据各种实施例的半导体器件的钝化层的示意性顶视图；
图6示出了根据各种实施例的形成半导体器件的方法的流程图。
具体实施方式
以下具体实施方式参考了附图，附图通过图示的方式示出了可以实践本发明的具体细节和实施例。
本文使用词语“示例性”来表示“用作示例、实例或说明”。本文描述为“示例性”的任何实施例或设计不一定被解释为比其他实施例或设计更优选或更有优势。
关于在侧面或表面“上方”形成的沉积材料使用的词语“在……上方”可以在本文中用于表示沉积材料可以“直接”形成在隐含的侧面或表面上，例如直接接触。关于在侧面或表面“上方”形成的沉积材料使用的词语“在……上方”可以在本文中用于表示沉积材料可以“间接地”形成在隐含的侧面或表面上，其中在隐含的侧面或表面与沉积材料之间布置一个或多个附加层。
如图1所示，在根据现有技术的半导体器件100中，例如，在晶体管中，金属夹104可以焊接到金属层结构108，其中金属层结构108被配置为电触点。在焊接过程中，焊料106可能从夹子104下方渗出。例如，主要可以在夹子104的左侧看到渗出的焊料106。同样在底部的放大视图中，大部分焊料布置在夹子104的左侧。渗出的焊料106可能导致一方面由于在夹子104和金属层结构108之间的间隙中缺少焊料106另一方面由于间隙外的过量焊料106而引起的若干不希望的效果。焊料可以是焊料金属或焊料金属膏。举例来说，焊料可以是无铅的或者可以包括铅。焊料可包括或基本上由以下材料中的一种或多种组成：SnAg和/或Pb和/或SnAgSb。
关于间隙外的过量焊料106，焊料渗出可能到达形成另外的电触点并且位于金属层结构108附近的接合焊盘112。因此，渗出的焊料106可以在金属层结构108和一个或多个接合焊盘112之间形成短路接触。即使焊料106没有完全到达接合焊盘112，液体焊料106也可能释放污染物，这些污染物可能沉积在附近的接合焊盘112上。在引线键合工艺期间，受污染的接合焊盘112可以比未受污染的接合焊盘112的粘附力小，这可能在引线键合期间导致所谓的“焊盘上的不粘接”。即，与接合焊盘接触的导线，例如如图1的底部图像所示，可能容易失去与接合焊盘112的接触，从而可能损害半导体器件100的可靠性。
此外，金属层结构108上的过量焊料106可以降低对封装材料的粘附力，封装材料例如是可以布置在金属层结构108和夹子104上的模具(未示出)。
在各种实施例中，在半导体器件中形成阻挡区域。阻挡结构被配置为将焊料(该焊料可用于将接触结构(例如夹子)焊接到金属层结构(其被配置为半导体器件的电触点))限制到焊接区域，即，形成焊料储存(reservoir)。因此，一方面可以确保在焊接区域中保留足够的焊料以确保超过80％的接触结构(夹子)焊料表面被焊料覆盖，另一方面，可以确保没有或只有少量焊料溢出阻挡区域朝向缓冲区域。焊接区域、阻挡区域和缓冲区域都可以被金属层结构覆盖，并且在阻挡区域中，金属层结构可以更远离半导体衬底，半导体衬底是半导体器件的一部分，并且在其中或其上形成有源区域。有源区域可以被金属层结构覆盖。
即，在半导体器件中包括阻挡基底结构，以便形成用于焊料渗出控制的焊料储存。
可以通过在半导体衬底上或上方布置阻挡基底结构并且通过在半导体衬底上方且在阻挡基底结构上方布置金属层结构来形成阻挡结构。
图2A至2C各自示出了根据各种实施例的半导体器件200的示意性截面图，图3示出了根据各种实施例的半导体器件200的阻挡结构220的放大视图，图4示出了根据各种实施例的半导体器件200的钝化层的示意性顶视图，并且图5A和图5B各自示出了根据各种实施例的半导体器件200的钝化层的示意性顶视图。
在各种实施例中，半导体器件200可以包括在半导体衬底234上方形成的金属层结构108。半导体器件200可以包括器件的有源区域226。有源区域226可以暴露在半导体衬底234的第一表面(例如，顶表面，例如图2A和图2C中)上，或者可以被例如布线层结构236覆盖(参见图2B)。
有源区域226可以被金属层结构108覆盖。金属层结构108可以是单个金属层108或包括多个金属层的金属层堆叠108。金属层结构的金属可以包括通常用于形成电触点并适用于半导体器件200的任何金属或金属组合或由其组成，例如铜、铜合金、铜铬合金、金、铝、镍、镍合金、钛、钛合金、钨、钨合金和/或钛钨合金。金属层结构108的厚度可以在约100nm至约100μm的范围内，例如在约1μm至约10μm的范围内，例如约5μm。
金属层结构108和(如果适用的话)布线层结构236可以如本领域中已知的通过沉积工艺，例如，气相沉积工艺、电镀工艺等形成。可以使用掩模，例如使用光刻掩模工艺，进行金属层结构108和(如果适用的话)布线层结构236的结构化。
布线层结构236可以是单个金属层236或包括多个金属层的金属层堆叠236。布线层结构236可以包括通常用于形成布线层结构236并适用于半导体器件200的任何金属或金属组合或由其组成，例如铜、金、铝、镍、镍合金、钯、钯合金和/或镍钯合金。
半导体器件200可以例如形成分立的电子元件，例如，二极管、晶闸管、MOSFET、CoolMOS和IGBT。半导体器件200可以例如形成功率电子元件。半导体器件200可以被配置为具有穿过半导体器件200的沿垂直方向流动的电流。
金属层结构108可以被配置为形成半导体器件200的电触点(例如，源极触点)。
金属层结构108可以包括焊接区域230、缓冲区域232、以及焊接区域230和缓冲区域232之间的阻挡区域220。
焊接区域230、缓冲区域232和阻挡区域220可以形成为一个连续的金属层结构108，并且可以通过它们的相对位置、它们的形状和/或它们的功能来区分，如下所述。
焊接区域230和缓冲区域232中的每一个可以与有源区域226直接接触，或者与在有源区域和金属层结构108之间布置的布线层结构236直接接触。即，金属层结构108可以布置成覆盖有源区域226，使得由金属层结构108提供的到有源区域226的电接触(通过布线层236的直接接触或间接接触)在有源区域226的整个区域上延伸以确保高效率。
在阻挡区域220中，金属层结构108可以比在焊接区域230中和在缓冲区域232中更远离有源区域226。在阻挡区域220中，可以将金属层结构108布置在阻挡基底结构228上方。即，可以在半导体衬底234上方，例如，在有源区域226上或在布线层236上，形成阻挡基底结构228，并且可以在其(以及相应地在有源区域226或布线层236的其余部分)上方形成金属层结构108。
阻挡基底结构228可以是单个阻挡基底层或包括多个阻挡基底层的阻挡基底层堆叠。阻挡基底结构228可以如本领域中已知的例如通过沉积工艺，例如，气相沉积工艺、电镀工艺等形成。可以使用掩模，例如使用光刻掩模工艺，进行阻挡基底结构228的结构化。
在各种实施例中，阻挡基底结构228可以包括介电材料或由介电材料组成，例如，酰亚胺、氧化物和/或氮化物。在半导体器件200包括例如在有源区域226外部(或者，相应地在布线层236外部)的半导体衬底234上方(例如上)的钝化层224的情况下，这可能是有利的。在这种情况下，可以将钝化层224的材料选择为与阻挡基底结构228的介电材料相同(反之亦然)，这意味着可以同时形成钝化层224和阻挡基底结构228。即，在这种情况下，可能不需要额外的(相对于形成现有技术的半导体器件100的工艺)处理步骤来形成阻挡基底结构228。而是可以仅修改用于形成钝化层224的掩模以同样形成阻挡基底结构228。
在各种实施例中，阻挡基底结构228可以包括金属或由金属组成，例如铜、铜合金、铜铬合金、金、铝、镍、镍合金、钛、钛合金、钨、钨合金和/或钛钨合金。因此，也可以在阻挡区域220和有源区域226(或者相应的布线层结构236)之间提供直接导电接触。在各种实施例中，阻挡基底结构228的金属可以与金属层结构220的金属相同。在金属层结构220形成层堆叠的情况下，阻挡基底结构228的金属可以与金属层结构220的直接接触阻挡基底结构228的层相同。
在各种实施例中，阻挡基底结构228可包括一个或多个金属层和一个或多个介电层的混合物。
在各种实施例中，阻挡基底结构228的高度可以在约3μm至约100μm的范围内，例如约10μm至约50μm，例如约25μm。阻挡基底结构228的宽度可以在约2μm至约25μm的范围内，例如约5μm至约20μm，例如约13μm。在各种实施例中，阻挡基底结构228的宽度可以大于其高度。阻挡基底结构228的宽度可以通过(例如，光刻工艺的)技术限制来确定。例如，将酰亚胺用于阻挡基底结构228的情况下，对于厚度为6μm的阻挡基底结构228可以实现10μm的宽度。
半导体器件200还可以包括一个或多个另外的电触点，如图1中所示的另外的电触点112。它们各自的位置在图4、图5A和图5B的每一个中通过钝化层224包围的四个钝化层自由区域440来表示。阻挡区域可以(至少)布置在焊接区域230和另外的电触点112之间。因此，可以防止或至少减轻在焊接过程期间焊料流向另外的电触点112。因此，可以避免由金属层结构108提供的触点与另外的电触点112之间的短路，并且还可以避免或至少减轻另外的电触点112的污染。
这意味着，在各种实施例中，可以优化夹子104下方的焊料106覆盖，以确保产品的低RDS(on)和高功率效率。这将有助于防止在夹子104附接期间或之后由于焊料106污染接合焊盘112而导致的抬升的焊盘上导线的可靠性问题。
为了刚好在焊接区域230和另外的电触点112之间形成阻挡区域，阻挡基底结构228可以例如成形为焊接区域230和另外的电触点112之间的连续壁或者中断壁。
在各种实施例中，阻挡基底结构228可以形成为环绕焊接区域230。从而，可以改善将焊料106限制到焊接区域230(即，形成焊料106储存)的能力，从而避免金属层结构108和金属接触结构104的焊接部分(焊接到或配置为焊接到金属层结构108)之间的空隙。
环绕的阻挡基底结构228在其形成自身闭合的结构的意义上可以是环形的。其形状可以是例如圆形、椭圆形或多边形(例如矩形，例如正方形，例如带有倒角的)环。
环形阻挡基底结构228可以成形为连续或中断的环。
在各种实施例中，阻挡基底结构228可以具有能够提高焊料106在焊接区域230的限制和/或有助于防止对缓冲区域232和/或另外的触点112的污染的任何其他形状，例如L形结构、U形结构、在焊接区域230的两个相对侧上各自的一个壁等。
缓冲区域232和/或另外的触点112的污染的减少或避免可以改善接合线(参见图1)和另外的触点112之间的接触质量，并且还改善了封装材料(未示出)与缓冲区域232的粘附性，并避免或减轻了焊接区域230外的枝晶生长。
在各种实施例中，中断的阻挡基底结构228(中断壁、环、L形/U形结构等)可以以如下方式形成，使得相邻的阻挡基底结构部分之间的距离使得它们在金属层结构108形成在阻挡基底结构228上方时由金属层结构108填充，即，具有约为金属层结构108的厚度的两倍的距离。在以较大距离布置阻挡基底结构段的情况下，该距离可以足够小，使得焊料106仍然保留在焊接区域230上。
在各种实施例中，例如，如图5A和图5B所示，阻挡基底结构228可以形成为双阻挡基底结构228、228_2。即，金属层结构108可以包括在阻挡区域220和缓冲区域232之间的另外的阻挡区域220_2。阻挡区域220和另外的阻挡区域220_2之间的金属层结构108的区域可以被认为是中间缓冲区域232i(参见图2C)。
在各种实施例中，另外的阻挡区域220_2可以形成为环绕或部分环绕阻挡区域220。
阻挡区域220与另外的阻挡区域220_2之间的距离(并且相应地，阻挡基底结构228与另外的阻挡基底结构228_2之间)的距离可以在约20μm至约100μm的范围内，例如30μm。
在各种实施例中，可以提供多于两个阻挡区域，例如，三个或更多阻挡区域。参见例如图5B，其中壁形阻挡基底结构228_3形成在矩形双阻挡基底结构228、228_2外的两侧上。
图3中的放大图像示出了阻挡区域220(铜)的截面图，其中下方具有阻挡基底结构228(酰亚胺)。在阻挡基底结构228和金属层结构108下方，布线层236(AlCu)布置在有源区域226上。在从焊接区域230上升到阻挡区域220的过渡区域中，金属层结构108可以以大致垂直和大致与垂直呈60°之间的角度布置，并且对称地布置在从缓冲区域232上升到阻挡区域220的过渡区域中。这意味着阻挡基底结构228可以形成有导致所描述的金属层结构108的布置的轮廓。通常，阻挡基底结构228可以形成有尽可能陡峭的侧壁，同时仍然确保金属层结构108对基底阻挡结构228的不间断覆盖。可以以类似的形状形成另外的基底阻挡结构228_2。
如上所述，半导体器件200可以包括金属接触结构104，例如，金属夹，具有焊接到金属层结构108的焊接区域230的焊接部分。金属夹104的宽度可以在约1mm至约2mm的范围内，并且高度可以在约3mm至约5mm的范围内。
在各种实施例中，焊接区域230的横向尺寸可以被配置为基本上匹配焊接部分的横向尺寸。例如，由内部阻挡基底结构228围绕的区域的宽度和长度(其基本上(除了要布置在阻挡基底结构228上方的金属层结构108)在尺寸上对应于焊接区域230)与金属接触结构104的焊接部分相比，可以略微更大(例如，在每个尺寸上为约5％至约10％)。即，阻挡区域220可以在金属接触结构104(例如，夹子)外部横向形成。
在各种实施例中，阻挡区域220可以以如下方式布置，使得其与金属层结构108的相对边缘具有相同或近似相同的距离。
在各种实施例中，半导体器件200可以包括多个有源区域226(即，多个半导体元件)和多个金属接触结构(例如，夹子)，其中可以为每个半导体元件提供其自身的阻挡结构220。
图6示出了根据各种实施例的形成半导体器件的方法的流程图600。
该方法可以包括在半导体衬底中形成有源区域(在610中)并在有源区域上方形成金属层结构，其中，金属层结构被配置为形成电触点，金属层结构包括焊接区域、缓冲区域、以及焊接区域与缓冲区域之间的阻挡区域，其中，在阻挡区域中，金属层结构比在焊接区域和缓冲区域中更远离有源区域，其中，焊接区域和缓冲区域中的每个与有源区域直接接触或者与在有源区域和金属层结构之间布置的布线层结构直接接触(在620中)。
以下将说明各种示例：
示例1是一种半导体器件。半导体器件可以包括半导体衬底，该半导体衬底包括有源区域，在有源区域上方的金属层结构，其中，金属层结构被配置为形成电触点，该金属层结构包括焊接区域、缓冲区域、以及焊接区域和缓冲区域之间的阻挡区域，其中，在阻挡区域中，金属层结构比在焊接区域和缓冲区域中更远离有源区域，并且其中，焊接区域和缓冲区域中的每个与有源区域直接接触或者与在有源区域和金属层结构之间布置的布线层结构直接接触。
在示例2中，示例1的主题可以可选地包括在阻挡区域中，金属层结构布置在阻挡基底结构上方。
在示例3中，示例1或2的主题可以可选地包括阻挡基底结构是单个阻挡基底层或包括多个阻挡基底层的阻挡基底层堆叠。
在示例4中，示例2或3的主题可以可选地包括阻挡基底结构包括介电材料或由介电材料组成。
在示例5中，示例4的主题可以可选地包括：阻挡基底结构的介电材料包括一组介电材料中的至少一种材料或由一组介电材料中的至少一种材料组成，该组由酰亚胺、氧化物和氮化物组成。
在示例6中，示例3至5中任一项的主题还可以可选地包括在有源区域外部的半导体衬底上方的钝化层。
在示例7中，示例6的主题可以可选地包括钝化层的材料与阻挡基底结构的介电材料相同。
在示例8中，示例6或示例7的主题可以可选地包括同时形成钝化层和阻挡基底结构。
在示例9中，示例2的主题可以可选地包括阻挡基底结构包括金属或由金属组成。
在示例10中，示例9的主题可以可选地包括阻挡基底结构的金属与金属层结构的金属相同。
在示例11中，示例1至10中任一项的主题还可以可选地包括另外的电触点，其中，阻挡区域布置在焊接区域和另外的电触点之间。
在示例12中，示例2至11中任一项的主题可以可选地包括形成阻挡基底结构以环绕焊接区域。
在示例13中，示例2至12中任一项的主题可以可选地包括阻挡基底结构形成为圆形、椭圆形或多边形环。
在示例14中，示例2至13中任一项的主题可以可选地包括将阻挡基底结构成形为中断的环。
在示例15中，示例2至14中任一项的主题可以可选地包括将阻挡基底结构成形为连续的环。
在示例16中，示例1至15中任一项的主题还可以可选地包括在阻挡区域和缓冲区域之间的另外的阻挡区域。
在示例17中，示例16的主题可以可选地包括形成另外的阻挡区域以环绕或部分环绕阻挡区域。
在示例18中，示例1至17中任一项的主题可以可选地包括金属层结构是单个金属层或包括多个金属层的金属层堆叠。
在示例19中，示例1至18中任一项的主题可以可选地包括金属层结构的金属包括一组金属和金属合金中的至少一种金属或金属合金，该组金属和金属合金由铜、铜合金、铜铬合金、金、铝、镍、镍合金、钛、钛合金、钨、钨合金和钛钨合金组成。
在示例20中，示例1至19中任一项的主题可以可选地包括布线层结构是单个金属层或包括多个金属层的金属层堆叠。
在示例21中，示例1至20中任一项的主题可以可选地包括布线层结构包括一组金属和金属合金中的至少一种金属或金属合金，该组金属和金属合金由铜、金、铝、镍、镍合金、钯、钯合金和镍钯合金组成。
在示例22中，示例1至21中任一项的主题可以可选地包括在从焊接区域上升到阻挡区域的过渡区域中，金属层结构以大致垂直和大致与垂直呈60°之间的角度布置。
在示例23中，示例1至22中任一项的主题可以进一步可选地包括金属接触结构，该金属接触结构具有焊接到焊接区域的焊接部分，其中，焊接区域的横向尺寸被配置为与焊接部分的横向尺寸基本上匹配。
在示例24中，示例23的主题可以可选地包括金属接触结构是金属夹。
在示例25中，示例24的主题可以可选地包括金属夹与焊接区域的整个表面重叠。
在示例26中，示例1至25中任一项的主题可以可选地包括半导体器件形成分立的电子元件。
在示例27中，示例1至26中任一项的主题可以可选地包括半导体器件形成一组电子元件中的一个，该组包括二极管、晶闸管、MOSFET、CoolMOS和IGBT。
在示例28中，示例1至27中任一项的主题可以可选地包括半导体器件形成功率电子元件。
在示例29中，示例1至28中任一项的主题可以可选地包括半导体器件被配置为具有穿过半导体器件沿垂直方向流动的电流。
在示例30中，示例2至29中任一项的主题可以可选地包括阻挡基底结构的高度在3μm至100μm的范围内。
示例31是一种形成半导体器件的方法。该方法可以包括在半导体衬底中形成有源区域，在有源区域上方形成金属层结构，其中，金属层结构被配置为形成电触点，金属层结构包括焊接区域、缓冲区域、以及焊接区域和缓冲区域之间的阻挡区域，其中，在阻挡区域中，金属层结构比在焊接区域和缓冲区域中更远离有源区域，其中，焊接区域和缓冲区域中的每个与有源区域直接接触或者与在有源区域和金属层结构之间布置的布线层结构直接接触。
在示例32中，示例31的主题还可以可选地包括：在形成金属层结构之前，在有源区域上方形成阻挡基底结构，其中，形成金属层结构包括在阻挡区域中在阻挡基底结构上方布置金属层结构。
在示例33中，示例32的主题可以可选地包括阻挡基底结构包括介电材料或由介电材料组成。
在示例34中，示例33的主题可以可选地包括阻挡基底结构的介电材料包括一组介电材料中的至少一种材料或由一组介电材料中的至少一种材料组成，该组由酰亚胺、氧化物和氮化物组成。
在示例35中，示例33或34的主题还可以可选地包括在形成阻挡基底结构的同时，在有源区域外部的半导体衬底上方形成钝化层。
在示例36中，示例35的主题可以可选地包括钝化层的材料与阻挡基底结构的介电材料相同。
在示例37中，示例32的主题可以可选地包括阻挡基底结构包括金属或由金属组成。
在示例38中，示例37的主题可以可选地包括阻挡基底结构的金属与金属层结构的金属相同。
在示例39中，示例31至38中任一项的主题还可以可选地包括将金属接触结构的焊接部分焊接到焊接区域。
在示例40中，示例39的主题可以可选地包括焊接区域的横向尺寸被配置为与焊接部分的横向尺寸基本上匹配。
在示例41中，示例31至40中任一项的主题可以可选地包括阻挡基底结构是单个阻挡基底层或包括多个阻挡基底层的阻挡基底层堆叠。
在示例42中，示例31至41中任一项的主题还可以可选地包括另外的电触点，其中，阻挡区域布置在焊接区域和另外的电触点之间。
在示例43中，示例32至42中任一项的主题可以可选地包括形成阻挡基底结构以环绕焊接区域。
在示例44中，示例31至43中任一项的主题可以可选地包括将阻挡基底结构形成为圆形、椭圆形或多边形环。
在示例45中，示例32至44中任一项的主题可以可选地包括将阻挡基底结构成形为中断的环。
在示例46中，示例32至45中任一项的主题可以可选地包括将阻挡基底结构成形为连续的环。
在示例47中，示例31至46中任一项的主题还可以可选地包括在阻挡区域和缓冲区域之间的另外的阻挡区域。
在示例48中，示例47的主题可以可选地包括形成另外的阻挡区域以环绕或部分环绕阻挡区域。
在示例49中，示例31至48中任一项的主题可以可选地包括金属层结构是单个金属层或包括多个金属层的金属层堆叠。
在示例50中，示例31至49中任一项的主题可以可选地包括金属层结构的金属包括一组金属和金属合金中的至少一种金属或金属合金，该组金属和金属合金由铜、铜合金、铜铬合金、金、铝、镍、镍合金、钛、钛合金、钨、钨合金和钛钨合金组成。
在示例51中，示例31至50中任一项的主题可以可选地包括布线层结构是单个金属层或包括多个金属层的金属层堆叠。
在示例52中，示例31至51中任一项的主题可以可选地包括布线层结构包括一组金属和金属合金中的至少一种金属或金属合金，该组金属和金属合金由铜、金、铝、镍、镍合金、钯、钯合金和镍钯合金组成。
在示例53中，示例31至52中任一项的主题可以可选地包括在从焊接区域上升到阻挡区域的过渡区域中，金属层结构以大致垂直和大致与垂直呈60°之间的角度布置。
在示例54中，示例39至53中任一项的主题可以进一步可选地包括金属接触结构是金属夹。
在示例55中，示例31至54中任一项的主题可以可选地包括半导体器件形成分立的电子元件。
在示例56中，示例31至55中任一项的主题可以可选地包括半导体器件形成一组电子元件中的一个，该组包括二极管、晶闸管、MOSFET、CoolMOS和IGBT。
在示例57中，示例31至56中任一项的主题可以可选地包括半导体器件形成功率电子元件。
在示例58中，示例31至57中任一项的主题可以可选地包括半导体器件被配置为具有穿过半导体器件沿垂直方向流动的电流。
在示例59中，示例32至58中任一项的主题可以可选地包括阻挡基底结构的高度在3μm至100μm的范围内。
尽管已经参考具体实施例具体示出和描述了本发明，但是本领域技术人员应该理解，在不脱离由所附权利要求限定的本发明的精神和范围的情况下，可以在形式和细节上进行各种改变。因此，本发明的范围由所附权利要求指示，并且因此旨在涵盖属于权利要求的等同变换的含义和范围内的所有改变。

Claims (30)

1.一种半导体器件(200)，包括：
半导体衬底(234)，包括有源区域(226)；
金属层结构(108)，在所述有源区域(226)上方，其中，所述金属层结构(108)被配置为形成电触点，所述金属层结构(108)包括：
焊接区域(230)，
缓冲区域(232)，
在所述焊接区域(230)和所述缓冲区域(232)之间的阻挡区域(220)，
其中，在所述阻挡区域(220)中，所述金属层结构(108)布置在包括介电材料或由介电材料组成的阻挡基底结构(228)上方；以及
钝化层(224)，所述钝化层在所述有源区域(226)外部的所述半导体衬底(234)上方与所述阻挡基底结构(228)同时形成，
其中，所述钝化层(224)的材料与所述阻挡基底结构(228)的介电材料相同，
其中，在所述阻挡区域(220)中，所述金属层结构(108)比在所述焊接区域(230)和所述缓冲区域(232)中更远离所述有源区域(226)；
其中，所述焊接区域(230)和所述缓冲区域(232)中的每个与所述有源区域(226)直接接触，或者与在所述有源区域(226)和所述金属层结构(108)之间布置的布线层结构(236)直接接触。
2.根据权利要求1所述的半导体器件(200)，
其中，所述阻挡基底结构(228)是单个阻挡基底层或包括多个阻挡基底层的阻挡基底层堆叠。
3.根据权利要求1或2所述的半导体器件(200)，
其中，所述阻挡基底结构(228)的介电材料包括一组介电材料中的至少一种材料或由一组介电材料中的至少一种材料组成，所述组包括：
酰亚胺；
氧化物；以及
氮化物。
4.根据权利要求1所述的半导体器件(200)，
其中，所述阻挡基底结构(228)包括金属。
5.根据权利要求4所述的半导体器件(200)，
其中，所述阻挡基底结构(228)的金属与所述金属层结构(108)的金属相同。
6.根据权利要求1至5中任一项所述的半导体器件(200)，还包括：
另外的电触点(112)，
其中，所述阻挡区域(220)布置在所述焊接区域(230)和所述另外的电触点(112)之间。
7.根据权利要求1至6中任一项所述的半导体器件(200)，
其中，形成所述阻挡基底结构(228)以环绕所述焊接区域(230)。
8.根据权利要求1至7中任一项所述的半导体器件(200)，
其中，所述阻挡基底结构(228)形成为圆形、椭圆形或多边形环。
9.根据权利要求1至8中任一项所述的半导体器件(200)，
其中，将所述阻挡基底结构(228)成形为中断的环。
10.根据权利要求1至9中任一项所述的半导体器件(200)，
其中，将所述阻挡基底结构(228)成形为连续的环。
11.根据权利要求1至10中任一项所述的半导体器件(200)，还包括：
所述阻挡区域(220)和所述缓冲区域(232)之间的另外的阻挡区域(220_2)。
12.根据权利要求11所述的半导体器件(200)，
其中，形成所述另外的阻挡区域(220_2)以环绕所述阻挡区域(220)。
13.根据权利要求1至12中任一项所述的半导体器件(200)，
其中，所述金属层结构(108)是单个金属层或包括多个金属层的金属层堆叠。
14.根据权利要求1至13中任一项所述的半导体器件(200)，
其中，所述金属层结构(108)的金属包括一组金属和金属合金中的至少一种金属或金属合金，该组金属和金属合金由以下组成：
铜；
铜合金；
铜铬合金；
金；
铝；
镍；
镍合金；
钛；
钛合金；
钨；
钨合金；以及
钛钨合金。
15.根据权利要求1至14中任一项所述的半导体器件(200)，
其中，所述布线层结构(236)是单个金属层或包括多个金属层的金属层堆叠。
16.根据权利要求1至15中任一项所述的半导体器件(200)，
其中，所述布线层结构(236)包括一组金属和金属合金中的至少一种金属或金属合金，该组金属和金属合金由以下组成：
铜；
铝；
钨；
钛；
镍；
镍合金；
钯；
钯合金；
镍钯合金。
17.根据权利要求1至16中任一项所述的半导体器件(200)，
其中，在从所述焊接区域(230)上升到所述阻挡区域(220)的过渡区域中，所述金属层结构(108)以大致垂直和大致与垂直呈60°之间的角度布置。
18.根据权利要求1至17中任一项所述的半导体器件(200)，还包括：
金属接触结构(104)，所述金属接触结构具有焊接到所述焊接区域(230)的焊接部分，
其中，所述焊接区域(230)的横向尺寸被配置为与所述焊接部分的横向尺寸基本上匹配。
19.根据权利要求18所述的半导体器件(200)，
其中，所述金属接触结构(104)是金属夹。
20.根据权利要求19所述的半导体器件(200)，
其中，所述金属夹与所述焊接区域(230)的整个表面重叠。
21.根据权利要求1至20中任一项所述的半导体器件(200)，
其中，所述半导体器件(200)形成分立的电子元件。
22.根据权利要求1至21中任一项所述的半导体器件(200)，
其中，所述半导体器件(200)形成一组电子元件中的一个，所述组包括：
二极管，
晶闸管，
MOSFET；
CoolMOS；以及
IGBT。
23.根据权利要求1至22中任一项所述的半导体器件(200)，
其中，所述半导体器件形成功率电子元件。
24.根据权利要求1至23中任一项所述的半导体器件(200)，
其中，所述半导体器件被配置为具有穿过所述半导体器件沿垂直方向流动的电流。
25.根据权利要求1至24中任一项所述的半导体器件(200)，
其中，所述阻挡基底结构(228)的高度在3μm至100μm的范围内。
26.一种形成半导体器件的方法，所述方法包括：
在半导体衬底中形成有源区域(610)；
在所述有源区域上方形成阻挡基底结构；
在形成阻挡基底结构的同时，在所述有源区域外部的所述半导体衬底上方形成钝化层；
在所述有源区域上方形成金属层结构，其中，所述金属层结构被配置为形成电触点，并且其中，所述形成金属层结构包括在阻挡区域中在所述阻挡基底结构上方布置所述金属层结构，所述金属层结构包括：
焊接区域，
缓冲区域，以及
在所述焊接区域和所述缓冲区域之间的阻挡区域，
其中，在所述阻挡区域中，所述金属层结构比在所述焊接区域和所述缓冲区域中更远离所述有源区域；
其中，所述焊接区域和所述缓冲区域中的每个与所述有源区域直接接触或者与在所述有源区域和所述金属层结构之间布置的布线层结构直接接触。
27.根据权利要求26所述的方法，
其中，所述阻挡基底结构包括介电材料或由介电材料组成。
28.根据权利要求26所述的方法，
其中，所述阻挡基底结构包括金属。
29.根据权利要求28所述的方法，
其中，所述阻挡基底结构的金属与所述金属层结构的金属相同。
30.根据权利要求26至29中任一项所述的方法，还包括：
将金属接触结构的焊接部分焊接到所述焊接区域，
其中，所述焊接区域的横向尺寸被配置为与所述焊接部分的横向尺寸基本上匹配。
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