CN110995183B - Self-adaptive linearization heterojunction bipolar transistor power amplifier - Google Patents

Abstract

The invention discloses an adaptive linearized heterojunction bipolar transistor power amplifier, comprising an input CLC matching network, an adaptive linearized bias network, a three-stacked heterojunction bipolar transistor amplification network, and an output CLC matching network. The core architecture of the invention adopts the high power and high gain characteristics of the three-stacked heterojunction bipolar transistor amplification network in the microwave band, and simultaneously utilizes the adaptive linearized bias network to adjust the static bias of each stacked transistor of the three-stacked heterojunction bipolar transistor amplification network when performing small signal and large signal power amplification, so that the entire power amplifier obtains good high gain, high linearity and high power output capability.

Description

An adaptive linearized heterojunction bipolar transistor power amplifier

Technical Field

The invention relates to the field of field effect transistor radio frequency power amplifiers and integrated circuits, and in particular to an adaptive linearized heterojunction bipolar transistor power amplifier applied to a transmitting module at the end of a radio frequency microwave transceiver.

Background Art

With the rapid development of wireless communication systems and RF microwave circuits, RF front-end transceivers are also developing towards high performance, high integration and low power consumption. Therefore, the market urgently needs the RF and microwave power amplifiers of transmitters to have high output power, high gain, high efficiency and low cost, and integrated circuits are the key technologies that are expected to meet this market demand.

However, when using integrated circuit technology to design and implement RF and microwave power amplifier chip circuits, their performance and cost are subject to certain constraints, mainly reflected in:

(1) Limited high power and high efficiency capabilities: Traditional power amplifiers have a small voltage swing and low single-tube output power, and often require the use of a multi-path parallel synthesis structure or a distributed structure. The synthesis efficiency of these two structures is limited, resulting in part of the power being lost in the synthesis network, limiting the high power and high efficiency capabilities.

(2) Limited linearity indicators: The bias circuit of a typical power amplifier network often has a relatively simple design method and cannot meet the improvement of linearity indicators. It often requires additional linearization circuits, which brings complex factors to the system application.

There are many common circuit structures of high-gain, high-power amplifiers, the most typical of which is a multi-stage, multi-channel synthesis single-ended power amplifier. However, it is very difficult for a traditional multi-stage, multi-channel synthesis single-ended power amplifier to meet the requirements of various parameters at the same time. This is mainly because: the output impedance of a traditional multi-stage, multi-channel synthesis single-ended power amplifier is low when a multi-channel parallel synthesis structure is used. Therefore, the output synthesis network needs to achieve impedance matching with a high impedance conversion ratio, which often requires sacrificing the gain of the amplifier and reducing the power, thereby limiting the high power and high efficiency capabilities.

In addition, typical traditional stacked heterojunction bipolar transistors often add a linearization bias network to the bottom bias network. Such a setting has limited improvement on the linearity index of the stacked amplifier and ignores the limitation of the bias circuit of the upper stacked transistor on linearity.

From this, it can be seen that the difficulties in designing high-gain, high-power amplifiers based on integrated circuit technology are: high-power, high-efficiency output is difficult; typical traditional stacked heterojunction bipolar transistors have limitations in the design of linear bias networks.

Summary of the invention

The technical problem to be solved by the present invention is to provide an adaptive linearized heterojunction bipolar transistor power amplifier, which combines the advantages of heterojunction bipolar transistor stacking technology and adaptive linearization technology, and has the advantages of high power, high gain and low cost in the microwave frequency band.

The technical solution of the present invention to solve the above technical problems is as follows: an adaptive linearized heterojunction bipolar transistor power amplifier, characterized in that it includes an input CLC matching network, an adaptive linearized bias network, a three-stacked heterojunction bipolar transistor amplification network, and an output CLC matching network;

The input end of the input CLC matching network is the input end of the entire power amplifier, and the output end thereof is connected to the first input end of the three-stack heterojunction bipolar transistor amplification network. Further, the input end RF _in of the input CLC matching network is connected to the microstrip line TL ₁ , the other end of the microstrip line TL ₁ is connected to the capacitor C _in1 , the other end of the capacitor C _in1 is connected to the grounded microstrip line TL ₂ and the capacitor C _in2 , and the other end of the capacitor C _in2 is connected to the output end of the input CLC matching network;

The beneficial effects of the above further solution are: the input CLC matching network adopted by the present invention can not only achieve impedance matching, but also improve the low-frequency stability of the circuit;

The input end, the first output end, the second output end and the third output end of the adaptive linearization bias network are respectively connected to the fifth input end, the second input end, the third input end and the fourth input end of the three-stack heterojunction bipolar transistor amplifier network. Further, the input end of the adaptive linearization bias network is connected to the collector of transistor _Qf1 , the resistor _Rg , the collector of transistor _Qf2 and the collector of transistor _Qf3 ; the other end of the resistor _Rg is connected to the base of transistor _Qf1 , the base of transistor _Qf2 , the base of transistor _Qf3 , the collector and base of transistor _Qd1 , and the grounding capacitor _Cb1 ; the emitter of transistor _Qf1 is connected to the third output end of the adaptive linearization bias network and the grounding resistor _Rs1 ; the emitter of transistor _Qf2 is connected to the second output end of the adaptive linearization bias network and the grounding resistor _Rs2 ; the emitter of transistor _Qf3 is connected to the first output end of the adaptive linearization bias network and the grounding resistor _Rs3 ; the emitter of transistor _Qd1 is connected to the collector and base of transistor _Qd2 , and the emitter of transistor Qd3 is connected to the collector and base of transistor Qd2. The emitter of _d2 is grounded;

The beneficial effects of the above further scheme are: the adaptive linearization bias network of the present invention can simultaneously perform linearization compensation for the base bias of three stacked heterojunction bipolar transistors, thereby greatly improving the linearization index of the stacked amplifier. In the small signal state, the bias point is a conventional deep AB class, and in the large signal state, the bias point of the amplifier is adjusted to a shallow AB class, thereby improving the linearity index;

The output end of the three-stack heterojunction bipolar transistor amplifier network is connected to the input end of the output CLC matching network. Further, the base of the transistor _Qs1 in the three-stack heterojunction bipolar transistor amplifier network is connected to the grounded capacitor _Cb2 and the resistor _Rt1 , and the other end of the resistor _Rt1 is connected to the fourth input end of the three-stack heterojunction bipolar transistor amplifier network; the collector of the transistor _Qs1 is connected to the microstrip line _TL5 and the output end of the three-stack heterojunction bipolar transistor amplifier network, and the other end of the microstrip line _TL5 is connected to the fifth input end of the three-stack heterojunction bipolar transistor amplifier network and the bias voltage _Vc ; the emitter of the transistor _Qs1 is connected to the microstrip line _TL4 , and the other end of the microstrip line _TL4 is connected to the collector of the transistor _Qs2 ; the base of the transistor _Qs2 is connected to the grounded capacitor _Cb3 and the resistor _Rt2 , and the other end of the resistor _Rt2 is connected to the third input end of the three-stack heterojunction bipolar transistor amplifier network; the emitter of the transistor _Qs2 is connected to the microstrip line _TL3 , and the microstrip line TL The other end of ₃ is connected to the collector of transistor Q _s3 ; the base of transistor Q _s3 is connected to the first input end of the three-stack heterojunction bipolar transistor amplifier network and resistor R _t3 , the other end of resistor R _t3 is connected to the second input end of the three-stack heterojunction bipolar transistor amplifier network, and the emitter of transistor Q _s3 is directly grounded;

The beneficial effects of the above further scheme are: the three-stacked heterojunction bipolar transistor amplifier network adopted by the present invention can increase the voltage swing of the amplifier, improve the power output capability and output impedance, and improve output matching;

The output end of the output CLC matching network is the output end of the entire power amplifier. Further, the input end of the output CLC matching network is connected to the microstrip line TL ₆ , the other end of the microstrip line TL ₆ is connected to the capacitor C _load , the other end of the capacitor C _load is connected to the microstrip line TL ₇ , the other end of the microstrip line TL ₇ is connected to the grounding capacitor C _out and the microstrip line TL ₈ , and the other end of the microstrip line TL ₈ is connected to the output end of the output CLC matching network;

The beneficial effect of the above further solution is that the output CLC matching network adopted by the present invention can achieve high-efficiency, low-insertion-loss output impedance matching, and at the same time has the function of direct-current isolation of RF signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a block diagram of a power amplifier according to the present invention;

FIG. 2 is a circuit diagram of a power amplifier according to the present invention.

DETAILED DESCRIPTION

Now, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the accompanying drawings are only exemplary and are intended to explain the principles and spirit of the present invention, rather than to limit the scope of the present invention.

The embodiment of the present invention provides an adaptive linearized heterojunction bipolar transistor power amplifier, comprising an input CLC matching network, an adaptive linearized bias network, a three-stacked heterojunction bipolar transistor amplification network, and an output CLC matching network.

As shown in FIG1 , the input end of the input CLC matching network is the input end of the entire power amplifier, and its output end is connected to the first input end of the three-stack heterojunction bipolar transistor amplification network;

The input terminal, the first output terminal, the second output terminal, and the third output terminal of the adaptive linearization bias network are respectively connected to the fifth input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the three-stack heterojunction bipolar transistor amplifier network;

The output end of the three-stack heterojunction bipolar transistor amplifier network is connected to the input end of the output CLC matching network;

The output end of the output CLC matching network is the output end of the entire power amplifier.

As shown in FIG2 , the input terminal RF _in of the input CLC matching network is connected to the microstrip line TL ₁ , the other end of the microstrip line TL ₁ is connected to the capacitor C _in1 , the other end of the capacitor C _in1 is connected to the grounded microstrip line TL ₂ and the capacitor C _in2 , and the other end of the capacitor C _in2 is connected to the output terminal of the input CLC matching network;

The input end of the adaptive linearization bias network is connected to the collector of transistor _Qf1 , resistor _Rg , collector of transistor _Qf2 , and collector of transistor _Qf3 ; the other end of resistor _Rg is connected to the base of transistor _Qf1 , base of transistor _Qf2 , base of transistor _Qf3 , collector and base of transistor _Qd1 , and grounded capacitor _Cb1 ; the emitter of transistor _Qf1 is connected to the third output end of the adaptive linearization bias network and grounded resistor _Rs1 ; the emitter of transistor _Qf2 is connected to the second output end of the adaptive linearization bias network and grounded resistor _Rs2 ; the emitter of transistor _Qf3 is connected to the first output end of the adaptive linearization bias network and grounded resistor _Rs3 ; the emitter of transistor _Qd1 is connected to the collector and base of transistor _Qd2 , and the emitter of transistor _Qd2 is grounded;

The base of transistor _Qs1 in the three-stack heterojunction bipolar transistor amplifier network is connected to the grounded capacitor _Cb2 and the resistor _Rt1 , and the other end of the resistor _Rt1 is connected to the fourth input end of the three-stack heterojunction bipolar transistor amplifier network; the collector of transistor _Qs1 is connected to the microstrip line _TL5 and the output end of the three-stack heterojunction bipolar transistor amplifier network, and the other end of the microstrip line _TL5 is connected to the fifth input end of the three-stack heterojunction bipolar transistor amplifier network and the bias voltage _Vc ; the emitter of transistor _Qs1 is connected to the microstrip line _TL4 , and the other end of the microstrip line _TL4 is connected to the collector of transistor _Qs2 ; the base of transistor _Qs2 is connected to the grounded capacitor _Cb3 and the resistor _Rt2 , and the other end of the resistor _Rt2 is connected to the third input end of the three-stack heterojunction bipolar transistor amplifier network; the emitter of transistor _Qs2 is connected to the microstrip line _TL3 , and the other end of the microstrip line _TL3 is connected to the collector of transistor _Qs3 ; The base of _s3 is connected to the first input terminal of the three-stack heterojunction bipolar transistor amplifier network and the resistor R _t3 , and the other end of the resistor R _t3 is connected to the second input terminal of the three-stack heterojunction bipolar transistor amplifier network. The emitter of transistor Q _s3 is directly grounded;

The input end of the output CLC matching network is connected to microstrip line TL ₆ , the other end of microstrip line TL ₆ is connected to capacitor C _load , the other end of capacitor C _load is connected to microstrip line TL ₇ , the other end of microstrip line TL ₇ is connected to ground capacitor C _out and microstrip line TL ₈ , and the other end of microstrip line TL ₈ is connected to the output end of the output CLC matching network.

The specific working principle and process of the present invention are introduced below in conjunction with FIG2:

The RF input signal enters the circuit through the input terminal RF _in , enters the first input terminal of the three-stack heterojunction bipolar transistor amplifier network after matching through the input CLC matching network, is power amplified through the amplifier network, is output from the output terminal of the three-stack heterojunction bipolar transistor amplifier network, and is output from the output terminal RF _out after impedance matching through the output CLC matching network. At the same time, the input terminal, the first output terminal, the second output terminal, and the third output terminal of the adaptive linearization bias network are respectively connected to the fifth input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the three-stack heterojunction bipolar transistor amplifier network to provide a suitable working state for the circuit.

Based on the above circuit analysis, the adaptive linearized heterojunction bipolar transistor power amplifier proposed by the present invention is different from the previous amplifier structure based on integrated circuit technology in that the core architecture adopts a three-stacked heterojunction bipolar transistor amplifier network with an adaptive linearized bias network:

The triple-stacked heterojunction bipolar transistor is very different in structure from the conventional single transistor, which will not be described here;

The difference between the three-stack heterojunction bipolar transistor and the cascode amplifier is that the stacked base compensation capacitor of the common-emitter tube of the cascode transistor is a capacitor with a large capacitance value, which is used to achieve AC grounding of the base, while the stacked base compensation capacitor of the common-emitter tube of the three-stack heterojunction bipolar transistor is a capacitor with a very small capacitance value, which is used to achieve AC synchronous swing of the base, non-AC grounding.

The adaptive linearization bias network can simultaneously perform linearization compensation for the base bias of three stacked heterojunction bipolar transistors, thereby greatly improving the linearization index of the stacked amplifier. In the small signal state, the bias point is the conventional deep class AB, and in the large signal state, the bias point of the amplifier is adjusted to the shallow class AB, thereby improving the linearity index.

In the entire adaptive linearized heterojunction bipolar transistor power amplifier, the size of the transistor and the sizes of other resistors and capacitors are determined after comprehensive consideration of various indicators such as the gain, bandwidth and output power of the entire circuit. Through subsequent layout design and reasonable layout, the required indicators can be better achieved, and high power output capability, high power gain, and good input-output matching characteristics can be achieved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (1)

1. The self-adaptive linearization heterojunction bipolar transistor power amplifier is characterized by comprising an input CLC matching network, a self-adaptive linearization bias network, a three-stack heterojunction bipolar transistor amplifying network and an output CLC matching network;

The input end of the input CLC matching network is the input end of the whole power amplifier, the output end of the input CLC matching network is connected with the first input end of the three-stacked heterojunction bipolar transistor amplifying network, namely, the input end RF _in of the input CLC matching network is connected with a microstrip line TL ₁, the other end of the microstrip line TL ₁ is connected with a capacitor C _in1, the other end of the capacitor C _in1 is connected with a grounding microstrip line TL ₂ and a capacitor C _in2, and the other end of the capacitor C _in2 is connected with the output end of the input CLC matching network;

The input end, the first output end, the second output end and the third output end of the self-adaptive linearization bias network are respectively connected with the fifth input end, the second input end, the third input end and the fourth input end of the three-stacked heterojunction bipolar transistor amplifying network, namely the input end of the self-adaptive linearization bias network is connected with the collector electrode of the transistor Q _f1, the resistor R _g, the collector electrode of the transistor Q _f2, a collector of transistor Q _f3; The other end of the resistor R _g is connected with the base electrode of the transistor Q _f1, the base electrode of the transistor Q _f2, the base electrode of the transistor Q _f3, the collector and base of transistor Q _d1, and ground capacitance C _b1; An emitter of the transistor Q _f1 is connected to the third output of the adaptive linearization bias network and to the ground resistor R _s1; an emitter of the transistor Q _f2 is connected to the second output of the adaptive linearization bias network and to the ground resistor R _s2; An emitter of the transistor Q _f3 is connected to the first output of the adaptive linearization bias network and to the ground resistor R _s3; an emitter of the transistor Q _d1 is connected with a collector and a base of the transistor Q _d2, and an emitter of the transistor Q _d2 is grounded;

the output end of the three-stacked heterojunction bipolar transistor amplifying network is connected with the input end of the output CLC matching network, namely, the base electrode of the transistor Q _s1 is connected with the grounding capacitor C _b2 and the resistor R _t1, and the other end of the resistor R _t1 is connected with the fourth input end of the three-stacked heterojunction bipolar transistor amplifying network; The collector of the transistor Q _s1 is connected with the microstrip line TL ₅ and the output end of the three-stacked heterojunction bipolar transistor amplification network, and the other end of the microstrip line TL ₅ is connected with the fifth input end of the three-stacked heterojunction bipolar transistor amplification network and the bias voltage V _c; An emitter of the transistor Q _s1 is connected with the microstrip line TL ₄, and the other end of the microstrip line TL ₄ is connected with a collector of the transistor Q _s2; The base electrode of the transistor Q _s2 is connected with the grounding capacitor C _b3 and the resistor R _t2, and the other end of the resistor R _t2 is connected with the third input end of the three-stacked heterojunction bipolar transistor amplifying network; An emitter of the transistor Q _s2 is connected with the microstrip line TL ₃, and the other end of the microstrip line TL ₃ is connected with a collector of the transistor Q _s3; The base electrode of the transistor Q _s3 is connected with the first input end of the three-stacked heterojunction bipolar transistor amplification network and the resistor R _t3, and the other end of the resistor R _t3 is connected with the emitter electrode of the transistor Q _s3 at the second input end of the three-stacked heterojunction bipolar transistor amplification network;

The output end of the output CLC matching network is the output end of the whole power amplifier, the input end is connected with a microstrip line TL ₆, the other end of the microstrip line TL ₆ is connected with a capacitor C _load, the other end of the capacitor C _load is connected with a microstrip line TL ₇, the other end of the microstrip line TL ₇ is connected with a grounding capacitor C _out and a microstrip line TL ₈, and the other end of the microstrip line TL ₈ is connected with the output end of the output CLC matching network.