CN110993656A - Display panel preparation method and display panel - Google Patents
Display panel preparation method and display panel Download PDFInfo
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- CN110993656A CN110993656A CN201911180213.6A CN201911180213A CN110993656A CN 110993656 A CN110993656 A CN 110993656A CN 201911180213 A CN201911180213 A CN 201911180213A CN 110993656 A CN110993656 A CN 110993656A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 285
- 239000004065 semiconductor Substances 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000004380 ashing Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 2
- 238000002834 transmittance Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention provides a preparation method of a display panel and the display panel, wherein a source drain electrode metal layer, a channel and a first electrode are formed by patterning a transparent electrode film layer and a second metal layer through a yellow light process. Specifically, the transparent electrode film layer and the second Metal layer are deposited on a planarization layer together as a new Metal layer (Metal2), and the transparent electrode film layer and the second Metal layer are patterned by utilizing the light transmittance of a half-tone mask plate. The invention reduces the number of mask plates, thereby achieving the purposes of reducing the preparation cost and increasing the preparation efficiency.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
White Light-Emitting diodes (OLEDs) have the advantage of high stability. But the number of the required mask plates is large during the preparation, the productivity can be greatly improved by reducing the number of the mask plates, and the cost is reduced.
As shown in fig. 1, in the current large-size display panel, generally, a source/drain metal layer 11 structure (mostly adopting a molybdenum and metal double-layer structure) is used, and a process from the source/drain metal layer 11 to a transparent electrode 14 structure requires preparation of 4 layers of structures (the source/drain metal layer 11, a passivation layer 12, a planarization layer 13, and the transparent electrode 14) and requires 4 mask plates.
Therefore, it is urgently needed to provide a new display panel, which can achieve the purpose of saving the mask plate and reduce the preparation cost.
Disclosure of Invention
The invention aims to form a source drain electrode metal layer, a channel and a first electrode by patterning the transparent electrode film layer and the second metal layer through a yellow light process. Therefore, the number of mask plates is reduced, the preparation cost is reduced, and the preparation efficiency is improved.
In order to achieve the above object, the present invention provides a method for manufacturing a display panel, comprising the steps of: providing a substrate; depositing a buffer layer on the substrate; depositing a semiconductor layer on the buffer layer; depositing a gate layer on the semiconductor layer; depositing a first metal layer on the gate layer; depositing an interlayer insulating layer and a planarization layer on the buffer layer in sequence; depositing a transparent electrode film layer and a second metal layer on the planarization layer; and patterning the transparent electrode film layer and the second metal layer by a yellow light process to form a source/drain metal layer, a channel and a first electrode.
Further, in the step of forming the source/drain metal layer, the channel, and the first electrode by patterning the transparent electrode film layer and the second metal layer through a yellow light process, the method specifically includes: providing a halftone mask, the halftone mask comprising: a full via and a semi-permeable region; coating a photoresist on the second metal layer; arranging the halftone mask plate above the photoresist; irradiating the photoresist through the halftone mask plate by using ultraviolet light to perform exposure development to obtain source/drain electrode patterns and first electrode patterns, wherein the first electrode patterns correspond to the semi-transparent area; etching the second metal layer and the transparent electrode film layer corresponding to the full through hole to form the channel; ashing the first electrode pattern; and etching the second metal layer corresponding to the first electrode pattern, and removing the source and drain electrode pattern to form the source and drain electrode metal layer.
Further, after the step of sequentially depositing an interlayer insulating layer and a planarization layer on the buffer layer, the method further includes: and forming a first through hole and a second through hole on the planarization layer, wherein the first through hole penetrates through the planarization layer and part of the interlayer insulating layer to the surface of the semiconductor layer, and the second through hole penetrates through the planarization layer and part of the interlayer insulating layer to the surface of the semiconductor layer.
Further, in the step of sequentially depositing a transparent electrode film layer and a second metal layer on the planarization layer, the method further includes: and sequentially depositing the transparent electrode film layer and the second metal layer in the first through hole and the second through hole.
Further, after the step of providing a substrate, the method includes: depositing a light shielding layer on the substrate.
Further, still include: depositing a pixel defining layer on the source drain metal layer, the planarization layer, the channel and the first electrode; forming a slot on the pixel defining layer, wherein the slot is recessed to the surface of the first electrode.
The present invention also provides a display panel, including: a substrate; the buffer layer is arranged on the substrate; a semiconductor layer disposed on the buffer layer; a gate layer disposed on the semiconductor layer; the first metal layer is arranged on the grid layer; an interlayer insulating layer disposed on the buffer layer, the semiconductor layer, and the first metal layer; a planarization layer disposed on the interlayer insulating layer; the planarization layer is provided with a first through hole and a second through hole, the first through hole penetrates through the planarization layer and a part of the interlayer insulating layer to the surface of the semiconductor layer, and the second through hole penetrates through the planarization layer and a part of the interlayer insulating layer to the surface of the semiconductor layer; a first electrode disposed on the planarization layer and in the first and second vias; and the source and drain electrode layer is arranged on the first electrode.
Further, still include: a light-shielding layer disposed in the buffer layer and corresponding to the semiconductor layer; and the RGB color resistors are arranged in the planarization layer.
Further, still include: the pixel limiting layer is arranged on the source drain electrode metal layer, the planarization layer, the channel and the first electrode; the pixel defining layer has a slot recessed to the surface of the first electrode
The invention has the beneficial effects that: the invention provides a preparation method of a display panel and the display panel, wherein a source drain electrode metal layer, a channel and a first electrode are formed by patterning a transparent electrode film layer and a second metal layer through a yellow light process. Specifically, the transparent electrode film layer and the second Metal layer are deposited on a planarization layer together as a new Metal layer (Metal2), and the transparent electrode film layer and the second Metal layer are patterned by utilizing the light transmittance of a half-tone mask plate. The number of mask plates is reduced, so that the preparation cost is reduced, and the preparation efficiency is improved.
Drawings
The invention is further described below with reference to the figures and examples.
Fig. 1 is a schematic structural diagram of a display panel in the prior art.
Fig. 2 is a schematic partial structural diagram of a manufacturing method of a display panel according to the present invention.
Fig. 3 is a structural diagram of depositing a second metal layer of a transparent electrode film layer on the basis of fig. 2.
Fig. 4 is a schematic structural diagram of a mask and an exposure photoresist provided on the basis of fig. 3.
Fig. 5 is a schematic view of the structure after developing the photoresist on the basis of fig. 4.
Fig. 6 is a schematic structural diagram of a channel and a first electrode formed after etching a pattern on the basis of fig. 5.
Fig. 7 is a schematic view of the structure after ashing the first electrode pattern on the basis of fig. 6.
Fig. 8 is a schematic structural view after etching a second metal layer corresponding to the first electrode pattern on the basis of fig. 7.
Fig. 9 is a schematic structural diagram after a source-drain pattern is removed on the basis of fig. 8.
Fig. 10 is a schematic structural view of a pixel defining layer prepared on the basis of fig. 9.
Fig. 11 is a schematic structural diagram of a display panel provided in the present invention.
A display panel 100;
a substrate 101; a light-shielding layer 103; a buffer layer 102;
a semiconductor layer 104; a gate layer 105; a first metal layer 106;
an interlayer insulating layer 107; a planarization layer 108; a first electrode 115;
source drain metal layer 116; a pixel defining layer 117; a slot 118;
an OLED functional device 120; a transparent electrode film layer 109; a second metal layer 110;
a photoresist 111; a halftone mask 200; a full via 201;
a semi-permeable region 202; source-drain patterns 113; a first electrode pattern 112;
a channel 114; RGB color resistance 119; a first through hole 1081;
second through hole 1082.
Detailed Description
In order that the present invention may be better understood, the following examples are included to further illustrate the invention, but not to limit its scope.
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc., refer to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
As shown in fig. 2, the present invention provides a method for manufacturing a display panel, comprising the steps of.
S1) providing a substrate 101.
S2) depositing a light-shielding layer 103 on the substrate 101.
S3) depositing a buffer layer 102 on the light-shielding layer 103 and the substrate 101.
S4) depositing a semiconductor layer 104 on the buffer layer 102.
S5) depositing a gate layer 105 on the semiconductor layer 104.
S6) depositing a first metal layer 106 and the gate layer 105.
S7) sequentially depositing an interlayer insulating layer 107 and a planarization layer 108 on the buffer layer 102.
S8) forming a first via 1081 and a second via 1082 on the planarization layer 108, wherein the first via 1081 penetrates through the planarization layer 108 and a portion of the interlayer insulating layer 107 to the surface of the semiconductor layer 104, and the second via 1082 penetrates through the planarization layer 108 and a portion of the interlayer insulating layer 107 to the surface of the semiconductor layer 104.
S9) as shown in fig. 3, a transparent electrode film 109 and a second metal layer 110 (copper) are sequentially deposited on the planarization layer 108.
In the step of sequentially depositing a transparent electrode film 109 and a second metal layer 110 on the planarization layer 108, the method further includes:
a transparent electrode film 109 and a second metal layer 110 are sequentially deposited in the first via 1081 and the second via 1082.
Generally, the transparent electrode film layer 109 is below, and the second metal layer 110 is above the transparent electrode film layer 109.
S10) as shown in fig. 4, patterning the transparent electrode film 109 and the second metal layer 110 by a photolithography process to form a source/drain metal layer 116, a trench 114, and a first electrode 115, as shown in fig. 8 and 9. Wherein, in the first via 1081 and the second via 1082, the second metal layer 110 is connected to the semiconductor layer 104 through the first electrode 115.
In the step of forming the source/drain metal layer 116, the channel 114, and the first electrode 115 by patterning the transparent electrode film 109 and the second metal layer 110 through a yellow light process, the method specifically includes:
s101) provides a halftone mask 200 as shown in fig. 4. The half-tone mask plate 200 includes: a full via 201, a semi-transmissive region 202, and an opaque region 203. The full through hole 201 can allow all ultraviolet rays to pass through, and photoresist corresponding to the full through hole 201 area can be completely eliminated through display liquid; the photoresist corresponding to the semi-transparent region 202 is not completely removed.
S102) coating a photoresist 111 on the second metal layer 110, wherein the photoresist 111 is a negative photoresist.
S103) arranging the halftone mask plate 200 above the photoresist 111.
S104) as shown in fig. 5, irradiating the photoresist 111 with ultraviolet light through the halftone mask 200, and performing exposure and development to obtain a source/drain pattern 113 and a first electrode pattern 112, where the first electrode pattern 112 corresponds to the semi-transmissive region 202, and the source/drain pattern 113 corresponds to the opaque region 203.
The source and drain patterns 113 and the first electrode patterns 112 are made of photoresist, and due to the characteristics of the halftone mask 200, light is not completely transmitted through holes and is not eliminated by a developing solution.
S105) as shown in fig. 6, etching away the second metal layer 110 and the transparent electrode film 109 corresponding to the full via 201 to form a channel 114 and a first electrode 115.
S106) ashing the first electrode pattern 112 as shown in fig. 7.
S107) as shown in fig. 8, etching away the second metal layer 110 corresponding to the first electrode pattern 112 to expose the first electrode 115, and removing the source/drain pattern 113 to form a source/drain metal layer 116.
The source/drain metal layer 116 includes a source trace and a drain trace, which are respectively disposed in the first via 1081 and the second via 1082. Is connected to the semiconductor layer 104 through a portion of the first electrode 115.
S11) depositing a pixel defining layer 117 on the source drain metal layer 116, the planarization layer 108, the channel 114, and the first electrode 115.
S12) as shown in fig. 10, forming a trench 118 on the pixel defining layer 117, wherein the trench 118 is recessed to the surface of the first electrode 115. As shown in fig. 11, the OLED functional device 120 is finally deposited in the trench 118 to form a display panel.
The invention provides a preparation method of a display panel, in particular to a preparation method of a bottom-emitting white light OLED display panel. The transparent electrode film 109 and the second metal layer 110 are patterned by a photolithography process to form a source/drain metal layer 116, a channel 114, and a first electrode 115. Specifically, the transparent electrode film layer 109 and the second Metal layer 110 are deposited together as a new Metal layer (Metal2) on the planarization layer 108, and the transparent electrode film layer 109 and the second Metal layer 110 are patterned by utilizing the light transmittance of the half-tone mask 200. The number of mask plates is reduced, so that the cost in preparation is reduced, and the preparation efficiency is improved.
The invention also provides a display panel which is prepared by the preparation method of the display panel.
As shown in fig. 11, the display panel includes: the organic light emitting diode display device comprises a substrate 101, a light shielding layer 103, a buffer layer 102, a semiconductor layer 104, a gate layer 105, a first metal layer 106, an interlayer insulating layer 107, a planarization layer 108, a first electrode 115, a source-drain electrode layer 116, a pixel defining layer 117, and an OLED functional device 120.
The light-shielding layer 103 is disposed on the substrate 101 and corresponds to the semiconductor layer 104. The buffer layer 102 is disposed on the substrate 101 and covers the light-shielding layer 103.
The semiconductor layer 104 is disposed on the buffer layer 102; the gate layer 105 is disposed on the semiconductor layer 104.
The first metal layer 106 is disposed on the gate layer 105; the interlayer insulating layer 107 is disposed on the buffer layer 102, the semiconductor layer 104, and the first metal layer 106.
The planarization layer 108 is provided on the interlayer insulating layer 107; the planarization layer 108 has a first via 1081 and a second via 1082. the first via 1081 penetrates through the planarization layer 108 and a portion of the interlayer insulating layer 107 to the surface of the semiconductor layer 104, and the second via 1082 penetrates through the planarization layer 108 and a portion of the interlayer insulating layer 107 to the surface of the semiconductor layer 104.
The planarization layer 108 is further provided with an RGB color filter 119 for light emitting display.
The first electrode 115 is disposed on the planarization layer 108 and on the hole walls of the first via 1081 and the second via 1082, respectively.
The source/drain electrode layer 116 is disposed on the first electrode 115 and fills the first via 1081 and the second via 1082 to be planarized.
The pixel defining layer 117 is disposed on the source/drain metal layer 116, the planarization layer 108, the channel 114, and the first electrode 115; the pixel defining layer 117 has a trench 118, and the trench 118 is recessed to the surface of the first electrode 115. The OLED functional device 120 is disposed in the slot 118.
The invention also provides a display panel prepared by the preparation method of the display panel, in particular to a bottom-emitting white light OLED display panel. The transparent electrode film 109 and the second metal layer 110 are patterned by a photolithography process to form a source/drain metal layer 116, a channel 114, and a first electrode 115. Specifically, the transparent electrode film layer 109 and the second Metal layer 110 (as a new Metal2) are deposited together on the planarization layer 108, and the transparent electrode film layer 109 and the second Metal layer 110 are patterned by utilizing the light transmittance of the half-tone mask 200. The number of the mask plates is reduced, and the cost in preparation is reduced.
Although the structure of the display panel prepared by the invention is obviously changed, the positions of the first electrode 115 and the source-drain metal layer 116 are directly contacted, the source-drain metal layer 116 is connected with the semiconductor layer 104 through the first electrode 115 arranged in the first through hole 1081 and the second through hole 1082, and the first electrode 115 is connected with the source-drain metal layer 116, so that the effect of the electrical connection is the same. The invention further reduces the number of film layers and obviously improves the preparation efficiency.
It should be noted that many variations and modifications of the embodiments of the present invention fully described are possible and are not to be considered as limited to the specific examples of the above embodiments. The above examples are given by way of illustration of the invention and are not intended to limit the invention. In conclusion, the scope of the present invention should include those changes or substitutions and modifications which are obvious to those of ordinary skill in the art.
Claims (9)
1. A preparation method of a display panel is characterized by comprising the following steps:
providing a substrate;
depositing a buffer layer on the substrate;
depositing a semiconductor layer on the buffer layer;
depositing a gate layer on the semiconductor layer;
depositing a first metal layer on the gate layer;
depositing an interlayer insulating layer and a planarization layer on the buffer layer in sequence;
depositing a transparent electrode film layer and a second metal layer on the planarization layer; and patterning the transparent electrode film layer and the second metal layer by a yellow light process to form a source/drain metal layer, a channel and a first electrode.
2. The method according to claim 1, wherein the step of patterning the transparent electrode film layer and the second metal layer by a yellow light process to form a source/drain metal layer, a channel, and a first electrode includes:
providing a halftone mask, the halftone mask comprising: a full via and a semi-permeable region;
coating a photoresist on the second metal layer;
arranging the halftone mask plate above the photoresist;
irradiating the photoresist through the halftone mask plate by using ultraviolet light to perform exposure development to obtain source/drain electrode patterns and first electrode patterns, wherein the first electrode patterns correspond to the semi-transparent area;
etching the second metal layer and the transparent electrode film layer corresponding to the full through hole to form the channel;
ashing the first electrode pattern;
and etching the second metal layer corresponding to the first electrode pattern, and removing the source and drain electrode pattern to form the source and drain electrode metal layer.
3. The method for manufacturing a display panel according to claim 1, further comprising, after the step of sequentially depositing an interlayer insulating layer and a planarizing layer on the buffer layer:
and forming a first through hole and a second through hole on the planarization layer, wherein the first through hole penetrates through the planarization layer and part of the interlayer insulating layer to the surface of the semiconductor layer, and the second through hole penetrates through the planarization layer and part of the interlayer insulating layer to the surface of the semiconductor layer.
4. The method for manufacturing a display panel according to claim 1, wherein the step of sequentially depositing a transparent electrode film layer and a second metal layer on the planarization layer further comprises:
and sequentially depositing the transparent electrode film layer and the second metal layer in the first through hole and the second through hole.
5. The method for manufacturing a display panel according to claim 1, comprising, after the step of providing a substrate, a step of forming a passivation layer on the substrate
Depositing a light shielding layer on the substrate.
6. The method for manufacturing a display panel according to claim 1, further comprising:
depositing a pixel defining layer on the source drain metal layer, the planarization layer, the channel and the first electrode;
forming a slot on the pixel defining layer, wherein the slot is recessed to the surface of the first electrode.
7. A display panel, comprising:
a substrate;
the buffer layer is arranged on the substrate;
a semiconductor layer disposed on the buffer layer;
a gate layer disposed on the semiconductor layer;
the first metal layer is arranged on the grid layer;
an interlayer insulating layer disposed on the buffer layer, the semiconductor layer, and the first metal layer;
a planarization layer disposed on the interlayer insulating layer; the planarization layer is provided with a first through hole and a second through hole, the first through hole penetrates through the planarization layer and a part of the interlayer insulating layer to the surface of the semiconductor layer, and the second through hole penetrates through the planarization layer and a part of the interlayer insulating layer to the surface of the semiconductor layer;
a first electrode disposed on the planarization layer and in the first and second vias;
and the source and drain electrode layer is arranged on the first electrode.
8. The display panel according to claim 7, further comprising: a light-shielding layer disposed in the buffer layer and corresponding to the semiconductor layer;
and the RGB color resistors are arranged in the planarization layer.
9. The display panel according to claim 7, further comprising:
the pixel limiting layer is arranged on the source drain electrode metal layer, the planarization layer, the channel and the first electrode;
the pixel defining layer has a slot recessed to the first electrode surface.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020125477A1 (en) * | 2001-03-02 | 2002-09-12 | So Woo Young | Thin film transistors with dual layered source/drain electrodes and manufacturing method thereof, and active matrix display device and manufacturing method thereof |
| CN101577283A (en) * | 2008-05-06 | 2009-11-11 | 三星移动显示器株式会社 | Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof |
| CN109585506A (en) * | 2018-11-22 | 2019-04-05 | 武汉华星光电技术有限公司 | OLED with illumination functions shows equipment |
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- 2019-11-27 CN CN201911180213.6A patent/CN110993656A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020125477A1 (en) * | 2001-03-02 | 2002-09-12 | So Woo Young | Thin film transistors with dual layered source/drain electrodes and manufacturing method thereof, and active matrix display device and manufacturing method thereof |
| CN101577283A (en) * | 2008-05-06 | 2009-11-11 | 三星移动显示器株式会社 | Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof |
| CN109585506A (en) * | 2018-11-22 | 2019-04-05 | 武汉华星光电技术有限公司 | OLED with illumination functions shows equipment |
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Application publication date: 20200410 |