CN110971856B - Device and method for generating HD-SDI video and analog video based on low-speed SRAM - Google Patents
Device and method for generating HD-SDI video and analog video based on low-speed SRAM Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention provides a device and a method for generating HD-SDI video and analog video based on low-speed SRAM (static random access memory), wherein an infrared image data receiving unit is a data source end, an FPGA (field programmable gate array) is a core processor, the FPGA caches infrared image data received by the infrared image data receiving unit into an asynchronous dual-port SRAM (static random access memory), reads the infrared image data from the asynchronous dual-port SRAM for processing according to the time sequence requirements of an SDI video coding unit and an analog video coding unit, and a power supply unit provides required voltage for the whole device for generating HD-SDI video and analog video based on the low-speed SRAM. The invention generates HD-SDI video and analog video on the basis of not changing the original image processing platform, realizes high-definition high-speed video by adopting low-speed SRAM, inherits mature technology to the maximum extent, and meets the requirements of engineering application.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to a device for generating a video and an implementation method.
Background
In the field of thermal infrared imagers, an infrared image video output by the thermal infrared imager needs to be transmitted to a rear-end image processing device for feature information extraction. In the currently adopted video transmission mode, the SDI has the advantages of few transmission cables, easy use, high definition, small time delay, and the like, and can also repeatedly use the analog video cable with the network, and is gradually and widely adopted.
An FPGA image processing platform based on a DDR (double data rate synchronous dynamic random access memory) is already used for realizing an HD-SDI (high definition SDI) video, but in engineering application, some original thermal infrared imagers adopting an FPGA image processing platform based on a low-speed SRAM hope to realize the HD-SDI video on the basis of not changing the original image processing platform.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a device for generating an HD-SDI video and an analog video based on a low-speed SRAM and an implementation method thereof. The invention generates HD-SDI video and analog video on the basis of the original FPGA image processing platform based on the low-speed SRAM.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a device for generating HD-SDI video and analog video based on low-speed SRAM comprises an infrared image data receiving unit, an FPGA, an asynchronous dual-port SRAM, an SDI video coding unit, an analog video coding unit and a power supply unit;
the infrared image data receiving unit is a data source end, the FPGA is a core processor, the FPGA caches the infrared image data received by the infrared image data receiving unit into the asynchronous dual-port SRAM, the infrared image data are read from the asynchronous dual-port SRAM for processing according to the time sequence requirements of the SDI video coding unit and the analog video coding unit, and the power supply unit provides required voltage for the whole device for generating the HD-SDI video and the analog video based on the low-speed SRAM.
The infrared image data receiving unit realizes photoelectric signal conversion and converts an infrared radiation signal of a target background into an electric signal.
The FPGA realizes time sequence management and signal processing.
The asynchronous dual-port SRAM is used as a display memory and stores infrared image data with 640 x 512 resolution.
The SDI video coding unit realizes HD-SDI video coding output.
The analog video coding unit realizes analog video coding output.
A method of an apparatus for generating HD-SDI video and analog video based on low speed SRAM comprises the following steps:
step 1: according to the requirement of an HD-SDI video format in an SDI video coding chip, the FPGA generates various control signals;
step 2: the infrared image data clock frequency output by the infrared image data receiving unit is clk, at the time of 2000 × clk before the rising edge of the effective signal of the HD-SDI video data, the FPGA sequentially reads the infrared image data of the first 2 lines (640 × 2 resolution) in the asynchronous dual-port SRAM, and the FPGA performs double-time interpolation amplification at the rate 4 times of clk and writes the infrared image data into an on-chip FIFO;
and step 3: when the HD-SDI video line data are effective, the FPGA reads 1024 data in the FIFO on the chip according to the HD-SDI video clock rate and outputs the data to the SDI video coding unit;
and 4, step 4: when the number of data in the on-chip FIFO is less than 200, the FPGA continues to sequentially read the next row (640 resolution) of infrared image data in the asynchronous dual-port SRAM at the clk rate, and the FPGA performs twice interpolation amplification at 4 times the clk rate and writes the amplified data into the on-chip FIFO;
and 5: and (4) repeating the steps 3 and 4 until the data in the asynchronous dual-port SRAM is completely read.
A method of an apparatus for generating HD-SDI video and analog video based on low speed SRAM, the steps of generating analog video are as follows:
step 1: according to the requirement of an analog video format, the FPGA generates various control signals;
step 2: at the time 2000 × clk before the analog video blanking signal is effective, the FPGA reads infrared image data of the 1 st line and the 3 rd line (640 × 2 resolution) in the asynchronous dual-port SRAM at the clk rate and writes the infrared image data into an on-chip FIFO;
and step 3: when the analog video line data is effective, the FPGA reads 640 data in the FIFO on the chip according to the analog video clock rate and outputs the data to the analog video coding unit;
and 4, step 4: when the number of data in the on-chip FIFO is less than 200, the FPGA continuously reads 640 infrared image data in the asynchronous dual-port SRAM in a clk interlaced mode and writes the infrared image data into the on-chip FIFO;
and 5: repeating the steps 3 and 4 until 640 th 512 th data in the asynchronous dual-port SRAM is read;
step 6: when the number of data in the on-chip FIFO is less than 200, the FPGA continues to read the infrared image data of the 2 nd line (640 resolution) in the asynchronous dual-port SRAM at the clk rate and writes the infrared image data into the on-chip FIFO;
and 7: and repeating the steps 3 and 4 until 640 × 511 th data in the asynchronous dual-port SRAM is read.
The invention has the advantages that the HD-SDI video and the analog video are generated on the basis of not changing the original image processing platform, the high-definition high-speed video is realized by adopting the low-speed SRAM, the mature technology is inherited to the greatest extent, and the engineering application requirements are met.
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Fig. 1 is a schematic structural diagram of an apparatus for generating HD-SDI video and analog video based on low-speed SRAM according to the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 1, an apparatus for generating HD-SDI video and analog video based on low speed SRAM includes an infrared image data receiving unit, an FPGA, an asynchronous dual port SRAM, an SDI video encoding unit, an analog video encoding unit, and a power supply unit;
the infrared image data receiving unit is a data source end, the FPGA is a core processor, the FPGA caches the infrared image data received by the infrared image data receiving unit into an asynchronous dual-port SRAM, and reads the infrared image data from the asynchronous dual-port SRAM for processing according to the time sequence requirements of an SDI video coding unit and an analog video coding unit, and a power supply unit provides required voltage for the whole device for generating HD-SDI video and analog video based on the low-speed SRAM;
the infrared image data receiving unit realizes photoelectric signal conversion and converts an infrared radiation signal of a target background into an electric signal;
the FPGA realizes time sequence management and signal processing;
the asynchronous dual-port SRAM is used as a display memory and stores infrared image data with 640 x 512 resolution;
the SDI video coding unit realizes HD-SDI video coding output;
the analog video coding unit realizes analog video coding output;
the power supply unit realizes power supply of the image processing platform;
the device and the method for generating the HD-SDI video and the analog video based on the low-speed SRAM are characterized in that the HD-SDI video is generated by adopting the following steps:
step 1: according to the requirement of an HD-SDI video format in an SDI video coding chip, the FPGA generates various control signals;
step 2: the infrared image data clock frequency output by the infrared image data receiving unit is clk, at the time of 2000 × clk before the rising edge of the effective signal of the HD-SDI video data, the FPGA sequentially reads the infrared image data of the first 2 lines (640 × 2 resolution) in the asynchronous dual-port SRAM, and the FPGA performs double-time interpolation amplification at the rate 4 times of clk and writes the infrared image data into an on-chip FIFO;
and step 3: when the HD-SDI video line data are effective, the FPGA reads 1024 data in the FIFO on the chip according to the HD-SDI video clock rate and outputs the data to the SDI video coding unit;
and 4, step 4: when the number of data in the on-chip FIFO is less than 200, the FPGA continues to sequentially read the next row (640 resolution) of infrared image data in the asynchronous dual-port SRAM at the clk rate, and the FPGA performs twice interpolation amplification at 4 times the clk rate and writes the amplified data into the on-chip FIFO;
and 5: repeating the steps 3) and 4) until the data in the asynchronous dual-port SRAM is completely read;
a device and a method for generating HD-SDI video and analog video based on low-speed SRAM are characterized in that the analog video generation adopts the following steps:
step 1: according to the requirement of an analog video format, the FPGA generates various control signals;
step 2: at the time 2000 × clk before the analog video blanking signal is effective, the FPGA reads infrared image data of the 1 st line and the 3 rd line (640 × 2 resolution) in the asynchronous dual-port SRAM at the clk rate and writes the infrared image data into an on-chip FIFO;
and step 3: when the analog video line data is effective, the FPGA reads 640 data in the FIFO on the chip according to the analog video clock rate and outputs the data to the analog video coding unit;
and 4, step 4: when the number of data in the on-chip FIFO is less than 200, the FPGA continuously reads 640 infrared image data in the asynchronous dual-port SRAM in a clk interlaced mode and writes the infrared image data into the on-chip FIFO;
and 5: repeating the steps 3) and 4) until 640 th 512 th data in the asynchronous dual-port SRAM is read;
step 6: when the number of data in the on-chip FIFO is less than 200, the FPGA continues to read the infrared image data of the 2 nd line (640 resolution) in the asynchronous dual-port SRAM at the clk rate and writes the infrared image data into the on-chip FIFO;
and 7: and repeating the steps 3) and 4) until 640 × 511 th data in the asynchronous dual-port SRAM is read.
In this embodiment, the FPGA employs EP3C120F780I7 to implement data preprocessing, generate HD-SDI video control signals of 1920 × 1080p @25 standard (with an effective resolution of 1280 × 1024) and analog video control signals of PAL standard, read infrared image data in the asynchronous dual-port SRAM at a rate of 22MHz according to timing requirements, and interpolate 640 × 512 infrared image data to 1280 × 1024 at a rate of 88 MHz.
The asynchronous dual-port SRAM adopts IDT70T633S12BCI, and stores 640 x 512-resolution infrared image data.
And the SDI video coding unit adopts an SDI video coding chip GV7600 to code HD-SDI video data output by the FPGA, and the clock frequency is 148.5 MHz.
The analog video coding unit adopts an analog video coding chip ADV7123 to code analog video data output by the FPGA, and the clock frequency is 13.5 MHz.
Claims (2)
1. The device for generating the HD-SDI video and the analog video based on the low-speed SRAM comprises an infrared image data receiving unit, an FPGA, an asynchronous dual-port SRAM, an SDI video coding unit, an analog video coding unit and a power supply unit; the infrared image data receiving unit is a data source end, the FPGA is a core processor, the FPGA caches the infrared image data received by the infrared image data receiving unit into an asynchronous dual-port SRAM, and reads the infrared image data from the asynchronous dual-port SRAM for processing according to the time sequence requirements of an SDI video coding unit and an analog video coding unit, and a power supply unit provides required voltage for the whole device for generating HD-SDI video and analog video based on the low-speed SRAM; the infrared image data receiving unit realizes photoelectric signal conversion and converts an infrared radiation signal of a target background into an electric signal; the FPGA realizes time sequence management and signal processing; the asynchronous dual-port SRAM is used as a display memory and stores infrared image data with 640 x 512 resolution; the SDI video coding unit realizes HD-SDI video coding output; the analog video coding unit realizes analog video coding output; the method is characterized in that:
the device for generating the HD-SDI video and the analog video based on the low-speed SRAM comprises the following steps of:
step 1: according to the requirement of an HD-SDI video format in an SDI video coding chip, the FPGA generates various control signals;
step 2: the clock frequency of infrared image data output by the infrared image data receiving unit is clk, at the time of 2000 × clk before the rising edge of an effective signal of HD-SDI video data, the FPGA sequentially reads the first 2 lines of infrared image data in the asynchronous dual-port SRAM, and the FPGA performs double-time interpolation amplification at the rate of 4 times clk and writes the data into an on-chip FIFO;
and step 3: when the HD-SDI video line data are effective, the FPGA reads 1024 data in the FIFO on the chip according to the HD-SDI video clock rate and outputs the data to the SDI video coding unit;
and 4, step 4: when the number of data in the on-chip FIFO is less than 200, the FPGA continues to sequentially read the next line of infrared image data in the asynchronous dual-port SRAM at the clk rate, and the FPGA performs twice interpolation amplification at 4 times the clk rate and writes the amplified data into the on-chip FIFO;
and 5: and (4) repeating the steps 3 and 4 until the data in the asynchronous dual-port SRAM is completely read.
2. The device for generating the HD-SDI video and the analog video based on the low-speed SRAM comprises an infrared image data receiving unit, an FPGA, an asynchronous dual-port SRAM, an SDI video coding unit, an analog video coding unit and a power supply unit; the infrared image data receiving unit is a data source end, the FPGA is a core processor, the FPGA caches the infrared image data received by the infrared image data receiving unit into an asynchronous dual-port SRAM, and reads the infrared image data from the asynchronous dual-port SRAM for processing according to the time sequence requirements of an SDI video coding unit and an analog video coding unit, and a power supply unit provides required voltage for the whole device for generating HD-SDI video and analog video based on the low-speed SRAM; the infrared image data receiving unit realizes photoelectric signal conversion and converts an infrared radiation signal of a target background into an electric signal; the FPGA realizes time sequence management and signal processing; the asynchronous dual-port SRAM is used as a display memory and stores infrared image data with 640 x 512 resolution; the SDI video coding unit realizes HD-SDI video coding output; the analog video coding unit realizes analog video coding output; the method is characterized in that:
the device for generating the HD-SDI video and the analog video based on the low-speed SRAM comprises the following steps of:
step 1: according to the requirement of an analog video format, the FPGA generates various control signals;
step 2: at the moment 2000 × clk before the analog video blanking signal is effective, reading infrared image data of the 1 st line and the 3 rd line in the asynchronous dual-port SRAM by the FPGA at a clk rate, and writing the infrared image data into an on-chip FIFO;
and step 3: when the analog video line data is effective, the FPGA reads 640 data in the FIFO on the chip according to the analog video clock rate and outputs the data to the analog video coding unit;
and 4, step 4: when the number of data in the on-chip FIFO is less than 200, the FPGA continuously reads 640 infrared image data in the asynchronous dual-port SRAM in a clk interlaced mode and writes the infrared image data into the on-chip FIFO;
and 5: repeating the steps 3 and 4 until 640 th 512 th data in the asynchronous dual-port SRAM is read;
step 6: when the number of data in the on-chip FIFO is less than 200, the FPGA continues to read the infrared image data of the 2 nd line in the asynchronous dual-port SRAM at the clk rate and writes the infrared image data into the on-chip FIFO;
and 7: and repeating the steps 3 and 4 until 640 × 511 th data in the asynchronous dual-port SRAM is read.
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