CN110971552A - DPSK demodulation circuit - Google Patents
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- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
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Abstract
The invention belongs to the field of electricity, and relates to a DPSK demodulation circuit which comprises a modulation signal input end, a carrier extraction circuit, a carrier removal circuit, a sampling decision circuit, a signal locking circuit, a NAND gate and a demodulation signal output end; the carrier extraction circuit is connected with the NAND gate through the carrier removal circuit and the sampling decision circuit; the carrier extraction circuit is connected with the NAND gate through the signal locking circuit; the modulation signal input end is respectively connected with the carrier extraction circuit, the carrier removal circuit, the sampling decision circuit and the signal locking circuit; the output end of the NAND gate is connected with the output end of the modulating signal. The invention provides a DPSK demodulation circuit which can correctly demodulate an input DPSK signal, has stable function and low cost and can effectively solve the carrier phase ambiguity.
Description
Technical Field
The invention belongs to the field of electricity, relates to a demodulation circuit, and particularly relates to a DPSK demodulation circuit.
Background
Modem is an important means of achieving modern communications. In order for a digital signal to be transmitted in a band pass channel, a carrier wave must be modulated with the digital baseband signal to match the signal to the channel characteristics. Therefore, the method has important significance in researching the digital communication modulation and demodulation theory and providing an effective modulation mode. A high transmission rate and a low error rate are necessary to ensure efficient transmission of information in a transmission system. Differential phase shift keying (DPSK for short) is the most common modulation scheme in data communication, and has the advantages of simplicity and easy implementation. And due to the unique modulation mode, the phenomenon of 'falling pi' in the PSK modulation is avoided. Demodulation is the inverse of modulation, and is particularly important in order to extract the signal from the carrier as undistorted as possible. There are two commonly used DPSK demodulation methods, i.e., differential coherent demodulation and coherent demodulation. In a transmission signal, a 2PSK signal has a better error rate performance than 2ASK and 2FSK signals, but there is phase uncertainty in a 2PSK signal transmission system and it will cause the received symbols "0" and "1" to be reversed, resulting in an error. In order to ensure the advantages of 2PSK and not generate bit errors, the 2PSK system is improved into binary differential phase shift keying (2 DPSK). The DPSK demodulation method includes two differential coherent demodulation methods and a coherent demodulation method. The coherent demodulation method is mainly to multiply the original signal and the carrier wave, remove the carrier wave and process the signal. Differential coherent demodulation needs to delay one path of signal, but sometimes some hardware circuits cannot accurately delay one bit of code element, which may cause errors. And the DPSK signal is demodulated by directly utilizing software such as an FPGA (field programmable gate array) and the like, but when the DPSK signal is applied to a circuit, the DPSK signal is required to correspond to a front system and a rear system, and the conversion is complex.
Disclosure of Invention
In order to solve the above technical problems in the background art, the present invention provides a DPSK demodulation circuit that can correctly demodulate an input DPSK signal, has stable functions and low cost, and can effectively solve carrier phase ambiguity.
In order to achieve the purpose, the invention adopts the following technical scheme:
a DPSK demodulation circuit, characterized in that: the DPSK demodulation circuit comprises an original carrier input end, a carrier extraction circuit, a carrier removal circuit, a sampling decision circuit, a signal locking circuit, a NAND gate and a demodulation signal output end; the carrier extraction circuit is connected with the NAND gate through the carrier removal circuit and the sampling decision circuit; the carrier extraction circuit is connected with the NAND gate through the signal locking circuit; the modulation signal input end is respectively connected with the carrier extraction circuit, the carrier removal circuit, the sampling judgment circuit and the signal locking circuit; the output end of the NAND gate is connected with the output end of the modulation signal.
The carrier extraction circuit comprises a logic phase-locked loop circuit, a first D trigger, a second D trigger and a carrier output end; one end of the first D trigger and one end of the second D trigger after forming the frequency divider are connected with the logic phase-locked loop circuit, and the other end of the first D trigger and the second D trigger are connected with the carrier output end; the input end of the modulation signal is connected with a logic phase-locked loop circuit; and the carrier output end is respectively connected with the carrier removing circuit and the signal locking circuit.
The logic phase-locked loop circuit comprises a chip U1, a first resistor R1, a second resistor R2, a sixth resistor R6, a seventh resistor R7, a first capacitor C1 and a fifth capacitor C5; the chip U1 is grounded after passing through a first resistor R1, a second resistor R2 and a first capacitor C1 in sequence; the chip U1 is grounded through a second resistor R2 and a first capacitor C1; the chip U1 is grounded through a sixth resistor R6 and a seventh resistor R7 respectively; the chip U1 is fed back to the chip U1 through a fifth capacitor C5; the modulation signal input end is connected with the first D trigger and the second D trigger respectively after passing through the chip U1.
The model of the chip U1 is CD74HC 4046; the model of each of the first D trigger and the second D trigger is 74HC 74.
The carrier removal circuit is a first logic gate; the carrier extraction circuit and the modulation signal input end are respectively connected to a first logic gate; the output end of the first logic gate is connected to a sampling decision circuit, and the model of the first logic gate is 74HC 86.
The sampling decision circuit comprises a first comparator, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3 and a tenth resistor R10; the modulation signal input end is connected with the first comparator and the second capacitor C2 respectively after passing through a third resistor R3; the carrier wave removing circuit is connected with the first comparator and the third capacitor C3 through a fourth resistor R4; the second capacitor C2 and the third capacitor C3 are respectively grounded; the first comparator is respectively connected with the NAND gate and the tenth resistor R10.
The first comparator is a four-way differential comparator, and the model of the first comparator is LM 339.
The resistance of the third resistor R3 is 10K Ω; the resistance value of the fourth resistor R4 is 82K omega; the resistance value of the tenth resistor R10 is 6K Ω; the capacitance value of the second capacitor C2 is 0.1 μ F; the capacitance value of the third capacitor C3 is 100 μ F.
The signal locking circuit comprises a second logic gate, an eighth resistor R8, a fourth capacitor C4, a fifth resistor R5, a ninth resistor R9, a second comparator and an eleventh resistor R11; the modulation signal input end and the carrier extraction circuit are respectively connected with an eighth resistor R8 through a second logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the second comparator; the power supply input end of the second comparator is connected to the positive input end of the second comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the second comparator; the output end of the second comparator is respectively connected with the eleventh resistor R11 and the second logic gate.
The second comparator is a four-way differential comparator, and the model of the second comparator is LM 339; the model of the second logic gate is 74HC 86; the resistance value of the eighth resistor R8 is 90K omega; the resistance value of the ninth resistor R9 is 21K omega; the resistance value of the fifth resistor R5 is 30K omega; the resistance value of the eleventh resistor R11 is 6K omega; the capacitance value of the fourth capacitor C4 is 1000 pF; the model of the NAND gate is 74HC 0D.
The invention has the advantages that:
the invention provides a DPSK demodulation circuit, which comprises a modulation signal input end, a carrier extraction circuit, a carrier removal circuit, a sampling decision circuit, a signal locking circuit, a NAND gate and a demodulation signal output end, wherein the modulation signal input end is connected with the carrier extraction circuit; the carrier extraction circuit is connected with the NAND gate through the carrier removal circuit and the sampling decision circuit; the carrier extraction circuit is connected with the NAND gate through the signal locking circuit; the modulation signal input end is respectively connected with the carrier extraction circuit, the carrier removal circuit, the sampling decision circuit and the signal locking circuit; the output end of the NAND gate is connected with the output end of the modulating signal. The DPSK hardware demodulation circuit provided by the invention correctly demodulates the input DPSK signal, and sets a locking indication state, and when no data is input, the locking indication is at a low level. Can be used as a direct indication number to be given to the system to save the judgment time of the system on the data. Compared with the differential coherent demodulation, the delay unit is omitted, and errors possibly caused by delay are avoided. Compared with a software control circuit, the digital signal processing circuit does not need software control, reduces serial ports and is directly applied to a modulation circuit of a certain fixed carrier. The invention provides a DPSK digital demodulation circuit with locking indication, which can be applied to lower carrier frequency and can successfully and correctly demodulate an input modulation signal.
Drawings
FIG. 1 is a schematic diagram of a DPSK demodulation circuit principle framework provided by the invention;
FIG. 2 is a schematic diagram of a carrier extraction circuit employed in the present invention;
FIG. 3 is a schematic diagram of a carrier removal circuit employed in the present invention;
FIG. 4 is a schematic diagram of a sampling decision circuit employed in the present invention;
fig. 5 is a schematic diagram of a signal locking circuit employed in the present invention.
Detailed Description
Referring to fig. 1, the present invention provides a DPSK demodulation circuit, characterized in that: the DPSK demodulation circuit comprises a modulation signal input end, a carrier extraction circuit, a carrier removal circuit, a sampling decision circuit, a signal locking circuit, a NAND gate and a demodulation signal output end; the carrier extraction circuit is connected with the NAND gate through the carrier removal circuit and the sampling decision circuit; the carrier extraction circuit is connected with the NAND gate through the signal locking circuit; the modulation signal input end is respectively connected with the carrier extraction circuit, the carrier removal circuit, the sampling decision circuit and the signal locking circuit; the output end of the NAND gate is connected with the output end of the modulating signal.
Referring to fig. 2, the carrier extraction circuit adopted in the present invention includes a logic phase-locked loop circuit, a first D flip-flop, a second D flip-flop, and a carrier output end; one end of the first D trigger and one end of the second D trigger after being connected in parallel are connected with the logic phase-locked loop circuit, and the other end of the first D trigger and the second D trigger are connected with the carrier output end; the input end of the modulation signal is connected with a logic phase-locked loop circuit; the carrier output end is respectively connected with the carrier removing circuit and the signal locking circuit.
The logic phase-locked loop circuit comprises a chip U1, a first resistor R1, a second resistor R2, a sixth resistor R6, a seventh resistor R7, a first capacitor C1 and a fifth capacitor C5; the chip U1 is grounded after passing through the first resistor R1, the second resistor R2 and the first capacitor C1 in sequence; the chip U1 is grounded through the second resistor R2 and the first capacitor C1; the chip U1 is grounded through a sixth resistor R6 and a seventh resistor R7 respectively; the chip U1 is fed back to the chip U1 through the fifth capacitor C5; the modulation signal input end is respectively connected with the first D trigger and the second D trigger after passing through the chip U1. The model of the chip U1 is CD74HC 4046; the first D flip-flop and the second D flip-flop are both 74HC74 in model number.
Referring to fig. 3, the carrier removal circuit employed in the present invention is a first logic gate; the carrier extraction circuit and the modulation signal input end are respectively connected to the first logic gate; the output end of the first logic gate is connected to the sampling decision circuit, and the model of the first logic gate is 74HC 86.
Referring to fig. 4, the sampling decision circuit employed in the present invention includes a first comparator, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, and a tenth resistor R10; the modulation signal input end is respectively connected with the first comparator and the second capacitor C2 after passing through a third resistor R3; the carrier wave removing circuit is connected with the first comparator and the third capacitor C3 respectively after passing through a fourth resistor R4; the second capacitor C2 and the third capacitor C3 are grounded respectively; the first comparator is connected to the nand gate and the tenth resistor R10, respectively. The first comparator is a four-way differential comparator, and the model of the first comparator is LM 339. The resistance of the third resistor R3 is 10K Ω; the resistance of the fourth resistor R4 is 82K Ω; the resistance of the tenth resistor R10 is 6K Ω; the capacitance value of the second capacitor C2 is 0.1 μ F; the capacitance value of the third capacitor C3 is 100 muf.
Referring to fig. 5, the signal locking circuit adopted in the present invention includes a second logic gate, an eighth resistor R8, a fourth capacitor C4, a fifth resistor R5, a ninth resistor R9, a second comparator, and an eleventh resistor R11; the modulation signal input end and the carrier extraction circuit are respectively connected with an eighth resistor R8 through a second logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the second comparator; the power supply input end of the second comparator is connected to the positive input end of the second comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the second comparator; the output end of the second comparator is respectively connected with the eleventh resistor R11 and the second logic gate.
10. A DPSK demodulation circuit according to claim 9, characterized in that: the second comparator is a four-way differential comparator, and the model of the second comparator is LM 339; the second logic gate is model 74HC 86; the resistance of the eighth resistor R8 is 90K Ω; the resistance of the ninth resistor R9 is 21K Ω; the resistance of the fifth resistor R5 is 30K Ω; the resistance of the eleventh resistor R11 is 6K Ω; the capacitance value of the fourth capacitor C4 is 1000 pF; the model of the nand gate is 74HC 0D.
The DPSK hardware demodulation circuit provided by the invention correctly demodulates the input DPSK signal, and sets a locking indication state, and when no data is input, the locking indication is at a low level. Can be used as a direct indication number to be given to the system to save the judgment time of the system on the data. Compared with the differential coherent demodulation, the delay unit is omitted, and errors possibly caused by delay are avoided. Compared with a software control circuit, the digital signal processing circuit does not need software control, reduces serial ports and is directly applied to a modulation circuit of a certain fixed carrier. The invention mainly adopts a coherent demodulation method. Therefore, firstly, the modulated DPSK signal passes through a carrier extraction circuit to extract the same-frequency carrier, and a logic phase-locked loop is used for manufacturing a frequency follower, so that the carrier with the same frequency as the original carrier can be extracted. And multiplying the extracted carrier wave by the original modulation signal, and only leaving the signal after removing the carrier wave. The carrier is removed by mainly utilizing a logic gate to achieve the multiplication effect.
Through the above two steps, the obtained signal is not a complete signal, and here, a comparator is used for sampling judgment to judge the true signal. The demodulated signal is not successful, and when the power supply is repeatedly turned off and on, the two signals are found to be in phase sometimes and in phase opposition sometimes. This is known as coherent carrier phase ambiguity. This phenomenon occurs because the loop input signal is not a pure sinusoidal signal. The frequency of the loop input signal is equal to 2 times the carrier frequency of 2DPSK, i.e. equal to 2 times the carrier signal frequency of the modulation unit. The VCO signal frequency is equal to twice the carrier output signal frequency when the loop is locked. Therefore, when the loop is in a locked state, the carrier output frequencies of the modulation unit and the carrier synchronization unit are completely equal. And when the loop is locked, Ud is not a pure dc signal, and a small ac signal is superimposed on the dc level. In order to overcome the phenomenon, firstly, coherent demodulation is carried out on the 2DPSK signal to recover a relative code, and then the relative code is converted into an absolute code through an inverse code converter, so that the transmitted binary digital information is recovered. In the demodulation process, the coherent carrier generates 180-phase ambiguity, the demodulated relative code generates an inversion phenomenon, but after code inverse transformation, the output absolute code does not generate any inversion phenomenon, so that the problem of carrier phase ambiguity is solved. The present invention also has a lock signal that is low when no signal is input.
The key points of the technology of the invention are as follows: 1) and (3) synchronous carrier extraction: the invention fully considers that the demodulation is mainly to remove the carrier wave and extract the transmission signal, therefore, when adopting the coherent demodulation method, the extraction of the carrier wave is very important, and the extracted carrier wave and the original carrier wave have the same frequency and phase, and the carrier wave can be completely removed at the later stage. Therefore, when the carrier is extracted by using the phase-locked loop, the carrier of the input signal must be ensured to be in phase with the extracted same frequency. 2) And (3) sampling judgment: and the signal after carrier cancellation and the synchronous pulse signal enter a comparator for sampling judgment through a low-pass filter to obtain a differential code of the baseband signal.
The invention is a matched module digital system, and the last step of code inverse transformation is not carried out. Coherent demodulation methods mainly lie in how to obtain carriers with same frequency and phase. Since the DPSK signal is a double sideband signal suppressing the carrier, there is no carrier frequency component, and thus the local carrier cannot be directly extracted from the modulated signal by filtering. The design adopts a logic phase-locked loop CD74HC4046 and a double D trigger to extract a 400KHz carrier. And multiplying the extracted 400KHz carrier wave with the input 400KHz signal to offset the carrier wave. And the signal after carrier cancellation and the synchronous pulse signal enter a comparator for sampling judgment through a low-pass filter to obtain a differential code of the baseband signal.
In the invention, a path of locking signal is added, namely when no data is input, the locking signal is at low level and has no demodulation data; when data is input, the locking signal is at high level, and a demodulation signal is output.
Claims (10)
1. A DPSK demodulation circuit, characterized in that: the DPSK demodulation circuit comprises a modulation signal input end, a carrier extraction circuit, a carrier removal circuit, a sampling decision circuit, a signal locking circuit, a NAND gate and a demodulation signal output end; the carrier extraction circuit is connected with the NAND gate through the carrier removal circuit and the sampling decision circuit; the carrier extraction circuit is connected with the NAND gate through the signal locking circuit; the modulation signal input end is respectively connected with the carrier extraction circuit, the carrier removal circuit, the sampling judgment circuit and the signal locking circuit; the output end of the NAND gate is connected with the output end of the modulation signal.
2. The DPSK demodulation circuit of claim 1, wherein: the carrier extraction circuit comprises a logic phase-locked loop circuit, a first D trigger, a second D trigger and a carrier output end; one end of the first D trigger and one end of the second D trigger after being connected in parallel are connected with the logic phase-locked loop circuit, and the other end of the first D trigger and the second D trigger are connected with the carrier output end; the input end of the modulation signal is connected with a logic phase-locked loop circuit; and the carrier output end is respectively connected with the carrier removing circuit and the signal locking circuit.
3. The DPSK demodulation circuit of claim 2, wherein: the logic phase-locked loop circuit comprises a chip U1, a first resistor R1, a second resistor R2, a sixth resistor R6, a seventh resistor R7, a first capacitor C1 and a fifth capacitor C5; the chip U1 is grounded after passing through a first resistor R1, a second resistor R2 and a first capacitor C1 in sequence; the chip U1 is grounded through a second resistor R2 and a first capacitor C1; the chip U1 is grounded through a sixth resistor R6 and a seventh resistor R7 respectively; the chip U1 is fed back to the chip U1 through a fifth capacitor C5; the modulation signal input end is connected with the first D trigger and the second D trigger respectively after passing through the chip U1.
4. The DPSK demodulation circuit of claim 3, wherein: the model of the chip U1 is CD74HC 4046; the model of each of the first D trigger and the second D trigger is 74HC 74.
5. The DPSK demodulation circuit of claim 4, wherein: the carrier removal circuit is a first logic gate; the carrier extraction circuit and the modulation signal input end are respectively connected to a first logic gate; the output end of the first logic gate is connected to a sampling decision circuit, and the model of the first logic gate is 74HC 86.
6. The DPSK demodulation circuit of claim 5, wherein: the sampling decision circuit comprises a first comparator, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3 and a tenth resistor R10; the modulation signal input end is connected with the first comparator and the second capacitor C2 respectively after passing through a third resistor R3; the carrier wave removing circuit is connected with the first comparator and the third capacitor C3 through a fourth resistor R4; the second capacitor C2 and the third capacitor C3 are respectively grounded; the first comparator is respectively connected with the NAND gate and the tenth resistor R10.
7. The DPSK demodulation circuit of claim 6, wherein: the first comparator is a four-way differential comparator, and the model of the first comparator is LM 339.
8. The DPSK demodulation circuit of claim 7, wherein: the resistance value of the third resistor R3 is 10K omega; the resistance value of the fourth resistor R4 is 82K omega; the resistance value of the tenth resistor R10 is 6K Ω; the capacitance value of the second capacitor C2 is 0.1 μ F; the capacitance value of the third capacitor C3 is 100 μ F.
9. A DPSK demodulation circuit as claimed in any one of claims 1-8, wherein: the signal locking circuit comprises a second logic gate, an eighth resistor R8, a fourth capacitor C4, a fifth resistor R5, a ninth resistor R9, a second comparator and an eleventh resistor R11; the modulation signal input end and the carrier extraction circuit are respectively connected with an eighth resistor R8 through a second logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the second comparator; the power supply input end of the second comparator is connected to the positive input end of the second comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the second comparator; the output end of the second comparator is respectively connected with the eleventh resistor R11 and the second logic gate.
10. The DPSK demodulation circuit of claim 9, wherein: the second comparator is a four-way differential comparator, and the model of the second comparator is LM 339; the model of the second logic gate is 74HC 86; the resistance value of the eighth resistor R8 is 90K omega; the resistance value of the ninth resistor R9 is 21K omega; the resistance value of the fifth resistor R5 is 30K omega; the resistance value of the eleventh resistor R11 is 6K omega; the capacitance value of the fourth capacitor C4 is 1000 pF; the model of the NAND gate is 74HC 0D.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4575684A (en) * | 1985-02-22 | 1986-03-11 | Honeywell Inc. | Differential phase shift keying receiver |
| US20070047971A1 (en) * | 2005-08-25 | 2007-03-01 | Fujitsu Limited | RZ-DPSK optical receiver circuit |
| CN108055224A (en) * | 2017-12-07 | 2018-05-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | 16QAM carrier synchronization loop genlocing detection methods |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4575684A (en) * | 1985-02-22 | 1986-03-11 | Honeywell Inc. | Differential phase shift keying receiver |
| US20070047971A1 (en) * | 2005-08-25 | 2007-03-01 | Fujitsu Limited | RZ-DPSK optical receiver circuit |
| CN108055224A (en) * | 2017-12-07 | 2018-05-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | 16QAM carrier synchronization loop genlocing detection methods |
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