CN110970489B - Semiconductor device and method of forming semiconductor device - Google Patents

Abstract

The present disclosure relates to semiconductor devices and methods of forming semiconductor devices. A method comprising: forming a first fin extending from the substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along the sidewalls of the first gate stack, the first spacer comprising a first silicon oxycarbide composition, forming a second spacer along the sidewalls of the first spacer, the second spacer comprising a second silicon oxycarbide composition, forming a third spacer along the sidewalls of the second spacer, the third spacer comprising silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer.

Description

Semiconductor device and method of forming semiconductor device

technical field

The present disclosure generally relates to semiconductor devices and methods of forming semiconductor devices.

Background technique

Semiconductor devices are used in various electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric material, conductive material, and semiconducting material over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and element.

The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated in a given area. However, as the minimum feature size decreases, other issues arise that should be addressed.

Contents of the invention

According to an embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first fin and a second fin over a substrate; forming a first dummy gate structure over the first fin and forming a first dummy gate structure over the substrate. forming a second dummy gate structure over the second fin; depositing a first dummy gate structure on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure a layer of silicon oxycarbide material; implanting impurities into the first fin and the second fin through the first layer of silicon oxycarbide material; after implanting impurities, depositing over the first layer of silicon oxycarbide material A second layer of silicon oxycarbide material; after depositing the second layer of silicon oxycarbide material, perform a wet cleaning process on the first fin and the second fin; forming a first mask over the dummy gate structure; recessing the first fin adjacent to the first dummy gate structure to form a first groove in the first fin; After finning, performing the wet cleaning process on the first fin and the second fin; forming a second mask over the first fin and the first dummy gate structure; two dummy gate structures adjacent to the second fin to form a second groove in the second fin; and performing an epitaxial process to simultaneously form a first epitaxial source/drain in the first groove pole region and a second epitaxial source/drain region in the second recess.

According to another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: patterning a substrate to form a plurality of first fins and a plurality of second fins; forming a plurality of fins on the plurality of first fins; a plurality of first dummy gate structures; forming a plurality of second dummy gate structures on the plurality of second fins; forming a plurality of first spacer structures on the plurality of first dummy gate structures; A plurality of second spacer structures are formed on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures include a low-k dielectric material; forming a first groove in a plurality of first fins, comprising: performing a first wet desmear process; and performing a first anisotropic etching process to form a first groove in the plurality of first fins; After forming the first grooves in the plurality of first fins, forming second grooves in the plurality of second fins includes: performing a second wet desmear process; and performing a second anisotropic etching process to form second recesses in the plurality of second fins; and epitaxially growing a first source/drain structure in the first recesses and epitaxially growing a second source in the second recesses /drain structure.

According to yet another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first fin extending from a substrate; forming a fin over the first fin and along a sidewall of the first fin. a first gate stack; forming a first spacer along a sidewall of the first gate stack, the first spacer comprising a first silicon oxycarbide composition; along a sidewall of the first spacer forming a second spacer comprising a second silicon oxycarbide composition; forming a third spacer along sidewalls of the second spacer, the third spacer comprising silicon nitride; and A first epitaxial source/drain region is formed in the first fin and adjacent to the third spacer.

Description of drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 shows an example of a FinFET in a three-dimensional view according to some embodiments.

2, 3, 4, 5, 6, 7, 8A, 8B, 9A, and 9B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments.

10 is a graph of simulated data showing the variation in parasitic capacitance of a FinFET device relative to the dielectric constant of a spacer of the FinFET device, according to some embodiments.

11A and 11B are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments.

12A and 12B are cross-sectional views of a first wet cleaning process in an intermediate stage of fabrication of a FinFET according to some embodiments.

13A, 13B, 14A, and 14B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments.

15A and 15B are cross-sectional views of a second wet cleaning process in an intermediate stage of fabrication of a FinFET according to some embodiments.

16A, 16B, 17A, 17B, 18A, and 18B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments.

19A-19B are cross-sectional views of forming epitaxial source/drain regions in an intermediate stage of fabrication of a FinFET, according to some embodiments.

20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24, 25A, 25B, 26A, and 26B are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments.

27 is a graph of experimental data showing variation in carbon concentration of a spacer layer of a FinFET device according to some embodiments.

Detailed ways

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where the first and second features may be formed on or over the first and second features. An embodiment in which an additional feature is formed between two features such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various examples. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms (e.g., "below", "beneath", "below", "above", "upper", etc.) may be used herein to facilitate description of one element or feature shown in the figures relative to the other. relationship to another element(s) or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation than those depicted in the figures. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide processes for forming gate spacers and forming epitaxial source/drain regions in FinFET devices. In some embodiments, a low-k material such as silicon oxycarbide may be used for some or all of the gate spacers. Using silicon oxycarbide for gate spacers can reduce parasitic capacitance within FinFET devices. In addition, using the same epitaxial formation process, selectively masking the device regions and etching grooves for the epitaxial source/drain regions in each device region separately can simultaneously form different epitaxial source/drains in each device region polar region. Thus, epitaxial source/drain regions for different types of devices can be formed simultaneously, with characteristics specific to each type of device. Damage to the silicon oxycarbide layer can be reduced by using a wet chemical process of heated sulfuric acid and hydrogen peroxide to clean and prepare the surface before each multi-patterning step. Thus, both the benefits of silicon oxycarbide and the benefits of multiple patterning can be realized in the process flow with less potential for process defects.

Figure 1 illustrates an example of a FinFET in a three-dimensional view, according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (eg, a semiconductor substrate). Isolation regions 56 are disposed in substrate 50 , and fins 52 protrude from between and over adjacent isolation regions 56 . Although the isolation region 56 is described/illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including the isolation region. Furthermore, although fin 52 is shown as a single continuous material as substrate 50 , fin 52 and/or substrate 50 may comprise a single material or a plurality of materials. Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52 , and gate electrode 94 is over gate dielectric layer 92 . Source/drain regions 82 are disposed in the opposite side of fin 52 from gate dielectric layer 92 and gate electrode 94 .

Figure 1 further shows the reference cross section used in the following figures. The cross-section A-A is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions 82 of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of fin 52, and in the direction of current flow between, for example, source/drain regions 82 of a FinFET. Cross section C-C is parallel to cross section A-A and extends through the source/drain regions of the FinFET. For clarity, the subsequent figures refer to these reference cross-sections.

Some of the embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects for use in planar devices (eg, planar FETs).

2-9B and 11A-26B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Figures 2 to 7 illustrate the reference cross-section A-A shown in Figure 1, except for multiple fins/FinFETs. In FIGS. 8A to 9B , 11A to 11B , and 20A to 26B , the drawings ending with "A" marks are shown along the reference cross-section A-A shown in FIG. A similar reference cross-section B-B is shown showing figures ending with a "B" designation, except for multiple fins/FinFETs. In FIGS. 12A to 19B , the figures ending with the designation "A" are shown along the reference cross-section C-C shown in FIG. 1, and are shown along the similar reference cross-section B-B shown in FIG. Figures at the end of the B" mark, except for multiple fins/FinFETs. FIG. 24 is shown along the reference cross-section B-B shown in FIG. 1 , except for multiple fins/FinFETs.

In Fig. 2, a substrate 50 is provided. Substrate 50 may be a semiconductor substrate, eg, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (eg, with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, eg, a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, eg, multi-layer or gradient substrates. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloys A semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.

Substrate 50 has a region 50N and a region 50P. Region 50N may be used to form n-type devices, eg, NMOS transistors, such as n-type FinFETs. Region 50P may be used to form p-type devices, eg, PMOS transistors, such as p-type FinFETs. Region 50N may be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between region 50N and region 50P. . In some embodiments, both regions 50N and 50P are used to form the same type of device, eg, both regions are used for n-type devices or p-type devices.

In some embodiments, more than one n-type device may be formed in region 50N, or more than one p-type device may be formed in region 50P. For example, in some embodiments, region 50P may include sub-region 50P-1 in which a first p-type device (e.g., a p-type FinFET of the first design) is formed, and a second p-type device (e.g., , subregion 50P-2 of the p-type FinFET of the second design). (See, for example, the embodiments described below with reference to FIGS. 12A-19B.) In some embodiments, a multi-patterning process (eg, “2P2E " process or other type of multi-patterning process) to form different devices in different subregions. Region 50N may similarly include subregions in which different n-type devices are formed. In some embodiments, region 50N or region 50P may Contains only one region or may contain two or more sub-regions. Sub-regions may be physically separated from other sub-regions and any number of device features may be arranged between sub-regions.

In FIG. 3 , fins 52 are formed in substrate 50 . Fin 52 is a semiconductor strip. In some embodiments, fins 52 may be formed in substrate 50 by etching trenches in substrate 50 . Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. Etching can be anisotropic.

Fins can be patterned by any suitable method. For example, one or more photolithographic processes may be used to pattern the fins, including double patterning or multiple patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with eg smaller pitches than achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

In FIG. 4 , insulating material 54 is formed over substrate 50 and between adjacent fins 52 . The insulating material 54 can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (for example, remote plasma CVD-based material deposition and post-curing in the system to convert it into another material, such as an oxide, etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, insulating material 54 is silicon oxide formed by a FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, insulating material 54 is formed such that excess insulating material 54 covers fins 52 . Although insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, liners (not shown) may be formed first along the surfaces of substrate 50 and fins 52 . Thereafter, a fill material such as discussed above may be formed over the liner.

In FIG. 5 , a removal process is applied to insulating material 54 to remove excess insulating material 54 over fins 52 . In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch back process, combinations thereof, etc. may be used. The planarization process exposes fins 52 such that after the planarization process is complete, the top surfaces of fins 52 and insulating material 54 are horizontal.

In FIG. 6 , insulating material 54 is recessed to form shallow trench isolation (STI) regions 56 . Insulating material 54 is recessed such that upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56 . Additionally, the top surface of STI region 56 may have a planar surface as shown, a convex surface, a concave surface (eg, a depression), or a combination thereof. With appropriate etching, the top surface of STI region 56 may be formed to be flat, convex and/or concave. STI regions 56 may be recessed using an acceptable etch process, eg, an etch process that is selective to the material of insulating material 54 (eg, etches the material of insulating material 54 at a faster rate than the material of fin 52 ). For example, chemical oxides that can be removed using a suitable etch process, for example using dilute hydrofluoric (dHF) acid, may be used.

The process described with respect to FIGS. 2-6 is just one example of how fin 52 may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50 and trenches may be etched through the dielectric layer to expose underlying substrate 50 . The homoepitaxial structure may be grown epitaxially in the trench, and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, heteroepitaxial structures may be used for fins 52 . For example, fin 52 in FIG. 5 may be recessed, and a material other than fin 52 may be grown epitaxially over recessed fin 52 . In such an embodiment, fin 52 includes a recessed material, and an epitaxially grown material disposed over the recessed material. In still further embodiments, a dielectric layer may be formed over the top surface of substrate 50, and trenches may be etched through the dielectric layer. The heteroepitaxial structure may then be epitaxially grown in the trench using a different material than substrate 50 , and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form fin 52 . In some embodiments, the homoepitaxial structure or the heteroepitaxial structure is grown epitaxially. Epitaxially grown materials can be doped in situ during growth, which avoids previous and subsequent implants, but in situ doping and implant doping can be used together.

Still further, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium ( _{SixGe1 -x} , where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V Formation of compound semiconductors, II-VI compound semiconductors, etc. For example, useful materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Additionally, in FIG. 6 , suitable wells (not shown) may be formed in fin 52 and/or substrate 50 . In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

In embodiments with different well types, photoresist or other masks (not shown) may be used to achieve different implant steps for regions 50N and 50P. For example, photoresist may be formed over fins 52 and STI regions 56 in region 50N. The photoresist is patterned to expose regions 50P of substrate 50 , eg, PMOS regions. The photoresist can be formed using spin coating techniques, and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, for example, an NMOS region . The n-type impurity may be phosphorus, arsenic, or the like implanted into the region at a concentration equal to or less than 10 ¹⁸ cm ⁻³ (for example, between about 10 ¹⁷ cm ⁻³ and about 10 ¹⁸ cm ⁻³ ). After implantation, the photoresist is removed, eg, by an acceptable ashing process.

After region 50P is implanted, photoresist is formed over fins 52 and STI regions 56 in region 50P. The photoresist is patterned to expose regions 50N of substrate 50 , eg, NMOS regions. The photoresist can be formed using spin coating techniques, and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into region 50P, for example, a PMOS region . The p-type impurity may be boron, BF ₂ , etc. implanted into the region at a concentration equal to or less than 10 ¹⁸ cm ⁻³ (for example, between about 10 ¹⁷ cm ⁻³ and about 10 ¹⁸ cm ⁻³ ). After implantation, the photoresist is removed, eg, by an acceptable ashing process.

After the implantation of the regions 50N and 50P, annealing may be performed to activate the implanted p-type and/or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which avoids implantation, but in situ doping and implant doping can be used together.

In FIG. 7 , dummy dielectric layer 60 is formed on fin 52 . Dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60 , and a mask layer 64 is formed over the dummy gate layer 62 . A dummy gate layer 62 may be deposited on the dummy dielectric layer 60 and then planarized, eg, by CMP. A mask layer 64 may be deposited over the dummy gate layer 62 . The dummy gate layer 62 may be a conductive material, and may be selected from a group including polysilicon, polysilicon germanium (polySiGe), metal nitride, metal silicide, metal oxide, and metal. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. Dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art for depositing conductive materials. The dummy gate layer 62 may be made of other materials that have high etch selectivity from the etching of the isolation regions. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. In some embodiments, a separate dummy gate layer may be formed in the region 50N and the region 50P, and a separate mask layer may be formed in the region 50N and the region 50P. Note that dummy dielectric layer 60 is shown covering only fin 52 for illustration purposes only. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56 , extending between dummy gate layer 62 and STI region 56 .

8A-9B and 11A-11B illustrate various additional steps in the fabrication of an embodiment device. FIGS. 8A-9B and FIGS. 11A-11B show features of any one of the region 50N and the region 50P. For example, the structure shown is applicable to both region 50N and region 50P. Differences, if any, in the structure of region 50N and region 50P are described in the text associated with each figure.

In FIGS. 8A and 8B , masking layer 64 may be patterned to form mask 74 using acceptable photolithography and etching techniques. The pattern of mask 74 may then be transferred to dummy gate layer 62 . In some embodiments, the pattern of mask 74 may also be transferred to dummy dielectric layer 60 by acceptable etching techniques, forming dummy gate 72 over the remainder of dummy dielectric layer 60 . In some embodiments (not separately shown), dummy dielectric layer 60 may not be patterned. The dummy gate 72 covers the corresponding channel region 58 of the fin 52 . The pattern of mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gates 72 may also have length directions that are substantially perpendicular to the length directions of the corresponding epitaxial fins 52 .

Additionally, in FIGS. 8A and 8B , a first spacer material 78 is formed on the exposed surfaces of dummy gate 72 , mask 74 , and/or fin 52 . The first spacer material 78 is used to form the first spacer 80 (see FIGS. 11A-11B ). In some embodiments, the first spacer material 78 may be a material such as an oxide, a nitride, a material such as silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, etc., or a combination thereof. In some embodiments, the first spacer material 78 may be formed using a process such as thermal oxidation, CVD, PE-CVD, ALD, PVD, sputtering, or the like. In FIG. 8B , first spacer material 78 is shown extending vertically over dummy gate 72 and mask 74 and laterally over fin 52 . In some embodiments, first spacer material 78 may include multiple layers of one or more materials. In some embodiments, first spacer material 78 may be formed to have a thickness between about 3 nm and about 5 nm.

In some cases, the parasitic capacitance of a device (eg, a FinFET device) can be reduced by using a material with a smaller dielectric constant (k). For example, using first spacer material 78 with a lower dielectric constant to form first spacer 80 can reduce parasitic capacitance within the FinFET device, for example, between gate electrode 94 and source/drain contact 112. capacitance (see Figure 26A-B). In some embodiments, first spacer material 78 may include a material having a dielectric constant less than about k=3.9, eg, about k=3.5 or less. For example, a silicon oxycarbide material may be used for the first spacer material 78 in some embodiments. Silicon oxycarbide has a dielectric constant of about k=3.5 or less, so using silicon oxycarbide for the first spacer material 78 can reduce parasitic capacitance within the FinFET device. In some embodiments, the silicon oxycarbide material may be deposited using techniques such as ALD or the like. In some embodiments, the silicon oxycarbide material may be deposited using a process temperature between about 50°C and about 80°C and a process pressure between about 5 Torr and about 10 Torr. In some embodiments, silicon oxycarbide can be formed to have between about 40 atomic % and about 46 atomic % silicon, between about 45 atomic % and about 50 atomic % oxygen, or between about 5 atomic % and about 18 atomic % % carbon between. In some embodiments, different regions or different layers of the first spacer material 78 may comprise different silicon oxycarbide compositions.

After the first gate spacer material 78 is formed, an implant into lightly doped source/drain (LDD) regions (not explicitly shown) may be performed. In an embodiment with a different device type, similar to the implantation discussed above in FIG. Material 78 implants an appropriate type (eg, n-type or p-type) of impurities into fin 52 in region 50P. The mask can then be removed. Subsequently, a mask, eg, photoresist, may be formed over region 50P, exposing region 50N, and an appropriate type of impurity may be implanted through first spacer material 78 into fin 52 in region 50N. The mask can then be removed. The n-type impurity may be any n-type impurity or other n-type impurity previously discussed above in FIG. 6 , and the p-type impurity may be any p-type impurity or other p-type impurity previously discussed above in FIG. 6 . The lightly doped source/drain regions may have an impurity concentration between about 10 ¹⁵ cm ⁻³ and about 10 ¹⁶ cm ⁻³ . Annealing can be used to activate the implanted impurities. Since the LDD dopant implant is performed through the first spacer material 78, portions of the first spacer material 78 (and portions of the first spacer 80) may also be doped with the implanted impurities. As such, in some embodiments, the first spacer material 78 may have a higher impurity concentration than the second spacer material 79 (see FIGS. 9A-9B ) formed after impurity implantation.

In FIGS. 9A and 9B , a second spacer material 79 is formed on the first spacer material 78 . The second spacer material 79 is used to form the second spacer 81 (see FIGS. 11A-11B ). In some embodiments, the second spacer material 79 may be a material such as an oxide, a nitride, a material such as silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, etc., or a combination thereof. In some embodiments, the second spacer material 79 may be formed using a process such as CVD, PE-CVD, ALD, PVD, sputtering, or the like. In some embodiments, second spacer material 79 may include multiple layers of one or more materials. In some embodiments, second spacer material 79 may be formed to have a thickness between about 3 nm and about 5 nm. Since the second spacer material 79 is formed after implanting impurities, the second spacer material 79 may have a lower impurity concentration than the first spacer material 78 . In some embodiments, second spacer material 79 and second spacer 81 (not separately illustrated) are omitted.

Similar to the first spacer material 78 described above (see FIG. 8B ), by forming the second spacer 81 (see FIG. 11B ) from the second spacer material 79 with a lower dielectric constant, device (eg, FinFET devices) can be reduced. within the parasitic capacitance. In some embodiments, the second spacer material 79 may include silicon oxycarbide, and thus may have a dielectric constant less than about k=3.9, eg, about k=3.5 or less. The silicon oxycarbide material of the second spacer material 79 may be formed in a manner similar to that previously described for the silicon oxycarbide of the first spacer material 78, although the second spacer material may be formed differently in other embodiments. Spacer material 79 . The composition of the silicon oxycarbide of the second spacer material 79 may be similar to that previously described for the silicon oxycarbide of the first spacer material 78 .

In some embodiments, both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 may be formed of silicon oxycarbide. The first spacer material 78 and the second spacer material 79 may have about the same silicon oxycarbide composition or have different compositions. For example, first spacer material 78 may have a composition of between about 45 atomic % and about 48 atomic % oxygen and/or between about 12 atomic % and about 15 atomic % carbon. The second spacer material 79 may have a composition of between about 47 atomic % and about 50 atomic % oxygen and/or between about 10 atomic % and about 13 atomic % carbon. The first spacer material 78 or the second spacer material 79 may have other compositions than these examples. In some cases, both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 may be formed from silicon oxycarbide than from a different material (eg, having a higher dielectric constant material) forming one or both of the first spacer 80 or the second spacer reduces the parasitic capacitance more.

Turning to FIG. 10 , the graph shows simulated data for the percent change in the parasitic capacitance (on the Y-axis) of the FinFET device relative to the dielectric constant (k) of the second spacer 81 (on the X-axis). The change in parasitic capacitance is relative to point 121 , which indicates that both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 have a dielectric constant of about k=5. Point 122 represents the change in capacitance due to the first spacer material 78 having a dielectric constant of about k=5 and the second spacer material 79 having a dielectric constant of about k=4. As shown, the smaller dielectric constant of the second spacer material 79 reduces the parasitic capacitance by about 2%.

Still referring to FIG. 10 , point 123 indicates that since the first spacer material 78 of the first spacer 80 has a dielectric constant of about k=5 and the second spacer material 79 of the second spacer 81 is composed of a dielectric constant of about k=3.5 Constant silicon oxycarbide formation results in a change in capacitance. As shown, the smaller dielectric constant of silicon oxycarbide reduces the parasitic capacitance by about 3.5%. Point 124 represents the change in capacitance due to the fact that both the first spacer material 78 and the second spacer material 79 are formed from silicon oxycarbide having a dielectric constant of approximately k=3.5. As shown, by forming the first spacer material 78 and the second spacer material 79 from silicon oxycarbide, the parasitic capacitance can be reduced by about 6.5%. Therefore, as shown in the graph of FIG. 10, forming both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 from silicon oxycarbide can reduce the gap between devices such as FinFETs. The parasitic capacitance of devices of the class. The graphs and simulated data shown in FIG. 10 are for illustrative purposes, and the dielectric constants of the first spacer material 78 or the second spacer material 79 may otherwise be different, or the first spacer material The change in capacitance of the various materials of the second spacer material 78 or the second spacer material 79 may be different in other cases.

Turning to FIGS. 11A and 11B , first spacers 80 , second spacers 81 , and sidewall spacers 86 are formed. For example, sidewall spacers 86 may be formed by conformally depositing an insulating material over second spacer material 79 and subsequently anisotropically etching the insulating material. In some embodiments, the anisotropic etch of the insulating material also etches first spacer material 78 to form first spacers 80 and etches second spacer material 79 to form second spacers 81 . The second spacer 81 may have a lower implanted impurity concentration than the first spacer 80 , as described above with respect to the second spacer material 79 and the first spacer material 78 . In some embodiments, the insulating material of sidewall spacers 86 may be a low-k dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG ), silicon nitride, silicon oxycarbide, silicon carbide, silicon carbonitride, etc., or a combination thereof. The material of sidewall spacers 86 may be formed by any suitable method, eg, CVD, PE-CVD, ALD, or the like. In some embodiments, sidewall spacers 86 may have a thickness between about 3 nm and about 5 nm.

Turning to FIGS. 12A-19B , epitaxial source/drain regions 82A-B are formed in fin 52 according to some embodiments. 12A-19B illustrate the formation of epitaxial source/drain regions 82A in subregion 50P- 1 and the formation of epitaxial source/drain regions 82B in subregion 50P- 2 . Subregion 50P- 1 and subregion 50P- 2 may be subregions of region 50P of substrate 50 . The epitaxial source/drain regions in region 50N and in region 50P, including epitaxial source/drain regions 82A-B, may be collectively referred to herein as epitaxial source/drain regions 82 . 12A, 13A, 14A, 15A, 16A, 17A, 18A and 19A are shown along the reference cross-section C-C shown in FIG. The reference cross-section shown in B-B is shown. Epitaxial source/drain regions 82 are formed in fins 52 such that each dummy gate 72 is disposed between a corresponding pair of adjacent epitaxial source/drain regions 82 . In some embodiments, epitaxial source/drain regions 82 may extend into fin 52 . In some embodiments, sidewall spacers 86 are used to separate epitaxial source/drain regions 82 from dummy gate 72 by an appropriate lateral distance such that epitaxial source/drain regions 82 do not interfere with the gate of a subsequently formed FinFET. Very short circuit.

Turning to FIGS. 12A-12B , a first wet cleaning process 95A is performed. The first wet cleaning process 95B may be a wet chemical cleaning process (eg, a "scum removal" process) that removes residues from the surface. The first wet cleaning process 95A may also include a surface treatment that bonds oxygen atoms to the surface of the sidewall spacers 86 , which reduces outgassing of species such as nitrogen or hydrogen during subsequent process steps. In some cases, outgassing (eg, _NHx outgassing) can lead to defects during photoresist development (sometimes referred to as "photoresist poisons"). A first wet cleaning process 95A may be performed to prepare the structure for forming the mask 91A (see FIGS. 13A-13B ).

In some embodiments, the first wet cleaning process 95A may include a heated mixture of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). The mixture may be, for example, sulfuric acid and hydrogen peroxide mixed in a molar ratio between about 2:1 and about 5:1. The mixture may be heated to a temperature between about 80°C and about 180°C. During the first wet cleaning process 95A, for example, the structure may be submerged in the heated mixture. Such mixtures described herein can remove residues and also reduce the likelihood of lithography-related defects during photoresist patterning, for example, defects due to "photoresist poisons."

Additionally, the heated mixture of sulfuric acid and hydrogen peroxide used in the first wet cleaning process 95A may require less The first spacer 80 and the second spacer 81 are seriously damaged. For example, some oxygen plasma cleaning techniques may deplete the silicon oxycarbide layer of carbon, causing damage to the layer and thus also causing possible process problems or defects. Thus, use of the mixtures described herein can reduce lithography-related defects (eg, "photoresist poisons") while also causing fewer damage-related defects when silicon oxycarbide materials are used. For example, by using the mixture described herein in the first wet cleaning process 95A, both the first spacers 80 and the second spacers 81 can be formed from a silicon oxycarbide material, reducing the overall potential for process problems or defects. sex. In this way, the benefits of using both cleaning processes (eg, improved photolithography) and silicon oxycarbide materials (eg, reduced parasitic capacitance) can be realized.

Turning to FIGS. 13A-13B , mask 91A is formed over sub-region 50P- 2 . The mask 91A may include a single layer or may be a multi-layer structure (eg, a double-layer structure, a triple-layer structure, or have more than three layers). Mask 91A may include materials such as photoresist materials, oxide materials, nitride materials, other dielectric materials, etc., or combinations thereof. In some embodiments, mask 91A includes a bottom antireflective coating (BARC). Mask 91A may be formed using one or more suitable techniques, for example, spin coating techniques, CVD, PE-CVD, ALD, PVD, sputtering, etc., or combinations thereof. Mask 91A may be patterned using suitable photolithography and etching processes to expose portions of sub-region 50P- 1 . For example, mask 91A may be etched using one or more wet etch processes or an anisotropic dry etch process.

Turning to FIGS. 14A-14B , grooves 84A are formed in fins 52 of sub-region 50P- 1 , according to some embodiments. Groove 84A may be formed using, for example, an anisotropic dry etching process. In some cases, portions of first spacer 80 , second spacer 81 , or sidewall spacer 86 may also be etched by an anisotropic dry etching process. The exemplary etching of spacers 80 , 81 , and 86 shown in FIG. 14A is intended to be illustrative, and in other embodiments, an anisotropic dry etching process may etch spacers 80 , 81 , or 86 differently. For example, in other embodiments, the anisotropic dry etch process may etch portions of spacers 80, 81, and 86 by different amounts such that one or more of spacers 80, 81, or 86 are more over STI region 56 than The other of the spacers 80, 81 or 86 extends higher. These and other variations are intended to fall within the scope of this disclosure. In some embodiments, the process parameters of the anisotropic dry etching process may be controlled so that the recess 84A or the spacers 80, 81 or 86 are etched to have desired characteristics. Process parameters may include, for example, process gas mixture, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some cases, the shape, volume, size, or shape of epitaxial source/drain regions 82A formed in recess 84A may be controlled by controlling the etching of recess 84A or spacers 80, 81, or 86 in this manner. Other properties (see Figures 18A-18B).

Turning to FIGS. 15A-15B , the mask 91A is removed and a second wet clean process 95B is performed. Mask 91A may be removed using a suitable process, for example, a wet chemical process or a dry process. After removing the mask 91A, a second wet cleaning process 95B is performed to remove residues and prepare the surface for the structure forming the mask 91B (see FIGS. 16A-16B ). In some embodiments, mask 91A is removed as part of performing second wet clean process 95B. The second wet cleaning process 95B may be similar to the first wet cleaning process 95A (see FIGS. 12A-12B ). For example, the second wet cleaning process 95B may use a heated mixture of sulfuric acid and hydrogen peroxide. The mixture may have a similar composition as described for the first wet cleaning process 95A and may be heated to a similar temperature. In other cases, the second wet cleaning process 95B may be a different mixture of sulfuric acid and hydrogen peroxide than that used in the first wet cleaning process 95A, and may be heated to a different temperature. Similar to the first wet cleaning process 95A, using a heated mixture of sulfuric acid and hydrogen peroxide can reduce damage to the silicon oxycarbide layer, for example, where the first spacer 80 and/or the second spacer 81 are oxidized from carbon Example of silicon formation.

Turning to FIGS. 16A-16B , mask 91B is formed over subregion 50P- 1 . The mask 91B may include a single layer or may be a multilayer structure (eg, a double layer structure, a triple layer structure, or have more than three layers). Mask 91A may include materials such as photoresist materials, oxide materials, nitride materials, other dielectric materials, etc., or combinations thereof. In some embodiments, mask 91B includes a bottom antireflective coating (BARC). Mask 91B may be formed using one or more suitable techniques, such as spin coating techniques, CVD, PE-CVD, ALD, PVD, sputtering, etc., or combinations thereof. Mask 91B may be patterned using suitable photolithography and etching processes to expose portions of sub-region 50P- 2 . For example, mask 91B may be etched using one or more wet etch processes or an anisotropic dry etch process. Mask 91B may be similar to mask 91A (see FIGS. 13A-13B ) or different from mask 91A.

Turning to FIGS. 17A-17B , grooves 84B are formed in fins 52 of sub-region 50P- 2 in accordance with some embodiments. Groove 84B may be formed using, for example, an anisotropic dry etching process. In some cases, portions of first spacer 80 , second spacer 81 , or sidewall spacer 86 may also be etched by an anisotropic dry etching process. In some embodiments, the process parameters of the anisotropic dry etching process may be controlled in order to etch the recess 84B or the spacers 80, 81 or 86 to have desired characteristics. The process parameters for the etching of the sub-region 50P- 2 may be different from the process parameters for the etching of the sub-region 50P- 1 . Process parameters may include, for example, process gas mixture, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some embodiments, process parameters may be controlled such that groove 84B in subregion 50P- 2 is different (eg, has a different depth, width, shape, etc.) than groove 84A in subregion 50P- 1 . Process parameters may also be controlled such that the spacers 80, 81, or 86 in subregion 50P-2 are different (e.g., have different heights, widths, shapes, etc.) than the spacers 80, 81, or 86 in subregion 50P-1 . These are examples, and these and other variations are intended to fall within the scope of this disclosure. In some cases, the shape, volume, size, or shape of epitaxial source/drain regions 82B formed in recesses 84B may be controlled by controlling the etching of recesses 84B or spacers 80, 81, or 86 in this manner. Other properties (see Figures 18A-18B). By using separate and different etch processes within sub-region 50P- 1 and sub-region 50P- 2 , epitaxial source/drain regions in each sub-region can be formed with different properties.

Turning to Figures 18A-18B, mask 91B is removed. Mask 91B may be removed using a suitable process, for example, a wet chemical process or a dry process. In this way, the source/drain regions of subregions 50P-1 and 50P-2 can be prepared for forming epitaxial source/drain regions 82A-B (see FIGS. 19A-19B ). As described in Figures 12A-18B, multiple patterning processes can be used to etch different sub-regions differently. In some embodiments, the multi-patterning process may be a "2P2E" process such as that described in FIGS. For example, sub-region 50P-1) is etched, then the second sub-region is masked while the first sub-region is etched. In other embodiments, subregion 50P- 1 may be masked and subregion 50P- 2 etched first before subregion 50P- 2 is masked and subregion 50P- 1 is etched. More than two sub-regions can be etched in this way using different etch processes by sequentially masking and etching the appropriate sub-regions. Furthermore, by using a wet clean process similar to wet clean process 95A-B, the wet clean process can be performed prior to each masking step and is less likely to damage the layer formed of silicon oxycarbide.

Turning to FIGS. 19A-19B , epitaxial source/drain regions 82 are formed in region 50P, according to some embodiments. In some embodiments, a pre-clean process may be performed first to remove oxide (eg, native oxide) from recesses 84A-B. The pre-clean process may include a wet chemical process (eg, diluted HF), a plasma process, or a combination. Using the same epitaxial process, epitaxial source/drain region 82A is formed in recess 84A of subregion 50P-1, and epitaxial source/drain region 82B is formed in recess 84B of subregion 50P-2. In some embodiments, additional epitaxial source/drain regions may be formed in other sub-regions (if any) using the same epitaxial process as epitaxial source/drain regions 82A-B. Epitaxial source/drain regions 82A-B may comprise any acceptable material, eg, a material suitable for a p-type FinFET. For example, if fin 52 is silicon or SiGe, epitaxial source/drain regions 82A-B may comprise SiGe, SiGeB, Ge, GeSn, other materials, etc., or combinations thereof.

In some embodiments, a single epitaxial process can form different epitaxial source/drain regions in different sub-regions. The epitaxial source/drain regions may be different due to differences in recesses (e.g., recesses 84A-B) formed by different etch processes performed in the sub-regions, or spacers in the sub-regions (e.g., spacer 80, 81 or 86). For example, as shown in FIG. 19A , the epitaxial source/drain regions 82A formed in the groove 84A of the subregion 50P-1 are merged together into a single epitaxial source/drain region 82A during epitaxy, but in the subregion Epitaxial source/drain regions 82B formed in recesses 84B of 50P-2 remain unmerged. In this way, the epitaxial source/drain region 82A is formed to have a larger volume than the epitaxial source/drain region 82B.

Merged epitaxial source/drain regions 82A and unmerged epitaxial source/drain regions 82B shown in FIGS. 19A-19B are intended to serve as different epitaxial source/drain regions formed in different sub-regions using the same epitaxial process. An illustrative example of a drain region, and these and other variations are intended to be within the scope of this disclosure. In other embodiments, the epitaxial source/drain regions formed in different sub-regions may differ in other ways, eg, height, width, shape, volume, profile, and the like. In this way, FinFET devices with different epitaxial source/drain regions can be formed in different sub-regions and using the same epitaxial process. For example, logic devices may be formed in a first subregion (eg, subregion 50P- 1 ), and SRAM devices may be formed in a second subregion (eg, subregion 50P- 2 ). These are examples, other types of devices are also possible.

Epitaxial source/drain regions 82 in region 50N (eg, an NMOS region) may be formed in fin 52 by masking region 50P (eg, a PMOS region) and etching the source/drain regions of fin 52 in region 50N. grooves to form. Epitaxial source/drain regions 82 in region 50N may then be grown epitaxially in the recess. Epitaxial source/drain regions 82 in region 50N may be formed before or after forming epitaxial source/drain regions 82 in region 50P (eg, after forming the epitaxial source/drain regions 82 shown in FIGS. 19A-19B ). region 82A-B before or after) is formed. Epitaxial source/drain regions 82 of region 50N may comprise any acceptable material, eg, a material suitable for an n-type FinFET. For example, if fin 52 is silicon, epitaxial source/drain region 82 in region 50N may comprise silicon, SiC, SiCP, SiP, or the like. Epitaxial source/drain regions 82 in region 50N may have surfaces raised from corresponding surfaces of fins 52 , may or may not be merged, or may have facets.

In some embodiments, region 50N may include sub-regions, and a multiple patterning process of masking and etching the individual sub-regions may be used prior to forming epitaxial source/drain regions 82 in region 50N. The multi-patterning process may be similar to the multi-patterning process performed for sub-regions 50P- 1 and 50P- 2 of region 50P as described in FIGS. 12A-18B . In this way, different epitaxial source/drain regions can be formed in different sub-regions using the same epitaxial process, and thus different FinFET devices (e.g., SRAM devices, logic devices, etc.) can be formed in different sub-regions. ). In some embodiments, the multi-patterning process may include one or more wet clean processes similar to the previously described wet clean processes 95A-B. In this way, silicon oxycarbide can be used for the first spacers 80 and the second spacers 81 in the region 50N and is less likely to be damaged during the multi-patterning process. In some embodiments, sidewall spacers 86 may be removed after forming epitaxial source/drain regions in regions 50N or 50P or subregions thereof. Sidewall spacers 86 may be removed using, for example, anisotropic dry etching.

Epitaxial source/drain regions 82 and/or fins 52 may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly doped source/drain regions, followed by annealing. The impurity concentration of the source/drain regions may be between about 10 ¹⁹ cm ⁻³ and about 10 ²¹ cm ⁻³ . The n-type and/or p-type impurities of the source/drain regions can be any of the impurities discussed previously. In some embodiments, epitaxial source/drain regions 82 may be doped in situ during growth.

Turning to Figures 20A and 20B, ILD 88 is deposited over region 50N and region 50P. The structure shown in FIGS. 20A-20B is an example structure after formation of epitaxial source/drain regions 82 and the process steps described are applicable to any structure, embodiment or device described previously. ILD 88 may be formed from a dielectric material or a semiconductor material, and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. The semiconductor material may include amorphous silicon, silicon germanium ( _Six Ge _1-x , where x may be between approximately 0 and 1), pure germanium, and the like. Other insulating or semiconducting materials formed by any acceptable process may be used. In some embodiments, contact etch stop layer (CESL) 87 is disposed between ILD 88 and epitaxial source/drain regions 82 , hardmask 74 , and sidewall spacers 86 . CESL 87 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., or combinations thereof.

In FIGS. 21A and 21B , a planarization process (eg, CMP) may be performed to make the top surface of ILD 88 flush with the top surface of dummy gate 72 . The planarization process may also remove mask 74 over dummy gate 72 and may also remove portions of first spacers 80 , second spacers 81 , and sidewall spacers 86 along sidewalls of mask 74 . After the planarization process, the top surfaces of the dummy gate 72 , the first spacer 80 , the second spacer 81 , the sidewall spacer, and the ILD 88 are horizontal. Accordingly, the top surface of dummy gate 72 is exposed through ILD 88 .

In FIGS. 22A and 22B , dummy gate 72 and the portion of dummy dielectric layer 60 directly underlying exposed dummy gate 72 are removed in one or more etching steps, thereby forming recess 90 . In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etch process may include a dry etch process using one or more process gases that selectively etches dummy gate 72 without etching ILD 88 or gate spacer 86 . Each groove 90 exposes a channel region of a corresponding fin 52 . Each channel region 58 is disposed between adjacent pairs of epitaxial source/drain regions 82 . During removal, dummy dielectric layer 60 may serve as an etch stop when dummy gate 72 is etched. The dummy dielectric layer 60 may then optionally be removed after the removal of the dummy gate 72 .

In FIGS. 23A and 23B , a gate dielectric layer 92 and a gate electrode 94 are formed for replacement gates, according to some embodiments. Figure 24 shows a detailed view of Figure 23B, as shown. A gate dielectric layer 92 is conformally deposited in the recess 90 , eg, on the top surface and sidewalls of the fin 52 and on the sidewalls of the first spacer 80 . A gate dielectric layer 92 may also be formed on the top surface of the first ILD 88 . According to some embodiments, gate dielectric layer 92 includes silicon oxide, silicon nitride, or layers thereof. In some embodiments, gate dielectric layer 92 is a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than about 7.0 and may include Hf, Al, Zr, La, Mg , Ba, Ti, Pb metal oxides or silicates, and combinations thereof. Formation methods of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of dummy gate dielectric 60 remain in recess 90 , gate dielectric layer 92 includes the material of dummy gate dielectric 60 (eg, silicon oxide).

Gate electrodes 94 are respectively deposited over gate dielectric layer 92 and fill the remainder of recesses 90 . Gate electrode 94 may be a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 94 is shown in FIG. 23B, the gate electrode 94 may include any number of pad layers 94A, any number of work function adjustment layers 94B, and a filling material 94C, as shown in FIG. . After gate electrode 94 is filled, a planarization process such as CMP may be performed to remove excess portions of gate dielectric layer 92 and gate electrode 94 material that are above the top surface of ILD 88 . Thus, the remainder of the material of gate electrode 94 and gate dielectric layer 92 forms the replacement gate of the resulting FinFET. Gate electrode 94 and gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and gate stack may extend along the sidewalls of the channel region 58 of the fin 52 .

The formation of gate dielectric layer 92 in region 50N and region 50P may occur simultaneously such that gate dielectric layer 92 in each region is formed from the same material, and the formation of gate electrode 94 may occur simultaneously such that each region The gate electrode 94 in is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by a different process, such that gate dielectric layer 92 may be of a different material, and/or gate electrode 94 in each region may be formed by a different process. process, so that the gate electrode 94 can be of different materials. When using different processes, various masking steps can be used to mask and expose appropriate areas.

In FIGS. 25A and 25B , ILD 108 is deposited over ILD 88 . In an embodiment, ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, eg, CVD, PE-CVD, or the like.

In FIGS. 26A and 26B , contacts 110 and 112 are formed by ILD 108 and ILD 88 , according to some embodiments. In some embodiments, an anneal process may be performed to form suicide at the interface between the epitaxial source/drain regions 82 and the contact 112 prior to forming the contact 112 . Contact 110 is physically and electrically connected to gate electrode 94 and contact 112 is physically and electrically connected to epitaxial source/drain region 82 . 26A-26B illustrate that contacts 110 and 112 are in the same cross-section; however, in other embodiments, contacts 110 and 112 may be disposed in different cross-sections. Furthermore, the locations of contacts 110 and 112 in FIGS. 26A-26B are illustrative only and are not intended to be limiting in any way. For example, contact 110 may be vertically aligned with fin 52 as shown, or may be disposed at a different location on gate electrode 94 . Additionally, contact 112 may be formed before, simultaneously with, or after forming contact 110 .

Turning to FIG. 27 , the graph shows experimental data for the measurement of the concentration of carbon present in the first spacer 80 and the second spacer 81 formed of a silicon oxycarbide material. Figure 27 shows the measured carbon concentrations after different process steps, called steps A, B, C and D. In FIG. 27, points 125A-D show the carbon concentration of the first sample, points 126A-D show the carbon concentration of the second sample, and points 127A-D show the carbon concentration of the third sample. As described in more detail below, a first wet cleaning process 95A and a second wet cleaning process 95B are used to clean the first sample (points 125A-D) and the second sample (points 126A-D), but the oxygen plasma A bulk process was used to clean the third sample (points 127A-D). Process step A corresponds to the step after forming first spacer 80 and second spacer 81, and thus points 125A, 126A, and 127A show the initial carbon concentration of the sample (eg, as shown in FIGS. 11A-11B ) .

Process step B corresponds to a step after the 2P2E multi-patterning process described in FIGS. 12A-18B has been performed. However, the first sample (points 125A-D) and the second sample (points 126A-D) used the previously described first wet cleaning process 95A and second wet cleaning process 95B, while the third sample (points 127A- D) Using a separate oxygen plasma process instead of the first wet cleaning process 95A and the second wet cleaning process 95B. As indicated by points 125B and 126B, the wet cleaning process 95A-B performed on the first and second samples reduced the carbon concentration of the first spacer 80 and the second spacer 81 of the first and second samples to About 50% of the initial carbon concentration (points 125A and 126A). As shown at point 127B, the oxygen plasma process performed on the third sample reduced the carbon concentration of first spacer 80 and second spacer 81 to less than about 10% of the initial carbon concentration (point 127A). The reduction in carbon concentration indicates increased damage to the first spacer 80 and the second spacer 81 by the oxygen plasma process. Thus, FIG. 27 shows that the carbon concentration of the silicon oxycarbide material can be reduced less using wet cleaning processes 95A-B than other types of cleaning processes. The data shown in FIG. 27 is an illustrative example, and the carbon concentration can be reduced by a greater amount or by a lesser amount in other cases using the wet cleaning process 95A-B.

Process step C corresponds to a step prior to performing the pre-cleaning process as described in FIGS. 19A-19B . As shown, the first sample (point 125C), the second sample (point 126C), and the third sample (point 127C) maintain approximately the same carbon concentration as at process step B. Process step D corresponds to the steps preceding the formation of epitaxial source/drain regions 82A-B as described in FIGS. 19A-19B . As shown, the first sample (point 125D), the second sample (point 126D), and the third sample (point 127D) maintain approximately the same carbon concentration as at process step B and process step C. Therefore, in some cases, after performing the wet cleaning process 95A-B, additional processes do not further reduce the carbon concentration.

Embodiments described herein may realize advantages. By using a wet cleaning process that includes a heated mixture of sulfuric acid and hydrogen peroxide, the silicon oxycarbide material can be used as part of a FinFET device with less risk of damage to the silicon oxycarbide material. For example, silicon oxycarbide material may be used for one, two or more spacers formed on the sidewalls of the dummy gates during the process. Since silicon oxycarbide has a relatively low dielectric constant, the use of silicon oxycarbide (eg, as a spacer material) within a FinFET device can reduce the parasitic capacitance of the FinFET device. For example, parasitic capacitance between the metal gate and source/drain contacts can be reduced. By reducing parasitic capacitance, the performance of FinFET devices can be improved, especially at higher frequency operations. Additionally, use of a wet cleaning process mixture as described herein may allow more reliable use of silicon oxycarbide in addition to multiple patterning techniques. For example, by using selective masks and different etch processes for different devices, multiple patterning can be used to form devices with different epitaxial regions using the same epitaxy step. This can reduce overall process steps, improve process efficiency and reduce manufacturing costs, while also providing the benefits of using silicon oxycarbide.

In an embodiment, a method includes forming a first fin and a second fin over a substrate, forming a first dummy gate structure over the first fin and forming a second dummy gate structure over the second fin, the A first layer of silicon oxycarbide material is deposited on the first fin, on the second fin, on the first dummy gate structure and on the second dummy gate structure, and impurities are implanted into the first fin and the first fin through the first layer of silicon oxycarbide material. In the second fin, after impurity implantation, a second layer of silicon oxycarbide material is deposited over the first layer of silicon oxycarbide material, after depositing the second layer of silicon oxycarbide material, wet processing is performed on the first fin and the second fin a cleaning process, forming a first mask over the second fin and the second dummy gate structure, recessing the first fin adjacent to the first dummy gate structure to form a first groove in the first fin, forming a first groove in the recess After the first fin, perform a wet cleaning process on the first fin and the second fin, form a second mask over the first fin and the first dummy gate structure, and recess the second dummy gate structure adjacent to the second dummy gate structure. fins to form a second groove in the second fin, and performing an epitaxial process to simultaneously form a first epitaxial source/drain region in the first groove and a second epitaxial source/drain in the second groove polar region. In an embodiment, the method includes performing an anisotropic etching process on the first layer of silicon oxycarbide material to form a first spacer on the first dummy gate structure, and performing an anisotropic etching process on the second layer of silicon oxycarbide material. an etching process to form a second spacer on the second dummy gate structure. In an embodiment, the first layer of silicon oxycarbide material has a higher impurity concentration than the second layer of silicon oxycarbide material. In an embodiment, the wet cleaning process includes using a heated mixture of sulfuric acid and hydrogen peroxide. In an embodiment, the mixture of sulfuric acid and hydrogen peroxide is mixed in a molar ratio between 2:1 and 5:1. In an embodiment, the heated mixture is at a temperature between 80°C and 180°C. In an embodiment, the method includes forming sidewall spacers over the second layer of silicon oxycarbide material, the sidewall spacers comprising a different dielectric material than the silicon oxycarbide material. In an embodiment, at least two first epitaxial source/drain regions are merged together. In an embodiment, the first groove has a first depth and the second groove has a second depth different from the first depth.

In an embodiment, a method includes patterning a substrate to form a plurality of first fins and a plurality of second fins, forming a plurality of first dummy gate structures on the plurality of first fins, and forming a plurality of first dummy gate structures on the plurality of second fins. forming a plurality of second dummy gate structures on the fins, forming a plurality of first spacer structures on the plurality of first dummy gate structures, forming a plurality of second spacer structures on the plurality of second dummy gate structures, Wherein, the plurality of first spacer structures and the plurality of second spacer structures include a low-k dielectric material, and forming first grooves in the plurality of first fins includes performing a first wet desmear process and performing first each An anisotropic etching process to form first grooves in the plurality of first fins, after forming the first grooves in the plurality of first fins, forming second grooves in the plurality of second fins, including performing a second wet method descum process, and perform a second anisotropic etching process to form second grooves in the plurality of second fins, and epitaxially grow the first source/drain structure in the first grooves and in the second grooves A second source/drain structure is epitaxially grown in the trench. In an embodiment, the first source/drain structure and the second source/drain structure are formed simultaneously through the same epitaxial growth process. In an embodiment, the first anisotropic etching process is different than the second anisotropic etching process. In an embodiment, the low-k dielectric material is silicon oxycarbide. In an embodiment, forming the plurality of first spacer structures includes: depositing a first layer of low-k dielectric material using a first deposition process, performing an implantation process on the first layer of low-k dielectric material, and after performing the implantation process, using A second deposition process is used to deposit a second layer of low-k dielectric material. In an embodiment, performing the first wet deslagging process includes heating the mixture of sulfuric acid and hydrogen peroxide to a temperature between 80°C and 180°C. In an embodiment, the first source/drain structure has a larger volume than the second source/drain structure. In an embodiment, the first anisotropic etch process etches more of the first plurality of spacer structures than the second anisotropic etch process etches the second plurality of spacer structures.

In an embodiment, a method includes forming a first fin extending from a substrate, forming a first gate stack over the first fin and along sidewalls of the first fin, along sides of the first gate stack The walls form first spacers, the first spacers include a first silicon oxycarbide composition, and along sidewalls of the first spacers form second spacers, the second spacers include a second silicon oxycarbide composition, along Sidewalls of the second spacer form a third spacer, the third spacer includes silicon nitride, and a first epitaxial source/drain region is formed in the first fin adjacent to the third spacer. In an embodiment, the method includes forming a second fin extending from the substrate, forming a second gate stack over and along sidewalls of the second fin, forming a second gate stack along sidewalls of the second gate stack A fourth spacer is formed, the fourth spacer includes a first silicon oxycarbide composition, and a fifth spacer is formed along the sidewall of the fourth spacer, the fifth spacer includes a second silicon oxycarbide composition, and a fifth spacer is formed along the sidewall of the fourth spacer. The sidewalls of the five spacers form a sixth spacer comprising silicon nitride, and a second epitaxial source/drain region is formed in the second fin adjacent to the sixth spacer, wherein the second The epitaxial source/drain region has a different volume than the first epitaxial source/drain region. In an embodiment, the first fin includes silicon germanium.

The foregoing summarizes features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. It should be appreciated by those skilled in the art that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method of forming a semiconductor device, comprising: forming a first fin and a second fin over a substrate; forming a first dummy gate structure over the first fin and forming a first dummy gate structure over the second fin. Two dummy gate structures; depositing a first layer of silicon oxycarbide material on the first fin, on the second fin, on the first dummy gate structure and on the second dummy gate structure; by The first layer of silicon oxycarbide material injects impurities into the first fin and the second fin; after implanting impurities, a second layer of silicon oxycarbide material is deposited on the first layer of silicon oxycarbide material ; after depositing the second layer of silicon oxycarbide material, performing a wet cleaning process on the first fin and the second fin; forming a first fin on the second fin and the second dummy gate structure a mask; recessing the first fin adjacent to the first dummy gate structure to form a first groove in the first fin; after recessing the first fin, for the first fin performing the wet cleaning process on a fin and the second fin; forming a second mask over the first fin and the first dummy gate structure; recessing adjacent to the second dummy gate structure to form a second groove in the second fin; and performing an epitaxial process to simultaneously form a first epitaxial source/drain region in the first groove and the second A second epitaxial source/drain region in the recess.

Example 2 is the method of Example 1, further comprising: performing an anisotropic etching process on the first layer of silicon oxycarbide material to form a first spacer on the first dummy gate structure, and performing an anisotropic etching process on the first dummy gate structure, and An anisotropic etching process is performed on the second layer of silicon oxycarbide material to form a second spacer on the second dummy gate structure.

Example 3 is the method of example 1, wherein the first layer of silicon oxycarbide material has a higher impurity concentration than the second layer of silicon oxycarbide material.

Example 4 is the method of example 1, wherein the wet cleaning process includes using a heated mixture of sulfuric acid and hydrogen peroxide.

Example 5 is the method of Example 4, wherein the mixture of sulfuric acid and hydrogen peroxide is mixed in a molar ratio between 2:1 and 5:1.

Example 6 is the method of example 4, wherein the heated mixture is at a temperature between 80°C and 180°C.

Example 7 is the method of Example 1, further comprising forming sidewall spacers over the second layer of silicon oxycarbide material, the sidewall spacers comprising a different dielectric material than the silicon oxycarbide material.

Example 8 is the method of example 1, wherein at least two first epitaxial source/drain regions are merged together.

Example 9 is the method of example 1, wherein the first groove has a first depth and the second groove has a second depth different from the first depth.

Example 10 is a method of forming a semiconductor device, comprising: patterning a substrate to form a plurality of first fins and a plurality of second fins; forming a plurality of first dummy gate structures on the plurality of first fins; Forming a plurality of second dummy gate structures on the plurality of second fins; forming a plurality of first spacer structures on the plurality of first dummy gate structures; forming a plurality of first spacer structures on the plurality of second dummy gate structures; Structurally forming a plurality of second spacer structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material; forming first fins in the plurality of first fins grooves, comprising: performing a first wet desmear process; and performing a first anisotropic etching process to form first grooves in the plurality of first fins; forming the first grooves in the plurality of first fins; After the first grooves, forming second grooves in the plurality of second fins includes: performing a second wet desmear process; and performing a second anisotropic etching process to form second grooves in the plurality of second fins. forming a second recess in the fin; and epitaxially growing a first source/drain structure in the first recess and epitaxially growing a second source/drain structure in the second recess.

Example 11 is the method of Example 10, wherein the first source/drain structure and the second source/drain structure are formed simultaneously by the same epitaxial growth process.

Example 12 is the method of example 10, wherein the first anisotropic etching process is different from the second anisotropic etching process.

Example 13 is the method of example 10, wherein the low-k dielectric material is silicon oxycarbide.

Example 14 is the method of Example 10, wherein forming the plurality of first spacer structures comprises: depositing a first layer of low-k dielectric material using a first deposition process; performing on the first layer of low-k dielectric material an implantation process; and after performing the implantation process, depositing a second layer of low-k dielectric material using a second deposition process.

Example 15 is the method of Example 10, wherein performing the first wet deslagging process includes heating a mixture of sulfuric acid and hydrogen peroxide to a temperature between 80°C and 180°C.

Example 16 is the method of example 10, wherein the first source/drain structure has a larger volume than the second source/drain structure.

Example 17 is the method of Example 10, wherein the first anisotropic etch process etches the plurality of second spacer structures compared to the second anisotropic etch process etches the plurality of second spacer structures A spacer structure is more.

Example 18 is a method of forming a semiconductor device, comprising: forming a first fin extending from a substrate; forming a first gate stack over the first fin and along sidewalls of the first fin; Sidewalls of the first gate stack form first spacers, the first spacers include a first silicon oxycarbide composition; second spacers are formed along sidewalls of the first spacers, the The second spacer includes a second silicon oxycarbide composition; a third spacer is formed along a sidewall of the second spacer, the third spacer includes silicon nitride; and in the first fin and A first epitaxial source/drain region is formed adjacent to the third spacer.

Example 19 is the method of example 18, further comprising: forming a second fin extending from the substrate; forming a second gate stack over the second fin and along sidewalls of the second fin; forming a fourth spacer along the sidewall of the second gate stack, the fourth spacer comprising the first silicon oxycarbide composition; forming a fifth spacer along the sidewall of the fourth spacer member, the fifth spacer includes the second silicon oxycarbide composition; a sixth spacer is formed along a sidewall of the fifth spacer, the sixth spacer includes silicon nitride; and in the A second epitaxial source/drain region is formed in the second fin and adjacent to the sixth spacer, wherein the second epitaxial source/drain region has a Different volumes in polar regions.

Example 20 is the method of example 18, wherein the first fin comprises silicon germanium.

Claims (20)

1. A method of forming a semiconductor device, comprising: forming a first fin and a second fin over the substrate; forming a first dummy gate structure over the first fin and forming a second dummy gate structure over the second fin; depositing a first layer of silicon oxycarbide material on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure; implanting impurities into the first fin and the second fin through the first layer of silicon oxycarbide material; After implanting impurities, depositing a second layer of silicon oxycarbide material on the first layer of silicon oxycarbide material; performing a first wet cleaning process on the first fin and the second fin after depositing the second layer of silicon oxycarbide material; forming a first mask over the second fin and the second dummy gate structure; recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin; performing a second wet cleaning process on the first fin and the second fin after recessing the first fin; forming a second mask over the first fin and the first dummy gate structure; recessing the second fin adjacent to the second dummy gate structure to form a second recess in the second fin; and performing an epitaxial process to simultaneously form a first epitaxial source/drain region in the first groove and a second epitaxial source/drain region in the second groove, wherein said first epitaxial source/drain region forms a component of a first transistor, said second epitaxial source/drain region forms a component of a second transistor, and wherein said first epitaxial source/drain The electrode region and the second epitaxial source/drain region have the same conductivity type. 2. The method according to claim 1, further comprising: performing an anisotropic etching process on the first layer of silicon oxycarbide material to form a first spacer on the first dummy gate structure, and performing an anisotropic etching process on the first dummy gate structure, and performing an anisotropic etching process on the second layer of silicon oxycarbide material to form a second spacer on the second dummy gate structure. 3. The method of claim 1, wherein the first layer of silicon oxycarbide material has a higher impurity concentration than the second layer of silicon oxycarbide material. 4. The method of claim 1, wherein the wet cleaning process comprises using a heated mixture of sulfuric acid and hydrogen peroxide. 5. The method of claim 4, wherein the mixture of sulfuric acid and hydrogen peroxide is mixed in a molar ratio between 2:1 and 5:1. 6. The method of claim 4, wherein the heated mixture is at a temperature between 80°C and 180°C. 7. The method of claim 1, further comprising forming sidewall spacers over the second layer of silicon oxycarbide material, the sidewall spacers comprising a different dielectric material than the silicon oxycarbide material. 8. The method of claim 1, wherein at least two first epitaxial source/drain regions are merged together. 9. The method of claim 1, wherein the first groove has a first depth and the second groove has a second depth different from the first depth. 10. A method of forming a semiconductor device comprising: patterning the substrate to form a plurality of first fins and a plurality of second fins; forming a plurality of first dummy gate structures on the plurality of first fins; forming a plurality of second dummy gate structures on the plurality of second fins; forming a plurality of first spacer structures on the plurality of first dummy gate structures; forming a plurality of second spacer structures on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material; Forming first grooves in the plurality of first fins includes: performing a first wet deslagging process; and performing a first anisotropic etching process to form first grooves in the plurality of first fins; After forming the first grooves in the plurality of first fins, forming second grooves in the plurality of second fins includes: performing a second wet deslagging process; and performing a second anisotropic etching process to form second grooves in the plurality of second fins; and Epitaxially growing a first source/drain structure in the first groove and epitaxially growing a second source/drain structure in the second groove, wherein the first source/drain structure having the same conductivity type as the second source/drain structure. 11. The method of claim 10, wherein the first source/drain structure and the second source/drain structure are formed simultaneously by the same epitaxial growth process. 12. The method of claim 10, wherein the first anisotropic etching process is different from the second anisotropic etching process. 13. The method of claim 10, wherein the low-k dielectric material is silicon oxycarbide. 14. The method of claim 10, wherein forming the plurality of first spacer structures comprises: depositing a first layer of low-k dielectric material using a first deposition process; performing an implantation process on the first layer of low-k dielectric material; and After performing the implant process, a second deposition process is used to deposit a second layer of low-k dielectric material. 15. The method of claim 10, wherein performing the first wet deslagging process comprises heating a mixture of sulfuric acid and hydrogen peroxide to a temperature between 80°C and 180°C. 16. The method of claim 10, wherein the first source/drain structure has a larger volume than the second source/drain structure. 17. The method of claim 10, wherein the first anisotropic etch process etches the plurality of second spacer structures compared to the second anisotropic etch process etches the plurality of second spacer structures. The first spacer has more structure. 18. A method of forming a semiconductor device comprising: forming a first fin extending from the substrate; forming a first gate stack over the first fin and along sidewalls of the first fin; forming first spacers along sidewalls of the first gate stack, the first spacers comprising a first silicon oxycarbide composition; forming a second spacer along sidewalls of the first spacer, the second spacer comprising a second silicon oxycarbide composition; forming third spacers along sidewalls of the second spacers, the third spacers comprising silicon nitride; forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer; forming a second fin extending from the substrate; forming a second gate stack over the second fin and along sidewalls of the second fin; forming fourth spacers along sidewalls of the second gate stack, the fourth spacers comprising the first silicon oxycarbide composition; forming a fifth spacer along sidewalls of the fourth spacer, the fifth spacer comprising the second silicon oxycarbide composition; forming a sixth spacer along a sidewall of the fifth spacer, the sixth spacer including silicon nitride; and forming a second epitaxial source/drain region in the second fin and adjacent to the sixth spacer, wherein said first epitaxial source/drain region forms a component of a first transistor, said second epitaxial source/drain region forms a component of a second transistor, and wherein said first epitaxial source/drain The electrode region and the second epitaxial source/drain region have the same conductivity type. 19. The method of claim 18, wherein the second epitaxial source/drain region has a different volume than the first epitaxial source/drain region. 20. The method of claim 18, wherein the first fin comprises silicon germanium.

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