CN110970361A - Method for manufacturing chip package - Google Patents
Method for manufacturing chip package Download PDFInfo
- Publication number
- CN110970361A CN110970361A CN201811138435.7A CN201811138435A CN110970361A CN 110970361 A CN110970361 A CN 110970361A CN 201811138435 A CN201811138435 A CN 201811138435A CN 110970361 A CN110970361 A CN 110970361A
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- insulating layer
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- microns
- manufacturing
- chip package
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 68
- 239000002335 surface treatment layer Substances 0.000 claims abstract description 22
- 238000005520 cutting process Methods 0.000 claims abstract description 14
- 239000012790 adhesive layer Substances 0.000 claims description 13
- 238000004806 packaging method and process Methods 0.000 abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000866 electrolytic etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The invention relates to a manufacturing method of a chip packaging body. A wafer is provided, which has an upper surface and a lower surface opposite to the upper surface, and includes a plurality of conductive bumps on the upper surface. The upper surface of the wafer is cut to form a plurality of grooves. A first insulating layer is formed on the upper surface and in the groove, and the conductive bump is exposed. A surface treatment layer is formed on the conductive bump, and the top surface of the surface treatment layer is higher than the top surface of the first insulating layer. The wafer is thinned from the lower surface to the upper surface, so that the first insulating layer in the groove is exposed from the lower surface. A second insulating layer is formed below the lower surface. And cutting the first insulating layer and the second insulating layer along the center of each groove to form a plurality of chip packages. The method can avoid the problem of contraposition deviation.
Description
Technical Field
The invention relates to a manufacturing method of a chip packaging body.
Background
The conventional chip packaging process is to package the semiconductor dies cut from the wafer one by one, which is time-consuming and labor-consuming. Or, the semiconductor dies cut from the wafer are arranged on the carrier one by one for packaging and then cut into the chip packages again, and the manufacturing method of the chip packages is time-consuming and labor-consuming and is easy to cause the problem of alignment deviation.
Disclosure of Invention
The present invention is directed to overcome the defects of the conventional chip package process, i.e., the problems that the semiconductor dies cut from the wafer are packaged one by one, or the semiconductor dies cut from the wafer are arranged one by one on the carrier plate for packaging and then cut into the chip packages again, and alignment offset is easily generated, and a method for manufacturing a new chip package is provided, which can complete a plurality of chip packages, and avoid the generation of alignment offset, thereby being more practical.
The purpose of the invention and the technical problem to be solved are realized by adopting the following technical scheme.
The manufacturing method of the chip packaging body provided by the invention comprises the following steps: first, a wafer is provided, which has an upper surface and a lower surface opposite to the upper surface, and includes a plurality of conductive bumps on the upper surface. The upper surface of the wafer is cut to form a plurality of grooves. A first insulating layer is formed on the upper surface and in the groove, and the conductive bump is exposed. A surface treatment layer is formed on the conductive bump, and a top surface of the surface treatment layer is higher than a top surface of the first insulating layer. The wafer is thinned from the lower surface to the upper surface, so that the first insulating layer in the groove is exposed from the lower surface. A second insulating layer is formed below the lower surface. And cutting the first insulating layer and the second insulating layer along the center of each groove to form a plurality of chip packages.
The object of the present invention and the technical problems solved thereby can be further achieved by the following technical measures. In the method for manufacturing the chip package, the surface treatment layer has a height of 2 to 10 micrometers.
The method for manufacturing a chip package further includes, after the step of forming the first insulating layer and before the step of thinning the wafer: forming an adhesion layer to cover the first insulating layer and the surface treatment layer; and forming a carrier plate on the adhesion layer.
The method for manufacturing a chip package further includes, after the step of forming the second insulating layer and before the step of cutting the first insulating layer and the second insulating layer along the grooves: removing the carrier and the adhesive layer.
In the method for manufacturing the chip package, after the step of thinning the wafer, the wafer and the surface treatment layer have a first total thickness of 100 to 150 μm.
In the manufacturing method of the chip package, after the step of forming the second insulating layer, the wafer, the surface treatment layer and the second insulating layer have a second total thickness of 120 to 210 micrometers.
In the manufacturing method of the chip package, the cutting width for cutting the first insulating layer and the second insulating layer along the grooves is 15 to 22 micrometers.
In the manufacturing method of the chip package, each of the conductive bumps has a height of 20 to 45 μm.
In the manufacturing method of the chip package, each of the grooves has a width of 50 to 70 micrometers and a depth of 150 to 200 micrometers.
In the method for manufacturing the chip package, after the step of providing the wafer, the wafer has a thickness of 525 to 725 μm.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the manufacturing method of the chip packaging body can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
1. a plurality of chip packages can be completed without packaging semiconductor dies cut from a wafer one by one, reducing manufacturing time and cost.
2. The problem of alignment offset easily caused by arranging the semiconductor crystal grains cut from the wafer on the carrier plate one by one for packaging and then cutting the semiconductor crystal grains into chip packages is avoided. And reduces manufacturing time and costs.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a chip package according to the present invention.
Fig. 2A to 2F are schematic cross-sectional views of various processing stages of a method for manufacturing a chip package according to an embodiment of the invention.
Fig. 3A to 3C are schematic cross-sectional views of various processing stages of a method for manufacturing a chip package according to another embodiment of the invention.
[ notation ] to show
100: the method 20 comprises the following steps: wafer
20T: thickness 210: upper surface of
220: lower surface 230: conductive bump
230H, 230H: height 240: groove
240C: center 240D: depth of field
240W: width 250: a first insulating layer
250S: top surface 260: surface treatment layer
260H: height 260S: top surface
270: second insulating layer 310: adhesive layer
320: carrier plate CW: width of cut
Tf1: first total thickness Tf2: second total thickness
S110, S120, S130, S140, S150, S160, S170: step (ii) of
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the manufacturing method of the chip package, its structure, method, steps, features and effects will be made with reference to the accompanying drawings and preferred embodiments.
The foregoing and other technical and scientific aspects, features and advantages of the present invention will be apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and specific embodiments thereof. For convenience of description, in the following embodiments, the same elements are denoted by the same reference numerals.
Fig. 1 is a flow chart of a method for manufacturing a chip package according to the present invention. Fig. 2A to 2E are schematic cross-sectional views of various processing stages of a method for manufacturing a chip package according to an embodiment of the invention. As shown in fig. 1, the method 100 includes steps S110, S120, S130, S140, S150 and S160.
In step S110, a wafer 20 is provided, as shown in fig. 2A. Specifically, the wafer 20 has an upper surface 210 and a lower surface 220 opposite to the upper surface 210, and the wafer 20 includes a plurality of conductive bumps 230 on the upper surface 210. In an embodiment, the wafer 20 may include, but is not limited to, silicon (silicon), Germanium (Germanium), or a group III-V element. In various embodiments, the wafer 20 includes a plurality of conductive pads (not shown) on the top surface 210, and the conductive bumps 230 are disposed on the conductive pads. In some embodiments, wafer 20 has a thickness 20T of 525 to 725 microns, which may be 550 microns, 575 microns, 600 microns, 625 microns, 650 microns, 675 microns, or 700 microns, for example.
In an embodiment, the conductive bumps 230 each have a height 230H of 20 to 45 microns, such as may be 22 microns, 24 microns, 26 microns, 28 microns, 30 microns, 32 microns, 34 microns, 36 microns, 38 microns, 40 microns, or 42 microns. In various embodiments, a method of forming the conductive bump 230 includes the following steps, for example. First, a patterned mask (not shown) having a plurality of openings (not shown) is formed on the top surface 210 of the wafer 20, such that a portion of the top surface 210 of the wafer 20 is exposed through the openings. Thereafter, the conductive bump 230 is formed in the opening by an electroplating process. In some embodiments, the conductive bump 230 includes gold (gold), tin (tin), copper (copper), nickel (nickel), or other suitable metal material.
In step S120, the upper surface 210 of the wafer 20 is diced to form a plurality of grooves 240, as shown in fig. 2B. In various embodiments, this step S120 can be achieved using cutter wheel cutting, laser cutting, or water jet cutting. In an embodiment, each groove 240 has a width 240W of 50 to 70 microns and a depth 240D of 150 to 200 microns. For example, width 240W may be 52 microns, 54 microns, 56 microns, 58 microns, 60 microns, 62 microns, 64 microns, 66 microns, or 68 microns, and depth 240D may be 155 microns, 160 microns, 165 microns, 170 microns, 175 microns, 180 microns, 185 microns, 190 microns, or 195 microns, but is not limited thereto.
In step S130, a first insulating layer 250 is formed on the upper surface 210 and in the recess 240, and the conductive bump 230 is exposed, as shown in fig. 2C. In some embodiments, the material used for the first insulating layer 250 may be polyimide (polyimide), Epoxy (Epoxy), or other suitable insulating material. In an embodiment, the first insulating layer 250 may be formed by underfill (underfill). Alternatively, the grooves 240 may be filled by printing, coating or molding (molding) and fully cover the upper surface 210 of the wafer 20, and then the conductive bumps 230 are exposed by a planarization process, such as chemical mechanical polishing, mechanical brushing, planarization chemical etching, polishing process, electrolytic etching or electropolishing etching.
In step S140, a surface treatment layer 260 is formed on the conductive bump 230, and a top surface 260S of the surface treatment layer 260 is higher than a top surface 250S of the first insulating layer 250, as shown in fig. 2D. In some embodiments, the surface treatment layer 260 may be a single layer structure such as a nickel layer or a tin layer, or a multi-layer structure composed of sub-layers of different materials such as a nickel layer or a tin layer, but is not limited thereto. In many examples, the surface finish layer 260 has a height 260H of 2 to 10 microns, e.g., 3 microns, 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, or 9 microns. The surface treatment layer 260 may be formed by a physical method such as Nickel-gold electroplating and tin spraying, or a chemical method such as Nickel immersion gold (ENIG).
In step S150, the wafer 20 is thinned from the bottom surface 220 toward the top surface 210, so that the first insulating layer 250 in the groove 240 is exposed from the bottom surface 220, as shown in fig. 2E. The wafer 20 may be thinned by using a chemical-mechanical polishing (cmp) method, a dry etching method, or other suitable processing methods, so that the chip package formed finally has a smaller size. In some embodiments, after the step S150 of thinning the wafer 20, the wafer 20 and the surface treatment layer 260 have a first total thickness Tf1 of 100 to 150 microns, such as 110 microns, 115 microns, 120 microns, 125 microns, 130 microns, 135 microns, 140 microns, or 145 microns. After completing this step S150, the wafer 20 is separated into a plurality of chips, and the chips maintain the relative positions between the chips through the first insulating layer 250 in the grooves 240. Therefore, the problem of alignment offset in the prior art can be solved.
In step S160, a second insulating layer 270 is formed under the lower surface 220, as shown in fig. 2F. In various embodiments, the material of the second insulating layer 270 may be the same as or similar to the material of the first insulating layer 250. In some embodiments, the method of forming the second insulating layer 270 may be the same as the method of forming the first insulating layer 250. In the present embodiment, after the step S160 of forming the second insulating layer 270, the wafer 20, the surface treatment layer 260 and the second insulating layer 270 have a second total thickness Tf2 of 120 to 210 microns, such as 125 microns, 130 microns, 135 microns, 140 microns, 145 microns, 150 microns, 155 microns, 160 microns, 165 microns, 170 microns, 175 microns, 180 microns, 185 microns, 190 microns, 195 microns, 200 microns or 205 microns.
In some embodiments, after the step S160 of forming the second insulating layer 270, a Laser Mark (not shown) may be disposed on the second insulating layer 270 of each chip to Mark a product name of a subsequently formed chip package.
In step S170, the first and second insulating layers 250 and 270 are cut along the grooves 240 to form a plurality of chip packages, as shown in fig. 2F. In an embodiment, the first and second insulating layers 250 and 270 may be cut along the center 240C of each groove 240, for example, to form a plurality of chip packages. In various embodiments, this step S170 can be achieved using cutter wheel cutting, laser cutting, or water jet cutting. In the present embodiment, the cutting width CW for cutting the first insulating layer 250 and the second insulating layer 270 along each groove 240 is 15 to 22 micrometers, and may be, for example, 15.5 micrometers, 16.0 micrometers, 16.5 micrometers, 17.0 micrometers, 17.5 micrometers, 18.0 micrometers, 18.5 micrometers, 19.0 micrometers, 19.5 micrometers, 20.0 micrometers, 20.5 micrometers, 21.0 micrometers, or 21.5 micrometers.
In various examples, the chip package may be used to package a light sensing element or a light emitting element. However, the application is not limited thereto, and the invention can be applied to various electronic components (electronic components) including integrated circuits such as discrete devices, active or passive devices (active or passive devices), digital circuits or analog circuits (digital or analog circuits), for example, to opto-electronic devices (opto-electronic devices), Micro-Electro-Mechanical systems (Micro-Electro-Mechanical systems), and the like
Systems, MEMS), micro fluidic systems (micro fluidic systems), or Physical sensors (Physical sensors) that measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process may be used to package semiconductor chips such as image sensors, light-emitting diodes (LEDs) or diodes (diodes), solar cells (solar cells), radio frequency devices (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), micro actuators, surface acoustic wave devices (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (inkjet heads).
The following description is another embodiment of a method of manufacturing a chip package according to the present invention. Fig. 3A to 3D are schematic cross-sectional views of various stages of a method for manufacturing a chip package according to another embodiment of the invention. Referring to fig. 3A, after step S140 and before step S150, an adhesive layer 310 is formed to cover the first insulating layer 250 and the surface treatment layer 260, and then a carrier 320 is formed on the adhesive layer 310. The adhesive layer 310 can reduce the stress generated in the subsequent thinning process, thereby reducing the risk of wafer cracking. In an embodiment, the adhesive layer 310 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). In an embodiment, the adhesive layer 310 may be formed by spin coating (spin coating), but is not limited thereto. The carrier 320 may provide better protection for the wafer 20, and therefore, the carrier 320 may be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto.
Then, after the structure shown in fig. 3A is formed, step S150 and step S160 are continuously performed to obtain the structure shown in fig. 3B. The detailed description of step S150 and step S160 is not repeated herein. Then, referring to fig. 3C, after the step S160 of forming the second insulating layer 270, the carrier 320 and the adhesive layer 310 are removed. In detail, the adhesive layer 310 may be irradiated or heated by ultraviolet light, so that the carrier 320 may be peeled off together with the decrease of the viscosity of the adhesive layer 310. After the structure shown in fig. 3C is completed, step S170 is continuously performed to form a plurality of chip packages.
In summary, the method for manufacturing the chip package of the present invention can not only reduce the manufacturing time and cost, but also avoid the problem of misalignment. Other operable embodiments of the present invention may be modified within the skill of the art to which the invention pertains so long as the basic knowledge is available. In the present invention, a patent is claimed for the essential technical solution, and the protection scope of the patent should include all the changes with the technical characteristics.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811138435.7A CN110970361B (en) | 2018-09-28 | 2018-09-28 | Method for manufacturing chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811138435.7A CN110970361B (en) | 2018-09-28 | 2018-09-28 | Method for manufacturing chip package |
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| Publication Number | Publication Date |
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| CN110970361A true CN110970361A (en) | 2020-04-07 |
| CN110970361B CN110970361B (en) | 2021-11-16 |
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| CN201811138435.7A Active CN110970361B (en) | 2018-09-28 | 2018-09-28 | Method for manufacturing chip package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112490182A (en) * | 2020-11-25 | 2021-03-12 | 通富微电子股份有限公司 | Multi-chip packaging method |
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| US20170179076A1 (en) * | 2015-03-21 | 2017-06-22 | Nxp B.V. | Reduction of defects in wafer level chip scale package (wlcsp) devices |
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2018
- 2018-09-28 CN CN201811138435.7A patent/CN110970361B/en active Active
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| CN1993809A (en) * | 2004-08-03 | 2007-07-04 | 古河电气工业株式会社 | Method of producing a semiconductor device, and wafer-processing tape |
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| CN110970361B (en) | 2021-11-16 |
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