CN110968068A

CN110968068A - Controller function verification method and device and test equipment

Info

Publication number: CN110968068A
Application number: CN201811141074.1A
Authority: CN
Inventors: 尹夕振
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2020-04-07

Abstract

The invention provides a method and a device for verifying controller functions, a readable storage medium and electronic equipment, wherein the method comprises the following steps: establishing link connection between a verification model and a controller to be verified; generating a verification sequence when the verification model is determined to be in a running state based on the link connection; sending the verification sequence to the controller to be verified; receiving a feedback sequence generated by the controller to be verified based on the verification sequence; and analyzing the feedback sequence, and determining a verification result of the function of the controller to be verified according to an analysis result. The controller function verification method provided by the invention can effectively and comprehensively verify the function of the controller to be verified.

Description

Controller function verification method and device and test equipment

Technical Field

The invention belongs to the technical field of hardware testing, and particularly relates to a method and a device for verifying functions of a controller and testing equipment.

Background

Many external device controllers are often integrated on a System-on-a-chip (SOC), and before the SOC leaves a factory, functions of the integrated external device controllers need to be verified. When the device controller is subjected to function verification, the device controller needs to be docked with a device verification model adapted to the device controller, so that the device verification model is an indispensable part in the function verification.

The newly developed SPACE WIRE (space bus) controller has strong functions, but a verification model matched with the controller is not established for the controller of the model, so that the functions of the controller cannot be effectively verified.

Disclosure of Invention

The invention provides a method and a device for verifying controller functions and test equipment, and aims to solve the problem that SPACE WIRE controller functions cannot be effectively verified in the prior art.

In order to solve the above problems, the present invention discloses a method for verifying a function of a controller, wherein the method comprises: establishing link connection between a verification model and a controller to be verified; generating a verification sequence when the verification model is determined to be in a running state based on the link connection; sending the verification sequence to the controller to be verified; receiving a feedback sequence generated by the controller to be verified based on the verification sequence; and analyzing the feedback sequence, and determining a verification result of the function of the controller to be verified according to an analysis result.

In order to solve the above problem, the present invention also discloses a controller function verification apparatus, which includes: the establishing module is used for establishing link connection between the verification model and the controller to be verified; the sequence generation module is used for generating a verification sequence when the verification module is determined to be in the running state based on the link connection; the sending module is used for sending the verification sequence to the controller to be verified; the receiving module is used for receiving a feedback sequence generated by the controller to be verified based on the verification sequence; and the verification module is used for analyzing the sequence and determining a verification result of the function of the controller to be verified according to an analysis result.

In order to solve the above problems, the present invention further discloses a testing apparatus, wherein the testing apparatus comprises a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors to perform one or more controller function verification methods in the present invention.

Compared with the prior art, the invention has the following advantages:

according to the controller function verification method, the controller function verification device and the test equipment, link connection between a verification model and a controller to be verified is established; based on link connection, generating a verification sequence when the verification model is determined to be in a running state; sending the verification sequence to a controller to be verified; receiving a feedback sequence generated by a controller to be verified based on a verification sequence; and analyzing the feedback sequence, and determining a verification result of the function of the controller to be controlled according to an analysis result. According to the controller function verification method provided by the embodiment of the invention, the function of the controller to be verified is verified by establishing SPACE WIRE a verification model special for the controller and sending a verification sequence to the controller to be verified by the verification model, so that the function of the controller to be verified is effectively and comprehensively verified.

Drawings

Fig. 1 is a flowchart illustrating steps of a method for verifying functions of a controller according to a first embodiment of the present invention;

FIG. 2 is a flow chart illustrating steps of a method for verifying controller functions according to a second embodiment of the present invention;

FIG. 3 is a schematic diagram of a verification model state transition;

FIG. 4 is a receiving end sequence state transition diagram;

FIG. 5 is a transmit end sequence state transition diagram;

fig. 6 is a schematic structural diagram of a controller function verification apparatus according to a third embodiment of the present invention;

fig. 7 is a schematic structural diagram of a controller function verification apparatus according to a fourth embodiment of the present invention;

fig. 8 is a schematic structural diagram of a controller function verification apparatus according to a fifth embodiment of the present invention;

fig. 9 is a schematic structural diagram of a test apparatus according to a sixth embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Example one

Referring to fig. 1, a flowchart illustrating steps of a method for verifying a function of a controller according to a first embodiment of the present invention is shown.

The controller function verification method of the embodiment of the invention comprises the following steps:

step 101: and establishing link connection between the verification model and the controller to be verified.

In the embodiment of the invention, the verification model is pre-programmed computer code which can run in the test equipment and verify the function of the controller to be verified. Wherein, the controller to be verified is an SPACE WIRE controller.

Optionally, according to different code function modules included in the verification model, the verification model may be regarded as a model including a plurality of function units, for example, the verification model may include a driver unit, a monitor unit, a sequence control unit, a monitor unit, and the like, and an external interface for performing signal interaction with a controller to be verified and an internal interface for performing interaction between the function units in the verification model may also be simulated by the verification model. When the function of the controller to be verified is verified, information interaction is carried out among all functional units in the verification model and between the verification model and the controller to be verified so as to complete the verification of the function of the controller to be verified.

According to an alternative embodiment, in this step, a link connection between the verification model and the controller to be verified may be established through the driving unit in the verification model.

Step 102: and generating a verification sequence when the verification model is determined to be in the running state based on the link connection.

In the embodiment of the present invention, the verification sequence may include any one or any combination of the following sequences: EOP, EEP, ESC, FCT, DATA, Time _ code, the above-mentioned sequence is legal sequence too; in addition, the verification sequence may be an illegal sequence.

Specifically, the link state may be monitored by a monitor unit in the verification model, and the monitored information may be broadcast to each functional unit in the verification model through an internal interface, and a driver unit in the verification model may obtain the broadcast information, determine that the verification model is in an operating state, notify a sequence control unit in the verification model, and generate a verification sequence according to the operating state of the verification model by the sequence control unit.

Step 103: and sending the verification sequence to the controller to be verified.

In the embodiment of the invention, the verification sequence can be generated by a sequence control unit in the verification model; and the driver unit in the verification model sends the verification sequence generated by the sequence control unit to an external interface of the verification model, and the verification sequence is sent to the controller to be verified through the external interface.

Step 104: and receiving various feedback sequences generated by the controller to be verified based on the verification sequences.

In the embodiment of the invention, when the to-be-verified controller receives the verification sequence sent by the external interface of the verification model, the to-be-verified controller generates a corresponding feedback sequence and sends the feedback sequence to the external interface of the verification model.

Optionally, the verification model may monitor the external interface all the time through the monitor unit to obtain the feedback sequence generated by the controller to be verified.

Step 105: and analyzing the feedback sequence, and determining a verification result of the function of the controller to be verified according to an analysis result.

In the embodiment of the invention, the monitor unit in the verification model analyzes the acquired feedback sequence, and the verification result of the function of the controller to be verified is determined according to the analysis result and the standard verification sequence.

For example: when the verification sequence sent by the verification model is an FCT sequence, theoretically, a standard sequence list obtained after analysis of a feedback sequence returned by a controller to be verified is required to be 8 DATA sequences at most; based on the standard sequence list, if the analysis result obtained by the analysis is less than or equal to 8 DATA sequences, the verification result is that the controller to be verified is in a normal working state, and if the analysis result is greater than 8 DATA sequences (if 9 DATA sequences are included), the verification result is that the controller to be verified is in an error working state.

Optionally, the verification model may generate various different verification sequences, and different functions of the controller to be verified may be verified according to the different verification sequences.

The controller function verification method provided by the embodiment of the invention establishes link connection between a verification model and a controller to be verified; based on link connection, generating a verification sequence when the verification model is determined to be in a running state; sending the verification sequence to a controller to be verified; receiving a feedback sequence generated by a controller to be verified based on a verification sequence; and analyzing the feedback sequence, and determining a verification result of the function of the controller to be controlled according to an analysis result. According to the controller function verification method provided by the embodiment of the invention, the verification model is established, different verification sequences are sent to the controller to be verified by the verification model, and different functions of the controller to be verified are verified, so that the functions of the controller to be verified are effectively and comprehensively verified.

Example two

Referring to fig. 2, a flowchart illustrating steps of a method for verifying a function of a controller according to a second embodiment of the present invention is shown.

In the embodiment of the invention, the function of the controller is verified through the verification model. The verification model is provided with a plurality of functional units, such as a state control unit, a driver unit, a monitor unit, a sequence control unit, a monitor unit and the like, and is also provided with an external interface used for signal interaction with a controller to be verified and an internal interface used for interaction among the functional units in the verification model. The external interface is used for information interaction with the controller to be verified, and the internal interface is used for signal transmission among all functional units in the verification model.

Optionally, in order to satisfy SPACE WIRE the characteristics of the controller to be verified, the external interface of the verification model may include: tx _2clk port (system clock signal port), resetn port (system reset port), tx _ clk port (transmitting terminal clock signal port), rx _ clk port (transmitting terminal clock signal port), sin _ P port (P port of receiving terminal S), sin _ N port (N port of receiving terminal S), din _ P port (P port of receiving terminal D), din _ N port (N port of receiving terminal D), sout _ P port (P port of transmitting terminal S), sout _ N port (N port of transmitting terminal S), dout _ P port (P port of transmitting terminal S), and dout _ N port (N port of transmitting terminal S).

The external interfaces are used for receiving signals sent by the controller to be verified or sending corresponding signals to the controller to be verified; optionally, the external interface may process the following signals: the tx _2clk port is used to process the tx _2clk signal; the resetn port is used for processing a resetn signal, namely a system reset signal (reset signal for short); the tx _ clk port is used for processing a tx _ clk signal (a sending end clock signal), and the tx _ clk signal is obtained by performing exclusive or processing on a sout _ p signal and a dout _ p signal; the rx _ clk port is configured to process an rx _ clk signal (a receiving end clock signal), where the rx _ clk signal is an exclusive-or processed signal of a sin _ p signal and a din _ p signal; the sin _ P port is used for processing a sin _ P signal, namely a signal received by a P port of a receiving end S; the sin _ N port is used for processing a sin _ N signal, namely a signal received by the N end of the receiving end S; the din _ P port is used for processing din _ P signals, namely signals received by the P end of the receiving end D; the din _ N port is used for processing din _ N signals, namely signals received by the N end of the receiving end D; the sout _ P port is used for processing a sout _ P signal, namely a signal sent by the P end of the sending end S; the sout _ N port is used for processing a sout _ N signal, namely a signal sent by the N end of the sending end S; the dout _ P port is used for processing a dout _ P signal, namely a signal sent by the P end of the sending end D; and the dout _ N port is used for processing a dout _ N signal, namely a signal sent by the N end of the sending end D.

Optionally, verifying the signals transmitted by the internal interface in the model may include: tx _ rstn signal, i.e. a reset signal of a transmitting end, specifically including reset signals of a transmitting end S and a transmitting end D; the Rx _ rstn signal is a receiving end reset signal, which specifically includes reset signals of a receiving end S and a receiving end D; the GotNull signal represents the first NULL sequence signal received; the GotFct signal represents the first FCT sequence signal received; the Rx _ credit _ count signal represents a receiving-end residual space signal; the Tx _ credit _ count signal represents a transmit-end residual space signal; the Rx _ link _ err signal represents a receive link error flag signal; the Tx _ link _ err signal represents a transmit link error flag signal.

Based on the functional units, the internal interface, the external interface, and the signals transmitted by the internal interface and the external interface included in the verification model, the method for verifying the controller function of the embodiment of the invention specifically includes the following steps:

step 201: and resetting the verification model when a reset signal is received.

In the embodiment of the invention, resetting the verification model represents that all signals in the verification model are cleared; the reset signal is a system reset signal (i.e., resetn signal). Resetting the verification model includes sequentially transitioning the verification model to the following states: reset state → error waiting state → transmission ready state → transmission start state, and the relationship between the states is as shown in fig. 3. After the state conversion, the verification model enters a connection state, so that link connection between the verification model and the controller to be verified is established.

As shown in fig. 3, the state transition process of the verification model includes: when the rising edge of the reset signal resetn is detected, the reset state jumps to an error reset state; in an error resetting state, resetting all signals in the verification model, delaying for a first preset time, and then jumping to an error waiting state; in the error waiting state, setting a sending end reset signal Rx _ rstn to 1, enabling a receiving end, and determining that in the process of delaying the second preset time length, when the receiving link error mark signal is not detected to be 1 or the sending link error mark signal is 1, jumping from the error waiting state to a sending preparation state, wherein in the process of delaying the second preset time length, when the receiving link error mark signal is detected to be 1 or the sending link error mark signal is detected to be 1, jumping back to the error resetting state from the error waiting state; in a sending preparation state, if the receiving link error mark signal is not detected to be 1 or the sending link error mark signal is detected to be 1, jumping to a sending starting state, otherwise, returning to an error resetting state; starting from the time point of jumping to the sending starting state, in the process of delaying for a third preset time, if any one of the conditions that a receiving link error mark signal is 1, a sending link error mark signal is 1 and GotNULL is 0 is not detected, namely GotNULL is detected to be 1, jumping to the connection state from the sending starting state, otherwise, jumping back to the error reset state; and in the process of delaying the fourth preset time length from the time point of jumping to the connection state, if any one of the conditions that the receiving link error mark signal is 1, the sending link error mark signal is 1 and the GotFct is 0 is not detected, namely the GotFct is detected to be 1, jumping to the running state from the sending starting state, and otherwise, jumping to the error resetting state from the running state.

The first preset time is 6.4 microseconds (μ s), the second preset time is 12.8 microseconds, the third preset time is 12.8 microseconds, and the fourth preset time is 12.8 microseconds.

By adopting the technical scheme, various states are set in the verification model, when an error flag signal (rx _ link _ err is 1 or tx _ link _ err is 1) is detected, all signals in the verification model are cleared, the whole verification model is reset, the accuracy of each path of signals in the verification model is effectively ensured, and the accuracy of the function verification of the controller to be verified is ensured.

Step 202: and establishing link connection between the verification model and the controller to be verified through link connection sequence interaction between the verification model and the controller to be verified.

In the embodiment of the present invention, when the link connection between the verification model and the controller to be verified is established through the link connection sequence interaction between the verification model and the controller to be verified, the following method may be specifically used:

firstly, when a rising edge of a reset signal (namely a Tx _ rstn signal) at a sending end of a verification model is detected, a NULL sequence is sent to a controller to be verified in a circulating mode until a first NULL sequence fed back by the controller to be verified is received, and an FCT sequence or a NULL sequence can be sent to the controller to be verified; the sending end comprises a sending end S and a sending end D.

Secondly, acquiring a sending end residual space value of the verification model, and sending other legal sequences to the controller to be verified when the sending end residual space value is equal to a preset value; wherein the predetermined value is 56.

And finally, when the first FCT sequence fed back by the controller to be verified is received, determining that the link connection between the verification model and the controller to be verified is established.

By adopting the technical scheme, based on the information interaction between the controller to be verified and the verification model, the link connection between the verification model and the controller to be verified is reliably established through the appointed sequence, and the subsequent function verification process of the controller to be verified can be ensured.

In a specific implementation process, a link connection process may be described with reference to the receiving end sequence state transition diagram in fig. 4 and the transmitting end sequence state transition diagram in fig. 5.

As shown in fig. 4, after the verification model circularly sends a NULL sequence to the controller to be verified, the monitor unit in the verification model monitors whether the first sequence received by the receiving end is a non-NULL sequence in real time; if the first sequence is not a NULL sequence, setting the Rx _ link _ err signal to be high level, namely setting the Rx _ link _ err signal to be 1; when the receiving end is monitored to receive the first NULL sequence, setting the GotNull signal to be high level and jumping out of circulation; after the verification model sends the FCT sequence to the controller to be verified, the monitor unit may also monitor whether the receiving end receives the FCT sequence according to the clock cycle of the rx _ clk signal output by the rx _ clk port; in the monitoring process, if the sequence received by the receiving end is not an FCT or NULL sequence, an Rx _ link _ err signal is set to be at a high level; when the first FCT sequence received by the receiving end is monitored, the GotFct signal is set to be high level, the residual space indicated by the rx _ credit _ count signal is increased by eight bytes, and circulation is skipped. When the sequence received by the receiving end is monitored to be a NULL sequence, the sequence received by the receiving end is continuously monitored according to the cycle of the rx _ clk signal. When the Rx _ link _ err signal is 1, the state jumps back to the error reset state, that is, all signals in the verification model are cleared.

As shown in fig. 5, when a rising edge of a reset signal of a sender is detected, a monitor unit may monitor in real time whether the sender sends a NULL sequence to a controller to be verified in a cycle according to a clock period; if the first sequence sent by the sending end is monitored to be a non-NULL sequence, setting a Tx _ link _ err signal to be high level, and jumping out of circulation after the first NULL sequence sent by the sending end is monitored; moreover, when receiving a NULL sequence fed back by the controller to be verified, the monitor unit may also monitor whether the sequence sent by the sending end is an FCT sequence according to the rtx _ clk cycle, and set the Tx _ link _ err signal to a high level, that is, set the Tx _ link _ err signal to 1, if it is monitored that the sequence sent by the sending end is not the FCT or NULL sequence; when the first FCT sequence sent by the sending end is monitored, the residual space indicated by the Tx _ credit _ count signal is increased by eight bytes, and the loop is skipped. When the sequence sent by the sending terminal is a NULL sequence, continuing to monitor the sequence sent by the sending terminal according to the tx _ clk cycle; the sequence sent by the sending end comprises a NULL sequence, an FCT sequence, an EEP sequence, an EOP sequence, a TCODE sequence and a DATA sequence. When the Tx _ link _ err signal is 1, the error reset state is jumped back, that is, all signals in the verification model are cleared.

By adopting the technical scheme, the monitor unit monitors the sending terminal and the receiving terminal in real time, and once the fact that the sequence sent by the sending terminal is inconsistent with the pre-agreed sequence or the sequence received by the receiving terminal is inconsistent with the pre-agreed sequence is found, the monitor unit generates a link error mark signal to switch the state of the verification model to an error reset state, so that the accuracy of the working state of each interface and functional unit in the verification model is ensured, and the reliable establishment of the link connection between the verification model and the controller to be verified is further ensured.

Step 203: and generating a verification sequence when the verification model is determined to be in the running state based on the link connection.

In this embodiment of the present invention, the generated verification sequence may include: any one or any combination of EOP, EEP, ESC, FCT, DATA, and Time _ code.

Specifically, the monitor unit in the verification model monitors the link state and broadcasts the monitored information to each functional unit in the verification model through the internal interface, the driver unit obtains the broadcasted information, and when the verification model is determined to be in the running state, the driver unit informs the sequence control unit in the verification model, and various verification sequences are generated by the sequence control unit so as to meet the verification of various functions of the SPACE WIRE controller.

Step 204: and sending the verification sequence to the controller to be verified.

In the embodiment of the invention, a driver unit in a verification model sends a verification sequence to an external interface of the verification model, and the external interface sends the verification sequence to a controller to be verified; the monitor unit constantly monitors the external interface while the verification model sends a verification sequence to the controller to be verified.

Further, before the driver unit in the verification model transmits the verification sequence to the external interface, the driver unit calculates a parity (denoted as P) corresponding to the verification sequence transmitted this time based on the length of the verification sequence (denoted as tx _ length), the data included in the verification sequence (denoted as tx _ data), the length of the verification sequence transmitted last time (denoted as last _ tx _ length) closest to the current time, and the data included in the verification sequence transmitted last time (denoted as last _ tx _ data). The parity bit P may be sent to the controller to be verified together with the verification sequence, so that the controller to be verified verifies the authenticity of the sequence.

Optionally, the sending, by the driver unit in the verification model, the verification sequence to the external interface specifically includes: driving the value of tx _ data to the dout _ p port on the rising edge of the clock signal of the tx _2clk port, and driving one bit to the dout _ p port at a time; therefore, if the space occupied by the verification sequence to be sent is X bits, the verification sequence to be sent needs to be driven to the dout _ p port circularly for X times. Meanwhile, defining a global variable tx _ flag, negating the tx _ flag after the drive ends the value of the dout _ p port, and acquiring an exclusive or result of the negated value of the tx _ flag and the tx _ data; and driving the xor result to the sout _ p port. The end of value drive for the dout _ p port means that the tx _ data values are all driven to the dout _ p port. Wherein the initial value of tx _ flag is set to 0.

After the tx _ data value driving corresponding to the verification sequence is completed, optionally, the driver unit controls each verification sequence, and the specific control manner is as follows: and writing a sending task according to the sequence priority of the Time _ Code, the FCT, the N _ chars and the NULL.

Further, the driver unit in the verification model sending the verification sequence to the external interface further comprises: when the Tx _ credit _ count value is larger than 0, sending an FCT sequence to an external interface; when the Rx _ credit _ count value is larger than 0, any one or any combination of DATA, EOP and EEP is used as a verification sequence to be sent to an external interface; in addition to the two cases described above, NULL is sent to the external interface as a verification sequence to ensure the connectivity of the link.

Further, a Tx _ data register is set in the verification model; in the verification model running stage, the monitor unit in the verification model can monitor the state of the transmission port of the verification model by the following modes: waiting for four jumping edges output by a Tx _ clk port, simultaneously storing data output by a dout _ p port into a Tx _ data register with the bit width of 10, wherein the received data exist in the high order of the register; inquiring whether an ESC sequence is stored in six to eight bits of a Tx _ data register; if the ESC sequence is stored in six to eight bits of the Tx _ data register, continuously waiting for the Tx _ clk port to output four jumping edges, sequentially storing the data output by the dout _ p port into the Tx _ data register, inquiring whether the data stored in the Tx _ data register is an FCT sequence, and if so, determining that a NULL sequence is detected; if the sequence is not the FCT sequence, continuously waiting for six transition edges of the tx _ clk port to detect the Time _ Code sequence; if the six to eight bits of the Tx _ data register do not store the ESC sequence, checking whether the eighth bit of the Tx _ data register is 1, and the eighth bit of the Tx _ data register is 1, which indicates that the FCT sequence, the EEP sequence, or the EOP sequence is detected.

Further, if the FCT sequence is detected, the remaining space indicated by Tx _ credit _ count is increased by eight bytes; if an EEP sequence or an EOP sequence is detected, the remaining space indicated by Tx _ credit _ count is reduced by one byte. If the eighth bit of the Tx _ DATA register is 0, indicating that a DATA sequence is detected, then four transition edges of the Tx _ clk interface are waited for again. The parity bit is checked after a sequence check is completed, and the Tx _ link _ err needs to be set to 1 if the check is unsuccessful or the control bit is erroneous.

Step 205: and receiving a feedback sequence generated by the controller to be verified based on the verification sequence.

In the embodiment of the invention, the controller to be verified sends the feedback sequence generated based on the verification sequence to the verification model through the external interface of the verification model.

Optionally, an Rx _ data register is set in the verification model; a monitor unit in the verification model monitors a receiving end in an external interface of the verification model in real time, waits for four jumping edges of an Rx _ clk port, and simultaneously stores data transmitted by a din _ p port into an Rx _ data register with the bit width of 10; inquiring whether an ESC sequence is stored in six to eight bits of an Rx _ data register;

if the ESC sequence is stored in six to eight bits of the Rx _ data register, continuously waiting for the Rx _ clk port to output four jumping edges, sequentially storing data transmitted by the din _ p port into the Rx _ data register, and inquiring whether two to four bits of the Rx _ data register store the FCT sequence or not; if two to four bits of the Rx _ data register store the FCT sequence, determining that a NULL sequence is received; if two to four bits of the Rx _ data register do not store the FCT sequence, six transition edges of the Rx _ clk interface are waited for to detect the Time _ Code sequence.

If the ESC sequence is not stored in six to eight bits of the Rx _ data register, inquiring whether the eighth bit of the Rx _ data register is 1; if the number is 1, determining that an FCT sequence, an EEP sequence or an EOP sequence is received; if the FCT sequence is determined to be received, increasing the residual space indicated by the Rx _ credit _ count signal by eight bits; if it is determined that the EEP sequence or the EOP sequence is received, the remaining space indicated by the Rx _ credit _ count signal is reduced by one byte.

Step 206: and analyzing the feedback sequence, and determining a verification result of the function of the controller to be verified according to the analysis result.

One way to determine the result of the verification of the controller function to be verified, preferably from the parsed result, is as follows:

when the verification sequence is a legal sequence, acquiring a standard sequence list corresponding to the verification sequence; searching whether a sequence matched with the analysis result exists in the standard sequence list, if so, determining that the controller to be verified is in a normal working state, otherwise, determining that the controller to be verified is in an error working state;

when the verification sequence is an illegal sequence, judging whether the verification result is information indicating that the verification sequence is the illegal sequence; if so, the verification result is that the controller to be verified is in a normal working state, and if not, the verification result is that the controller to be verified is in an error working state.

For example, when the sequence sent by the verification model is the FCT sequence, theoretically, the controller to be verified feeds back 8 DATA at most; if the number of the DATA sequences is less than 8, the verification result is that the controller to be verified is in a normal working state, and if the analysis result is greater than 8 DATA (if 9 DATA are contained), the verification result is that the controller to be verified is in an error working state.

In each step, the sequence sent by the controller to be verified can be monitored in real time through the monitor unit; generating a control signal according to a sequence sent by a controller to be verified; and when the generated control signal is an error flag signal, performing zero clearing treatment on all signals in the verification model, and disconnecting the link connection between the verification model and the controller to be verified.

Further, in each step, once the error flag signal is detected, all signals in the verification model are immediately cleared, and the link connection between the verification model and the controller to be verified is disconnected. Wherein the error flag signal includes: rx _ link _ err is 1, and tx _ link _ err is 1. For example: in the process of establishing link connection, when a first sequence received by a receiving end is not a NULL sequence, setting rx _ link _ err to 1; in the link connection establishing process, when the sequence received by the receiving end is monitored not to be the FCT sequence, setting rx _ link _ err to 1; in the link connection establishing process, when the first sequence sent by the sending end is monitored to be not a NULL sequence, setting rx _ link _ err and tx _ link _ err to be 1.

According to the controller function verification method provided by the embodiment of the invention, different functions of the controller to be verified are verified by sending different verification sequences to the controller to be verified, so that the functions of the controller to be verified are effectively and comprehensively verified. In addition, in the controller function verification method provided in the embodiment of the present invention, after the link between the verification model and the controller to be verified is established, whether the established link connection meets the disconnection condition is further determined based on a control signal generated by a sequence sent by the controller to be verified, so that the link connection is disconnected in time.

EXAMPLE III

Referring to fig. 6, a schematic structural diagram of a controller function verification apparatus according to a third embodiment of the present invention is shown.

As shown in fig. 6, the SPACE WIRE controller function verification model of the embodiment of the invention includes: an interface unit 301, a state control unit 302, a sequence control unit 303, a driver unit 304, and a monitor unit 305.

The interface unit 301 includes an external interface for connecting to a controller to be verified, and an internal interface for transmitting signals between units in the controller function verification apparatus. The controller to be verified is hereinafter described as the controller to be verified.

The external interface may include: tx _2clk port (system clock signal port), resetn port (system reset port), tx _ clk port (transmitting terminal clock signal port), rx _ clk port (transmitting terminal clock signal port), sin _ P port (P port of receiving terminal S), sin _ N port (N port of receiving terminal S), din _ P port (P port of receiving terminal D), din _ N port (N port of receiving terminal D), sout _ P port (P port of transmitting terminal S), sout _ N port (N port of transmitting terminal S), dout _ P port (P port of transmitting terminal S), and dout _ N port (N port of transmitting terminal S).

The signals passed by the internal interface may include: tx _ rstn signal, i.e. a reset signal of a transmitting end, specifically including reset signals of a transmitting end S and a transmitting end D; the Rx _ rstn signal is a receiving end reset signal, which specifically includes reset signals of a receiving end S and a receiving end D; the GotNull signal represents the first NULL sequence signal received; the GotFct signal represents the first FCT sequence signal received; the Rx _ credit _ count signal represents a receiving-end residual space signal; the Tx _ credit _ count signal represents a transmit-end residual space signal; the Rx _ link _ err signal represents a receive link error flag signal; the Tx _ link _ err signal represents a transmit link error flag signal.

The driver unit 304 includes a link establishing module 3041, configured to establish a link connection between the controller function verifying apparatus and the controller to be verified.

A state control unit 302, configured to detect and control the established link state.

Specifically, the link state may include the following states: the reset state, error wait state, transmission preparation state, transmission start state, connection state, and operation state, specifically, transition between the respective states is as shown in fig. 3.

The state control unit 302 includes: a first control module 3021, a second control module 3022, a third control module 3023, a fourth control module 3024, a fifth control module 3025, a sixth control module 3026, and a seventh control module 3027. The link state switching performed by each control module is described below with reference to fig. 4.

A first control module 3021, configured to switch the link state to an error reset state when a high-level resetn signal, i.e., a rising edge of the resetn signal, is received while the link is in the reset state.

The second control module 3022 is configured to switch the link state to the error waiting state after delaying a first preset duration when the link is in the error reset state.

In the error reset state, all signals in the inter _ if are cleared to 0, and the first preset time period may be set to 6.4 microseconds.

A third control module 3023, configured to set the Rx _ rstn signal to a high level, that is, set the Rx _ rstn signal to 1, enable the receiving end to delay for a second preset time period, and determine whether the high level Rx _ link _ err signal or the high level Tx _ link _ err signal is detected in the delay process, that is, the Rx _ link _ err signal or the Tx _ link _ err signal is 1; if so, switching the link state to an error reset state; if not, the link state is switched to a sending preparation state.

Wherein the second preset time period may be set to 12.8 microseconds.

The fourth control module 3024 is configured to determine whether a high-level Rx _ link _ err signal or a Tx _ link _ err signal is received when the link is in a ready-to-send state, where the Rx _ link _ err signal or the Tx _ link _ err signal is 1; and if the link state is not the error reset state, switching the link state to a sending starting state when the link enabling signal is valid.

A fifth control module 3025, configured to delay a third preset time duration when the link is in the transmission start state, and switch the link state to the error reset state when detecting that an Rx _ link _ err signal of a high level, a Tx _ link _ err signal of a Tx _ link _ err signal or a GotNull signal of a low level, that is, the Rx _ link _ err signal or the Tx _ link _ err signal is 1, or the GotNull signal is 0 in the delay process; when detecting that the high-level GotNull signal, i.e. the GotNull signal, is 1, the link state is switched to the connection state.

A sixth control module 3026, configured to delay for a fourth preset time period when the link is in the connection state, and switch the link state to the error reset state when detecting that the Rx _ link _ err signal is at a high level, the Tx _ link _ err signal is at a high level, or the GotFot signal is at a low level in the delay process, that is, when the Rx _ link _ err signal is 1 or the Tx _ link _ err signal is 1 or the GotFot signal is 0; when a high-level GotFot signal, namely the GotFot signal is detected to be 1, the link state is switched to the running state.

And the third preset time length and the fourth preset time length can be set to be 12.8 microseconds.

A seventh control module 3027, configured to switch the link state to an error reset state when the high Rx _ link _ err signal, the high Tx _ link _ err signal, or the link enable interrupt is detected while the link is in the operating state.

A sequence control unit 303, configured to control the driver unit 302 to transmit a sequence according to a control signal transmitted by a preset internal interface. The sequence mentioned later in the examples of the present invention is the verification sequence.

The sequence control unit 303 controls transmission of a sequence by the driver unit 304, including: the driver unit 304 is controlled to transmit sequences such as EOP, EEP, ESC, FCT, DATA, Time _ Code, etc. and combinations of the sequences according to different encoding modes, so as to meet the requirements of various controller function verifications. The driver unit 304 transmits the corresponding sequence according to a predetermined internal interface, such as Rx _ credit _ count, Tx _ credit _ count, and sequence, i.e., a control signal provided by a timer. The driver unit 304 determines a sequence to be transmitted according to control signals sent by preset internal interfaces, such as Rx _ credit _ count, Tx _ credit _ count, and sequence, and sends each sequence to be transmitted to a sending end in the external interface according to the established link.

Specifically, the driver unit 304 may further include: a sequence control module 3042, configured to sort the sequences to be sent according to the priority, and send the sequences according to the order;

specifically, the sequence control module 3042 writes a transmission task according to the sequence priority of Time _ Code, FCT, N _ chars, and NULL, and transmits FCT if the value of Tx _ credit _ count is greater than 0, that is, the remaining space of the transmitting end is greater than 0; if the value of Tx _ credit _ count is not more than 0, namely the residual space of the sending end is less than 0, and the value of Rx _ credit _ count is more than 0, sending three sequences of DATA, EOP and EEP; if the value of Tx _ credit _ count is not greater than 0, nor is the value of Rx _ credit _ count greater than 0, i.e. the receiving end residual space is greater than 0, NULL is sent to maintain the link connectivity. The transmission of each sequence is performed by the sequence transmission module 3043.

The sequence sending module 3043 drives the value of tx _ data to the dout _ p port on the rising clock edge of the tx _ clk port, one bit at a time; therefore, if the sequence to be transmitted contains X bits, it is necessary to drive the sequence to be transmitted to the dout _ p port cyclically X times. And defining a global variable tx _ flag in the system, wherein the initial value of the global variable is 0, negating the tx _ flag after the value of the dout _ p port is driven, and driving the value of tx _ data exclusive or the tx _ flag to the sout _ p port. Since the tx _ data value is driven to the dout _ p port one bit at a time, the value of the dout _ p port being driven off means that the tx _ data value is driven off.

Preferably, the sequence transmitting module 3043 may also generate parity bits for a sequence when transmitting the sequence for a data receiving side to verify the authenticity of the sequence. Specifically, for a current sequence to be transmitted, a parity bit is generated according to the length of the current sequence to be transmitted, the data of the current sequence to be transmitted, the length of a previous transmission sequence, and the data of the previous transmission sequence, and the parity bit is carried in the data of the current sequence to be transmitted for transmission. That is, the parity P to be checked is calculated according to the length tx _ length of the current sequence, the data tx _ data of the current sequence to be transmitted, the length last _ tx _ length of the last transmitted sequence, and the data last _ tx _ data value of the last transmitted sequence.

The controller function verification apparatus provided in the embodiment of the present invention further includes a monitor unit 305, configured to implement functions of receiving end connection state sequence collection, receiving end operation state sequence collection, sending end connection state sequence collection, and sending end operation state sequence collection.

Specifically, the monitor unit 305 includes: a receiving end connection state sequence collection module 3051, a receiving end running state sequence collection module 3052, a transmitting end connection state sequence collection module 3053 and a transmitting end running state sequence collection module 3054, wherein the specific working principle of each module is as follows.

The receiving end connection state sequence collection module 3051, configured to check a NULL sequence along a cycle according to a transition of an Rx _ clk signal output by an Rx _ clk port, where the Rx _ clk signal has a rising edge and a falling edge, in this embodiment, the NULL sequence is checked when the Rx _ clk signal transitions, if a first detected sequence is not a NULL sequence, setting an Rx _ link _ err signal to a high level, and setting a GotNull signal to a high level and skipping out of the cycle after detecting the first NULL sequence; checking an FCT sequence according to the cycle of an Rx _ clk signal output by an Rx _ clk port, and setting an Rx _ link _ err signal to be high level, namely setting the Rx _ link _ err signal to be 1, if the received sequence is not an FCT or NULL sequence in the detection process; when the first FCT sequence is checked, the GotFct signal is set to be high level, the residual space indicated by the rx _ credit _ count signal is increased by eight bytes, and the loop is skipped.

The receiving end running state sequence collection module 3052 is configured to wait for the Rx _ clk port to output four transition edges, and store data output by the din _ p port in an Rx _ data register with a bit width of 10; inquiring whether an ESC sequence is stored in six to eight bits of an Rx _ data register;

if yes, continuing to wait for the Rx _ clk port to output four jumping edges, sequentially storing data output by the din _ p port into an Rx _ data register, and inquiring whether two to four bits of the Rx _ data register store an FCT sequence or not; if two to four bits of the Rx _ data register store the FCT sequence, determining that a NULL sequence is received; if the two to four bits of the Rx _ data register do not store the FCT sequence, waiting for the Rx _ clk interface to output six jump edges to detect the Time _ Code sequence;

if not, inquiring whether the eighth bit of the Rx _ data register is 1, and if so, determining to receive an FCT sequence, an EEP sequence or an EOP sequence; if the FCT sequence is determined to be received, increasing the residual space indicated by the Rx _ credit _ count signal by eight bits; if it is determined that the EEP sequence or the EOP sequence is received, the remaining space indicated by the Rx _ credit _ count signal is reduced by one byte.

The transmitting end connection state sequence collection module 3053 is configured to check a NULL sequence according to a cycle of an rx _ clk signal output by an rx _ clk port, set a Tx _ link _ err signal to a high level if a first detected sequence is not a NULL sequence, and jump out of a cycle after the first detected sequence is a NULL sequence; checking an FCT sequence according to a cycle of an rx _ clk signal output by an rx _ clk port, and setting a Tx _ link _ err signal to be high level, namely setting the Tx _ link _ err signal to be 1, if the received sequence is not an FCT or NULL sequence in the detection process; when the remaining space indicated by the Tx _ credit _ count signal after checking the first FCT sequence is increased by eight bytes, the loop is skipped.

The transmitting end running state sequence collecting module 3054 is configured to wait for the Tx _ clk port to output four transition edges, store data output by the dout _ p port in a Tx _ data register with a bit width of 10, and store the received data in a high bit of the register; inquiring whether an ESC sequence is stored in six to eight bits of a Tx _ data register;

if an ESC sequence is stored in six to eight bits of the Tx _ data register, continuously waiting for the Tx _ clk port to output four jumping edges, sequentially storing data output by the dout _ p port into the Tx _ data register, inquiring whether the data stored in the Tx _ data register is FCT or not, and if so, determining that a NULL sequence is detected; if not, continuously waiting for the tx _ clk port to output six jumping edges, and detecting a Time _ Code sequence;

if the ESC sequence is not stored in the six-eight bits of the Tx _ data register, checking whether the eighth bit of the Tx _ data is 1; the eighth bit of Tx _ data is 1, which indicates that FCT or EEP or EOP is detected; specifically, if the FCT is detected, the remaining space indicated by Tx _ credit _ count is increased by eight bytes, and if the EEP or EOP is detected, the remaining space indicated by Tx _ credit _ count is decreased by one byte. An eighth bit of 0 for Tx _ DATA indicates that a DATA sequence is detected, and then waits for the Tx _ clk interface to output four transition edges. After a sequence is detected, the parity check bit and the control bit are checked, and if the check is unsuccessful or the control bit is in error, the Tx _ link _ err needs to be set to 1.

The controller function verification device provided by the embodiment of the invention comprises an interface unit, a state control unit, a sequence control unit, a driver unit and a monitor unit; the verification device can be connected with a controller to be verified through the interface unit, link connection between the verification device and the controller can be established through the driver unit, the sequence control unit can adjust the sending rule of the sequence based on different test requirements, and controls the driver unit to send the sequence according to the adjusted sequence sending rule. According to the controller function verification device provided by the invention, the sequence control unit can adjust the sending rule of the sequence according to the function adaptability of the controller to be tested, so that the different functions of the controller to be verified can be tested.

Example four

Referring to fig. 7, a schematic structural diagram of a controller function verification apparatus according to a fourth embodiment of the present invention is shown.

The controller function verification device of the embodiment of the invention comprises: an establishing module 701, configured to establish a link connection between a verification model and a controller to be verified; a sequence generating module 702, configured to generate a verification sequence when determining that the verification module is in an operating state based on the link connection; a sending module 703, configured to send the verification sequence to the controller to be verified; a receiving module 704, configured to receive a feedback sequence generated by the controller to be verified based on the verification sequence; the verification module 705 is configured to parse the sequence, and determine a verification result of the function of the controller to be verified according to a parsing result.

The controller function verification device provided by the embodiment of the invention establishes link connection between a verification model and a controller to be verified; based on link connection, generating a verification sequence when the verification model is determined to be in a running state; sending the verification sequence to a controller to be verified; receiving a feedback sequence generated by a controller to be verified based on a verification sequence; and analyzing the feedback sequence, and determining a verification result of the function of the controller to be controlled according to an analysis result. The controller function verification device provided by the embodiment of the invention verifies different functions of the controller to be verified by establishing the verification model and sending different verification sequences to the controller to be verified by the verification model, thereby effectively and comprehensively verifying the functions of the controller to be verified.

EXAMPLE five

Referring to fig. 8, a schematic structural diagram of a controller function verification apparatus according to a fifth embodiment of the present invention is shown.

The controller function verification device of the embodiment of the invention comprises: an establishing module 801, configured to establish a link connection between a verification model and a controller to be verified; a sequence generating module 802, configured to generate a verification sequence when determining that the verification module is in an operating state based on the link connection; a sending module 803, configured to send the verification sequence to the controller to be verified; a receiving module 804, configured to receive a feedback sequence generated by the controller to be verified based on the verification sequence; the verification module 805 is configured to analyze the sequence, and determine a verification result of the function of the controller to be verified according to an analysis result.

Preferably, the establishing module 801 comprises: a reset submodule 8011 configured to reset the verification model when a reset signal is received; a establishing sub-module 8012, configured to establish a link connection between the verification model and the controller to be verified through a link connection sequence interaction between the verification model and the controller to be verified.

Preferably, the establishing sub-module 8012 is specifically configured to: when a rising edge of a reset signal of a sending end is received, a NULL sequence is sent to the controller to be verified in a circulating mode, and when a first NULL sequence fed back by the controller to be verified is received, an FCT sequence or the NULL sequence is sent to the controller to be verified; acquiring a residual space value of a sending end, and sending other legal sequences to the controller to be verified when the residual space value of the sending end is equal to a preset value; and when receiving a first FCT sequence fed back by the controller to be verified, determining that the link connection between the verification model and the controller to be verified is established.

Preferably, the verification module 805 comprises: an analysis submodule 8051, configured to analyze the feedback sequence; a first verification sub-module 8052, configured to, when the verification sequence is a legal sequence, obtain a sequence list corresponding to the verification sequence; searching whether a sequence matched with the analysis result exists in the sequence list, if so, determining that the controller to be verified is in a normal working state, otherwise, determining that the controller to be verified is in an error working state; a second verification sub-module 8053, configured to, when the verification sequence is an illegal sequence, determine whether the verification result is information indicating that the verification sequence is an illegal sequence; if so, the verification result is that the controller to be verified is in a normal working state, and if not, the verification result is that the controller to be verified is in an error working state.

Preferably, the apparatus further comprises: a monitoring module 806, configured to monitor, in real time, a sequence sent by the controller to be verified; a control signal generating module 807, configured to generate a control signal according to the sequence sent by the controller to be verified; and the link control module 808 is configured to perform zero clearing processing on all signals in the verification model and disconnect a link connection between the verification model and the controller to be verified when the generated control signal is an error flag signal.

The controller function verification device in the embodiment of the present invention is used to implement the corresponding controller function verification device method in the foregoing method embodiment, and has the beneficial effects of corresponding method implementation, which are not described herein again.

EXAMPLE six

Referring to fig. 9, a schematic structural diagram of a test device for verifying a controller function according to a fifth embodiment of the present invention is shown.

Referring to fig. 9, the test equipment may include one or more of the following components: processing component 902, memory 904, power component 906, multimedia component 908, audio component 910, input/output (I/O) interface 912, sensor component 914, and communication component 916.

Processing group 902 generally controls the overall operation of the test equipment, such as operations associated with display, data communication, camera operations, and recording operations. Processing element 902 may include one or more processors 920 to execute instructions to perform all or a portion of the steps of the methods described above. Further, processing component 902 can include one or more modules that facilitate interaction between processing component 902 and other components. For example, the processing component 902 can include a multimedia module to facilitate interaction between the multimedia component 908 and the processing component 902.

The storage 904 is configured to store various types of data to support operations at the electronic device. Examples of such data include instructions for any application or method operating on the electronic device, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 904 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

The power supply component 906 provides power to the various components of the test equipment. The power components 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the test device.

The multimedia component 908 includes a screen that provides an output interface between the test equipment and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 908 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the test device is in an operational mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 910 is configured to output and/or input audio signals. For example, the audio component 910 includes a Microphone (MIC) configured to receive external audio signals when the test device is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 904 or transmitted via the communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

I/O interface 912 provides an interface between processing component 902 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

The sensor assembly 914 includes one or more sensors for providing status assessment of various aspects of the test equipment. For example, the sensor component 914 may detect an open/closed state of the testing device, the relative positioning of components, such as a display and keypad of the testing device, the sensor component 914 may also detect a change in position of the testing device or a component of the testing device, the presence or absence of user contact with the testing device, orientation or acceleration/deceleration of the testing device, and a change in temperature of the testing device. The sensor assembly 914 may include a proximity sensor configured to detect the presence of a nearby object in the absence of any physical contact. The sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 914 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 916 is configured to facilitate wired or wireless communication between the test device and other devices. The test device may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast associated information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communications component 916 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the test device may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described controller function verification methods. The controller function verification method comprises the following steps:

establishing link connection between a verification model and a controller to be verified; generating a verification sequence when the verification model is determined to be in a running state based on the link connection; sending the verification sequence to the controller to be verified; receiving a feedback sequence generated by the controller to be verified based on the verification sequence; and analyzing the feedback sequence, and determining a verification result of the function of the controller to be verified according to an analysis result.

Preferably, the step of establishing a link connection between the verification model and the controller to be verified includes: resetting the verification model when a reset signal is received; and establishing link connection between the verification model and the controller to be verified through link connection sequence interaction between the verification model and the controller to be verified.

Preferably, the step of establishing a link connection between the verification model and the controller to be verified through a link connection sequence interaction between the verification model and the controller to be verified includes: when the rising edge of a reset signal of a sending end is detected, a NULL sequence is sent to the controller to be verified in a circulating mode, and an FCT sequence or the NULL sequence is sent to the controller to be verified until a first NULL sequence fed back by the controller to be verified is received; acquiring a residual space value of a sending end, and sending other legal sequences to the controller to be verified when the residual space value of the sending end is equal to a preset value; and when receiving a first FCT sequence fed back by the controller to be verified, determining that the link connection between the verification model and the controller to be verified is established.

Preferably, the step of determining a verification result of the controller function to be verified according to the parsing result includes: when the verification sequence is a legal sequence, acquiring a standard sequence list corresponding to the verification sequence; searching whether a sequence matched with the analysis result exists in the standard sequence list, if so, determining that the controller to be verified is in a normal working state, otherwise, determining that the controller to be verified is in an error working state; when the verification sequence is an illegal sequence, judging whether the verification result is information indicating that the verification sequence is the illegal sequence; if so, the verification result is that the controller to be verified is in a normal working state, and if not, the verification result is that the controller to be verified is in an error working state.

Preferably, the method further comprises: monitoring a sequence sent by the controller to be verified in real time; generating a control signal according to the sequence sent by the controller to be verified; and when the generated control signal is an error flag signal, performing zero clearing processing on all signals in the verification model, and disconnecting a link between the verification model and the controller to be verified.

In an exemplary embodiment, a non-transitory computer readable storage medium comprising instructions, such as the memory 604 comprising instructions, executable by the processor 620 of the electronic device to perform the above-described dynamic compilation method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

A non-transitory computer readable storage medium having instructions therein which, when executed by a processor of a test device, enable the test device to perform any of the controller function verification methods shown in the above embodiments.

The test equipment of the embodiment of the invention is used for realizing the corresponding controller function verification method in the plurality of method embodiments, and has the beneficial effects of corresponding method implementation, which are not described herein again.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The method, the device and the test equipment for verifying the function of the controller provided by the invention are described in detail, a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A method for verifying controller functionality, comprising:

establishing link connection between a verification model and a controller to be verified;

generating a verification sequence when the verification model is determined to be in a running state based on the link connection;

sending the verification sequence to the controller to be verified;

receiving a feedback sequence generated by the controller to be verified based on the verification sequence;

and analyzing the feedback sequence, and determining a verification result of the function of the controller to be verified according to an analysis result.

2. The method of claim 1, wherein the step of establishing a link connection between the authentication model and the controller to be authenticated comprises:

resetting the verification model when a reset signal is received;

and establishing link connection between the verification model and the controller to be verified through link connection sequence interaction between the verification model and the controller to be verified.

3. The method according to claim 2, wherein the step of establishing the link connection between the verification model and the controller to be verified through the link connection sequence interaction between the verification model and the controller to be verified comprises:

when the rising edge of a reset signal of a sending end is detected, a NULL sequence is sent to the controller to be verified in a circulating mode, and an FCT sequence or the NULL sequence is sent to the controller to be verified until a first NULL sequence fed back by the controller to be verified is received;

acquiring a residual space value of a sending end, and sending other legal sequences to the controller to be verified when the residual space value of the sending end is equal to a preset value;

and when receiving a first FCT sequence fed back by the controller to be verified, determining that the link connection between the verification model and the controller to be verified is established.

4. The method according to claim 1, wherein the step of determining the result of the verification of the controller function to be verified according to the parsed result comprises:

5. The method according to any one of claims 1 to 4, further comprising:

monitoring a sequence sent by the controller to be verified in real time;

generating a control signal according to the sequence sent by the controller to be verified;

and when the generated control signal is an error flag signal, performing zero clearing processing on all signals in the verification model, and disconnecting a link between the verification model and the controller to be verified.

6. A controller function verification apparatus, comprising:

the establishing module is used for establishing link connection between the verification model and the controller to be verified;

the sequence generation module is used for generating a verification sequence when the verification module is determined to be in the running state based on the link connection;

the sending module is used for sending the verification sequence to the controller to be verified;

the receiving module is used for receiving a feedback sequence generated by the controller to be verified based on the verification sequence;

and the verification module is used for analyzing the sequence and determining a verification result of the function of the controller to be verified according to an analysis result.

7. The apparatus of claim 6, wherein the establishing module comprises:

the reset submodule is used for resetting the verification model when a reset signal is received;

and the establishing submodule is used for establishing link connection between the verification model and the controller to be verified through link connection sequence interaction between the verification model and the controller to be verified.

8. The apparatus of claim 7, wherein the setup submodule is specifically configured to:

9. The apparatus of claim 6, wherein the verification module comprises:

the analysis submodule is used for analyzing the feedback sequence;

the first verification submodule is used for acquiring a standard sequence list corresponding to the verification sequence when the verification sequence is a legal sequence; searching whether a sequence matched with the analysis result exists in the standard sequence list, if so, determining that the controller to be verified is in a normal working state, otherwise, determining that the controller to be verified is in an error working state;

the second verification submodule is used for judging whether the verification result is information indicating that the verification sequence is an illegal sequence when the verification sequence is the illegal sequence; if so, the verification result is that the controller to be verified is in a normal working state, and if not, the verification result is that the controller to be verified is in an error working state.

10. The apparatus of any one of claims 6 to 9, further comprising:

the monitoring module is used for monitoring the sequence sent by the controller to be verified in real time;

the control signal generation module is used for generating a control signal according to the sequence sent by the controller to be verified;

and the link control module is used for carrying out zero clearing treatment on all signals in the verification model and disconnecting the link connection between the verification model and the controller to be verified when the generated control signal is an error flag signal.

11. A test apparatus comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors to perform the controller function verification method of one or more of claims 1-5.