CN110958762B - printed wiring board - Google Patents
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- CN110958762B CN110958762B CN201910907814.6A CN201910907814A CN110958762B CN 110958762 B CN110958762 B CN 110958762B CN 201910907814 A CN201910907814 A CN 201910907814A CN 110958762 B CN110958762 B CN 110958762B
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
技术领域technical field
本公开涉及印刷布线基板。The present disclosure relates to printed wiring substrates.
背景技术Background technique
现在,开发了搭载高功能的封装基板、电子部件的印刷布线基板。印刷布线基板具有被层叠的多个绝缘层以及布线导体。布线导体位于被层叠的绝缘层的上下表面或绝缘层彼此之间。位于相互不同的层的布线导体彼此通过在厚度方向贯通绝缘层的通孔内的通孔导体而电连接。这样的印刷布线基板安装有封装基板、电子部件等,例如搭载于服务器等电子设备。Currently, printed wiring boards on which high-performance package substrates and electronic components are mounted are being developed. The printed wiring board has a plurality of laminated insulating layers and wiring conductors. The wiring conductors are located on the upper and lower surfaces of the laminated insulating layers or between the insulating layers. Wiring conductors located in mutually different layers are electrically connected by via conductors in via holes penetrating through the insulating layer in the thickness direction. Such a printed wiring board is mounted with a package substrate, electronic components, and the like, and is mounted, for example, in electronic equipment such as a server.
近年来,随着电子设备的高功能化,封装基板、电子部件的高功能化不断发展,存在信号系统数量、电力供给量增大的倾向。因此,印刷布线基板要求布线导体的增数。为了应对这样的要求,印刷布线基板存在通过增加绝缘层数量来确保布线导体的形成区域的情况。例如,在日本特开2000-244129号公报中,记载了在接近IC芯片等电子部件的位置具备由复合电介质层和金属层构成的层状电容器的布线基板。In recent years, along with the high functionality of electronic equipment, the high functionality of package substrates and electronic components has progressed, and the number of signal systems and the amount of power supply tend to increase. Therefore, the printed wiring board requires an increase in the number of wiring conductors. In order to meet such demands, printed wiring boards sometimes secure a wiring conductor formation area by increasing the number of insulating layers. For example, Japanese Patent Application Laid-Open No. 2000-244129 describes a wiring board including a layered capacitor composed of a composite dielectric layer and a metal layer at a position close to an electronic component such as an IC chip.
发明内容Contents of the invention
本实施方式所涉及的印刷布线基板具有:多个绝缘层,在厚度方向上被层叠;多个布线导体,分别对应地位于所述多个绝缘层之间;通孔,在所述厚度方向上贯通多个所述绝缘层以及多个所述布线导体;以及通孔导体,位于所述通孔的壁面。面向所述通孔的所述布线导体的第1面以在所述厚度方向上贯穿所述通孔的中心轴为基准,位于比面向所述通孔的所述绝缘层的第2面更靠外侧的位置。The printed wiring board according to this embodiment includes: a plurality of insulating layers stacked in the thickness direction; a plurality of wiring conductors respectively correspondingly located between the plurality of insulating layers; and via holes in the thickness direction. penetrating through a plurality of the insulating layers and the plurality of wiring conductors; and a via conductor located on a wall surface of the via hole. The first surface of the wiring conductor facing the through hole is located closer to the second surface of the insulating layer facing the through hole on the basis of the central axis passing through the through hole in the thickness direction. outboard position.
附图说明Description of drawings
图1是表示本公开的印刷布线基板的实施方式例的概略剖视图。FIG. 1 is a schematic cross-sectional view illustrating an embodiment example of a printed wiring board of the present disclosure.
图2是表示本公开的印刷布线基板的实施方式例的主要部位的放大剖视图。2 is an enlarged cross-sectional view of main parts showing an embodiment example of a printed wiring board of the present disclosure.
图3是表示本公开的印刷布线基板的另一实施方式例的主要部位的概略剖视图。3 is a schematic cross-sectional view showing main parts of another embodiment example of the printed wiring board of the present disclosure.
图4是表示本公开的印刷布线基板的另一实施方式例的概略剖视图。4 is a schematic cross-sectional view showing another embodiment example of the printed wiring board of the present disclosure.
图5A是在图3中以概略剖视图表示的部分的电子显微镜照片,图5B是图5A所示的区域X的放大照片。FIG. 5A is an electron micrograph of a portion shown as a schematic cross-sectional view in FIG. 3 , and FIG. 5B is an enlarged photograph of a region X shown in FIG. 5A .
图6是表示以往的印刷布线基板中的布线导体与通孔导体的边界面的电子显微镜照片。FIG. 6 is an electron micrograph showing the interface between a wiring conductor and a via-hole conductor in a conventional printed wiring board.
具体实施方式Detailed ways
接下来,以图1以及图2为基础对本公开的印刷布线基板进行说明。印刷布线基板1具有绝缘基体2、布线导体3以及阻焊剂4。印刷布线基板1在上表面搭载有例如封装基板等的布线基板、电子部件等。印刷布线基板1的厚度为0.04~10.0mm左右。Next, the printed wiring board of the present disclosure will be described based on FIGS. 1 and 2 . Printed
绝缘基体2具有在厚度方向上层叠的5层绝缘层5。绝缘层5例如包含使环氧树脂、双马来酰亚胺三嗪树脂等含浸于增强用的玻璃布而成的绝缘材料。绝缘基体2具有确保印刷布线基板1中的布线导体3的配置区域的功能、以及作为保持平坦性的支承体的功能等。各个绝缘层5的厚度例如被设定为20~400μm。The
这样的,绝缘基体2例如以如下方式形成。首先,准备两片双面覆铜层叠板。双面覆铜层叠板例如是在使绝缘树脂含侵于玻璃布中的绝缘板的上下表面贴附铜箔的层叠板。接下来,通过对各双面覆铜层叠板的铜箔进行蚀刻而形成具有规定的图案的布线导体3。接下来,准备三片预浸料以及两片铜箔。预浸料例如是使绝缘树脂含浸于玻璃布而成的半固化状态的绝缘材料。接下来,以一片预浸料为中心,在其上下表面分别依次层叠双面覆铜层叠板、预浸料、铜箔。接下来,通过在加热下进行冲压加工而形成有上述那样的绝缘基体2。In this way, the
如上所述,基于双面覆铜层叠板的铜箔形成的布线导体3例如也可以相对于厚度方向具有长条形状的晶粒。换言之,晶粒彼此之间的晶体界面大多朝向厚度方向,朝向与厚度方向正交的水平方向的晶体界面少。因此,在印刷布线基板1热膨胀而施加厚度方向的应力时,能够提高布线导体3的耐断裂性,在这一点上是有利的。As described above, the
绝缘基体2具有沿其厚度方向贯通的多个通孔6。通孔6中有在其内侧多个绝缘层的第2面5s以及多个布线导体的第1面3s露出的通孔。绝缘基体2的上下表面的布线导体3彼此、或者绝缘基体2的上下表面以及绝缘层5之间的布线导体3彼此经由通孔6电连接。通孔6的直径例如被设定为50~2000μm。The
如图2所示,在通孔6内,各个布线导体的第1面3s以在厚度方向贯穿通孔6的中心轴为基准,位于比绝缘层的第2面5s更靠外侧的位置。布线导体的第1面3s与绝缘层的第2面5s的高低差例如被设定在1~10μm的范围。As shown in FIG. 2 , in the
若两者的高低差小于1μm,则后述的通孔导体3a的一部分相比于绝缘层的第2面5s,进入到外侧的距离更小。因此,将通孔导体3a卡止于绝缘层5的效果变小。若大于10μm,则在形成后述的通孔导体3a时,镀覆处理液无法良好地回流至布线导体的第1面3s,存在镀铜金属不良好地析出的情况。因此,存在通孔导体3a与布线导体的第1面3s的连接变得不完全的可能性。考虑到这些观点,若将布线导体的第1面3s与绝缘层的第2面5s的高低差设定为3~7μm,则在品质上以及生产上是有利的。If the level difference between both is less than 1 μm, the distance that a part of via-
这样的通孔6例如以如下方式形成。首先,通过钻孔加工形成沿厚度方向贯穿绝缘基体2的贯通孔。接下来,通过去污处理除去残留在贯通孔内的树脂屑。最后,对在通孔6内露出的布线导体3进行蚀刻处理,溶解到成为上述的高低差。由此,形成有上述那样的通孔6。Such through
该蚀刻处理还具有除去在去污处理中未完全除去的金属屑、在贯通孔内露出的布线导体的第1面3s上附着的树脂屑的效果。This etching treatment also has the effect of removing metal shavings not completely removed by the desmear treatment and resin shavings adhering to the
布线导体3位于绝缘层5彼此之间、绝缘基体2的上下表面、以及通孔6内。布线导体3构成印刷布线基板1的导电路径,具有信号的传播、电力的供给等功能。布线导体3例如包含铜等的良导电性金属。The
这样的布线导体3中的位于通孔6内的布线导体作为通孔导体3a发挥功能。各个通孔导体3a具有用于信号的传播的信号用、用于电力的供给的电源用、或者接地用的功能。通孔导体3a将绝缘基体2的上下表面的布线导体3彼此、或者绝缘基体2的上下表面的布线导体3以及绝缘层5之间的布线导体3彼此电连接。Among
通孔导体3a以紧贴于面向通孔6的布线导体的第1面3s以及绝缘层的第2面5s的整个面的状态存在,是在通孔6的径向的中央部具有空洞的筒状。如上所述,布线导体的第1面3s以在厚度方向上贯穿通孔6的中心轴为基准,位于比绝缘层的第2面5s更靠外侧的位置。因此,通孔导体3a的一部分以进入绝缘层5彼此之间的状态存在。The via-
换言之,在通孔6内,布线导体的第1面3s露出的部位是相对于绝缘层的第2面5s凹陷的状态。通孔导体3a与位于该凹坑中的布线导体的第1面3s紧贴,并且也紧贴于绝缘层的第2面5s。In other words, in the via
通孔导体3a与绝缘层的第2面5s的接触面积增加,从而有利于提高通孔导体3a的紧贴强度。特别是在厚度方向上,凹坑中的通孔导体3a起到相对于绝缘层5的卡止的作用,从而能够抑制通孔导体3a与绝缘层5之间的剪切应力。进而,也能够抑制通孔导体3a与布线导体的第1面3s之间的剪切应力。The increase in the contact area between the via-
面向通孔6的布线导体的第1面3s在图2所示的剖视图中具有直线状,但也可以具有曲线状。在这样的情况下,与通孔导体3a的接触面积增加。因此,在能够提高布线导体的第1面3s与通孔导体3a的紧贴强度方面是有利的。The
填充于通孔导体3a的空洞内的孔填充树脂7位于通孔6内。孔填充树脂7在本公开中不是必须的,但在印刷布线基板1具有例如用导体层或者绝缘层等堵塞通孔6的上下的开口的构造的情况下使用。The hole-filling
在通孔6内,通过用孔填充树脂7填充通孔导体3a的内侧,气体、液体难以残留在通孔6内。由此,能够避免由于气体的膨胀、液体的腐蚀等而导致布线导体3等损伤或者腐蚀。In the through-
孔填充树脂7例如包含环氧树脂等热固化性树脂以及二氧化硅等绝缘粒子。
绝缘基体2的上下表面以及位于通孔6内的布线导体3例如以如下方式形成。The upper and lower surfaces of the insulating
首先,准备通过上述工序形成有通孔6的绝缘基体2。接下来,对绝缘基体2的上下表面以及面向通孔6的布线导体的第1面3s以及绝缘层的第2面5s依次进行无电解镀铜处理以及电解镀铜处理。在布线导体的第1面3s以及绝缘层的第2面5s析出的镀铜金属成为通孔导体3a。接下来,在通孔6内的比镀铜金属更靠内侧的位置填充孔填充树脂7并使其固化。接下来,对从通孔6突出的孔填充树脂7进行研磨,使在绝缘基体2的上下表面析出的镀铜金属与孔填充树脂7的露出面成为相同的高度。最后,在绝缘基体2的上下表面析出的镀铜金属以及孔填充树脂7的露出面进行镀覆处理,通过蚀刻形成规定的图案,由此在绝缘基体2的上下表面形成有布线导体3。First, the insulating
通孔导体3a的晶体界面的方向也可以具有随机的晶粒。换句话说,通孔导体3a的晶体界面不具有方向性。在这样的情况下,在能够使施加于通孔导体3a的热应力向随机的方向分散这一点上是有利的。The direction of the crystal interface of via-
阻焊剂4位于最上层的绝缘层5的上表面以及最下层的绝缘层5的下表面。阻焊剂4具有使位于绝缘基体2的上表面的布线导体3的一部分露出的开口4a以及使位于下表面的布线导体3的一部分露出的开口4b。The solder resist 4 is located on the upper surface of the uppermost insulating
在开口4a露出的布线导体3的一部分例如作为与封装基板、电子部件的电极连接的电极发挥功能。A part of the
在开口4b露出的布线导体3的一部分例如作为与电子部件连接的电极发挥功能。A part of the
阻焊剂4例如通过将丙烯酸改性环氧树脂等具有感光性的热固化性树脂的膜粘贴在绝缘层5的表面,通过曝光以及显影来形成开口4a或者开口4b并进行热固化而形成。Solder resist 4 is formed, for example, by attaching a film of photosensitive thermosetting resin such as acrylic modified epoxy resin to the surface of insulating
如上所述,本公开的印刷布线基板1具有在厚度方向上层叠的多个绝缘层5和在多个绝缘层5之间分别对应地存在的多个布线导体3、以及在厚度方向上贯通、多个绝缘层的第2面5s以及多个布线导体的第1面3s露出的通孔6。紧贴于绝缘层的第2面5s以及布线导体的第1面3s的整个面的通孔导体3a位于通孔6内。而且,在通孔6内,多个布线导体的第1面3s以在厚度方向上贯穿通孔6的中心轴为基准,位于比多个绝缘层的第2面5s更靠外侧的位置。换句话说,在通孔6内,布线导体的第1面3s露出的部位是相对于绝缘层的第2面5s凹陷的状态。As described above, the printed
因此,通孔导体3a以其一部分进入凹坑的状态紧贴于布线导体的第1面3s以及绝缘层的第2面5s。由此,通孔导体3a与布线导体的第1面3s以及绝缘层的第2面5s的接触面积增加,有利于提高通孔导体3a的紧贴强度。特别是在厚度方向上,凹坑中的通孔导体3a起到相对于绝缘层5的卡止的作用,能够抑制通孔导体3a与绝缘层5之间的剪切应力。其结果是,能够减少通孔导体3a与布线导体的第1面3s之间的断裂。Therefore, the via-
这样,根据本公开,能够减少具有信号用、电源用或者接地用的功能的通孔导体3a与布线导体的第1面3s之间的断裂。因此,能够提供信号的传播或者电力供给特性优异的印刷布线基板。In this manner, according to the present disclosure, it is possible to reduce breakage between the via-
本公开并不限定于上述的实施方式的一例,只要在不脱离本公开的要旨的范围,能够进行各种变更。The present disclosure is not limited to an example of the above-mentioned embodiment, and various changes can be made without departing from the scope of the present disclosure.
例如,在上述的实施方式的一例中,如图2所示,示出通孔导体3a与孔填充树脂7的界面没有凹部的状态。For example, in an example of the above-mentioned embodiment, as shown in FIG. 2 , the state where the interface between the via-
与该情况不同,如图3所示,通孔导体3a也可以在面向通孔6的多个布线导体的与第1面3s对置的内周面具有环状的凹部8。换句话说,筒状的通孔导体3a的内周面在与上述的凹坑对置的位置具有环状的凹部8。Unlike this case, as shown in FIG. 3 , via-
这样的情况,例如在印刷布线基板1产生热膨胀时,通孔导体3a被进入到凹部8内的孔填充树脂7向布线导体的第1面3s的方向按压。由此,通孔导体3a与布线导体的第1面3s之间的紧贴强度提高。In such a case, for example, when the printed
凹部8的深度例如被设定为2~5μm。在小于2μm的情况下,上述的按压的效果变小,有可能无法有助于通孔导体3a与布线导体的第1面3s之间的紧贴强度的提高。在大于5μm的情况下,有可能难以将孔填充树脂7填充到凹部8内。The depth of the
通过调整电解镀覆处理时间来形成这样的凹部8,以使得布线导体的第1面3s露出的部位成为残留相对于绝缘层的第2面5s凹陷的程度的厚度。另外,在不需要凹部8的情况下,将电解镀覆处理时间进一步延长、或进行两次电解镀覆处理即可。Such a
如图4所示,也可以在绝缘基体2的上下表面进一步层叠增层用的绝缘层9和布线导体3。在本例中,两层的增层用绝缘层9和布线导体3分别位于上表面以及下表面。As shown in FIG. 4 , build-up insulating layers 9 and
增层用绝缘层9具有在绝缘基体2的上下表面确保用于配置布线导体3的区域的功能。因此,具有增层用绝缘层9的构造与伴随电子设备的高功能化的信号系统、电力供给的增大相对应。因此,在能够增加印刷布线基板1的布线导体3这一点上是有利的。The build-up insulating layer 9 has a function of securing a region for arranging the
增层用绝缘层9覆盖布线导体3,具有确保相互邻接的布线导体3彼此的绝缘性的功能。The build-up insulating layer 9 covers the
增层用绝缘层9例如包含E玻璃或者S玻璃等玻璃纤维、聚酰亚胺树脂、环氧树脂或者双马来酰亚胺三嗪树脂等绝缘树脂以及二氧化硅(SiO2)或者氧化铝(Al2O3)等绝缘粒子等。对于玻璃纤维来说也可以不包含。The build-up insulating layer 9 includes, for example, glass fiber such as E glass or S glass, insulating resin such as polyimide resin, epoxy resin, or bismaleimide triazine resin, and silicon dioxide (SiO 2 ) or alumina. (Al 2 O 3 ) and other insulating particles. It is also not necessary for glass fibers to be included.
增层用绝缘层9例如通过将绝缘层用的膜被覆并进行热压接、固化而形成,以使得在真空下将布线导体3覆盖于绝缘基体2的上下表面、或者已经形成的增层用绝缘层9的表面。The build-up insulating layer 9 is formed, for example, by covering the film for the insulating layer, performing thermocompression bonding, and curing so that the
增层用绝缘层9具有以布线导体3为底面的多个过孔10。经由增层用绝缘层9而位于上下的布线导体3彼此经由过孔10内的布线导体3电连接。过孔10的直径例如被设定为30~100μm。The build-up insulating layer 9 has a plurality of via holes 10 having the
过孔10例如通过对增层用绝缘层9实施激光加工处理而形成。在激光加工之后,对过孔10的内部进行清洗,除去碳化物等异物,由此能够提高布线导体3与在过孔10内露出的增层用绝缘层9以及布线导体3之间的紧贴强度。Via hole 10 is formed, for example, by performing laser processing on build-up insulating layer 9 . After laser processing, the inside of the via hole 10 is cleaned to remove foreign substances such as carbides, thereby improving the adhesion between the
布线导体3位于增层用绝缘层9的上表面或者下表面、以及过孔10内。布线导体3例如通过半添加法、减成法等镀覆处理技术形成,包含铜等良导电性金属。
阻焊剂4位于最上层的增层用绝缘层9的上表面以及最下层的增层用绝缘层9的下表面。阻焊剂4具有使位于增层用绝缘层9的上表面的布线导体3的一部分露出的开口4a、使位于下表面的布线导体3的一部分露出的开口4b。The solder resist 4 is located on the upper surface of the uppermost insulating build-up layer 9 and the lower surface of the lowermost insulating build-up layer 9 . The solder resist 4 has the
在开口4a露出的布线导体3的一部分例如作为与封装基板、电子部件的电极连接的电极发挥功能。在开口4b露出的布线导体3的一部分例如作为与电子部件连接的电极发挥功能。A part of the
将在图3中以概略剖视图表示的部分的电子显微镜照片示于图5A。图5A所示的区域X的放大照片如图5B所示。图5A以及图5B所示的符号与图3所示的符号相同,省略说明。FIG. 5A shows an electron micrograph of the portion shown as a schematic cross-sectional view in FIG. 3 . An enlarged photograph of the region X shown in FIG. 5A is shown in FIG. 5B. The symbols shown in FIGS. 5A and 5B are the same as those shown in FIG. 3 , and description thereof will be omitted.
例如,在图2以及3中,明确地示出了布线导体的第1面3s的位置。这只是为了方便地示出在剖视图中示出时布线导体的第1面3s的位置,如图5B所示,布线导体的第1面3s不清楚的状态、即布线导体的第1面3s与通孔导体3a的边界面也可以是非直线地交错而浑然一体的状态。换句话说,在对布线导体3进行蚀刻处理时,使布线导体的第1面3s非直线地交错的状态,换言之处理为凹凸形状,使成为通孔导体3a的镀铜金属析出,由此布线导体的第1面3s与通孔导体3a的边界面成为上述的状态。For example, in FIGS. 2 and 3 , the position of the
如图5B中的箭头所示,对于形成布线导体3的导体而言,晶体在通孔6的深度方向上、即沿着通孔6的中心轴方向延伸。换句话说,在剖面视图中晶体具有在上层的绝缘层5与下层的绝缘层5的层叠方向上延伸的长条形状。这样,若形成布线导体3的导体的晶体沿通孔6的深度方向延伸,则能够使布线导体3更强地紧贴于绝缘层5。例如,在对印刷布线基板施加负荷的情况下,通孔导体3a容易在与通孔6的深度方向正交的方向、即与布线导体3、绝缘层5的主面水平的方向上施加负荷。即使这样的负荷施加于布线导体3,布线导体3也通过绝缘层5更强地紧贴,因此能够降低由负荷引起的通孔导体3a的位移,能够更不易断裂。在此,“晶体在沿着通孔6的中心轴的方向上延伸”表示晶体基本上在沿着通孔6的中心轴的方向上延伸。换句话说,晶体延伸的方向基本上沿着通孔6的中心轴。因此,晶体相对于通孔6的中心轴延伸的方向的角度可以是0至30度,更具体的是0至10度。As indicated by the arrows in FIG. 5B , for the conductor forming the
在对通孔6内露出的布线导体3进行蚀刻处理的情况下,使蚀刻液流向通孔6而进行。如图5B的区域Y所示,蚀刻液的流动的上游侧的通孔6的壁面与通孔导体3a的角具有锥状,去掉角部。通过这样去掉角部而具有锥状,从而形成通孔导体3a时的镀覆液容易向布线导体3方向流入。When etching the
如图6所示,以往的印刷布线基板中的布线导体13与通孔导体13a的边界面如区域Z所示,在通孔的壁面附近比较的明确地显现。若布线导体13与通孔导体13a的边界面存在于通孔的壁面附近,则例如在对印刷布线基板施加了负荷的情况下,容易在形成布线导体13的导体的晶体与形成通孔导体13a的导体的晶体之间产生断裂,容易产生导通不良。针对于此,本公开的印刷布线基板的信号的传播或者电力供给特性优异。As shown in FIG. 6 , in the conventional printed wiring board, the boundary surface between the
在上述的实施方式中,示出了通孔导体3a为筒状的情况。与该情况不同,在不需要孔填充树脂7或者凹部8的情况下,通孔导体3a也可以将通孔6内填充。在该情况下,通孔导体3a的电阻降低。因此,从提高信号的传播或者电力供给特性的观点出发是有利的。In the above-mentioned embodiment, the case where the via-
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4628598A (en) * | 1984-10-02 | 1986-12-16 | The United States Of America As Represented By The Secretary Of The Air Force | Mechanical locking between multi-layer printed wiring board conductors and through-hole plating |
JPH1131884A (en) * | 1997-07-11 | 1999-02-02 | Hitachi Ltd | Multilayer printed circuit board and electronic device |
JP2008066544A (en) * | 2006-09-08 | 2008-03-21 | Nec Corp | Multilayer printed circuit board and its manufacturing method |
JP2009182082A (en) * | 2008-01-30 | 2009-08-13 | Kyocera Corp | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND MOUNTING STRUCTURE |
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JP6600176B2 (en) * | 2015-06-19 | 2019-10-30 | ホシデン株式会社 | Multilayer printed wiring board and connection structure between multilayer printed wiring board and connector |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4628598A (en) * | 1984-10-02 | 1986-12-16 | The United States Of America As Represented By The Secretary Of The Air Force | Mechanical locking between multi-layer printed wiring board conductors and through-hole plating |
JPH1131884A (en) * | 1997-07-11 | 1999-02-02 | Hitachi Ltd | Multilayer printed circuit board and electronic device |
JP2008066544A (en) * | 2006-09-08 | 2008-03-21 | Nec Corp | Multilayer printed circuit board and its manufacturing method |
JP2009182082A (en) * | 2008-01-30 | 2009-08-13 | Kyocera Corp | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND MOUNTING STRUCTURE |
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