CN110958756A - Integrated system architecture of accelerator sequential system and fast machine protection system - Google Patents
Integrated system architecture of accelerator sequential system and fast machine protection system Download PDFInfo
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Abstract
The invention relates to the field of accelerators, in particular to an integrated system framework which is applied to small and medium-sized particle accelerators and can simultaneously meet the requirements of an accelerator physical time sequence system and a rapid machine protection system, has low cost and high flexibility and is used for the accelerator time sequence system and the rapid machine protection system; the main hardware of the integrated system architecture comprises a VME case, a VME controller, a VME J2 back plate connecting plug-in, a main logic plug-in and a multifunctional interface plug-in; the invention provides a time sequence and rapid protection system integrated architecture and a practice based on low cost and high flexibility, which can reliably and stably carry out high-efficiency interaction such as signal input/output and the like, integrally realize rapid logic processing, time sequence design functions and the like, and meet the requirements of an accelerator on a time sequence system and a rapid machine protection system.
Description
Technical Field
The invention relates to the field of accelerators, in particular to an integrated system framework which is applied to small and medium-sized particle accelerators, can simultaneously meet the requirements of an accelerator physical time sequence system and a rapid machine protection system, has low cost and high flexibility and is used for the accelerator time sequence system and the rapid machine protection system.
Background
At present, small and medium-sized particle accelerators have irreplaceable effects in the aspects of scientific innovation and leading industrial technical revolution, wherein a large amount of intelligent equipment is adopted to be put into scientific research, each kind of equipment is clearly divided into work and only completes the work in charge of the equipment, but the start and the completion of each work have strict time relation and have more accurate time intervals, so that the time sequence of the equipment work needs a stable production, transmission and receiving mechanism, and the mechanism has higher requirements on accuracy and stability; meanwhile, when some equipment (equipment) or beam current is abnormal, beam current output needs to be stopped quickly, and the time sequence of related equipment needs to be cut off or changed in time, so that the equipment is prevented from being permanently damaged due to beam current loss. In view of the scale, equipment distribution and construction cost of small and medium-sized particle accelerators, the design of integrating a time sequence system and a rapid machine protection system is adopted, the structure is compact, a main logic plug-in realizes time sequence generation logic, rapid machine protection logic and the like, and a multifunctional interface plug-in realizes input/output of various signals, so that the requirements of the accelerator on the time sequence system and the rapid machine protection system can be met simultaneously, and the method becomes a very excellent technical route.
In the prior art, a conventional solution is to use two chassis devices to respectively implement sequential logic and fast machine protection logic. Taking VME control as an example, 2 sets of VME chassis, 2 sets of VME controllers, 1 block of time sequence generation logic plug-in, 1 block of fast machine protection logic plug-in, 1 to 2 blocks of time sequence transmission plug-ins, 1 to 3 blocks of interface plug-ins, and the like are needed; therefore, although the system requirements can be solved, the cost is high, the system is bulky, and the unified maintenance is inconvenient. In addition, aiming at the diversified machine research of small and medium-sized accelerators, new requirements on the types and functional logics of interface plug-ins are often required to be added, so that the flexible and changeable integrated architecture is favorable for saving the construction cost and running maintenance.
Disclosure of Invention
Aiming at the characteristics of operation of small and medium-sized particle accelerators, the invention aims to provide a system architecture with low cost and high flexibility, and an integrated system architecture for an accelerator timing system and a rapid machine protection system, which can meet the requirements of accelerator physics on the timing system and the rapid machine protection system.
The technical scheme adopted by the invention is as follows: the integrated system architecture of the accelerator timing system and the rapid machine protection system is characterized in that main hardware of the integrated system architecture comprises a VME case, a VME controller, a VME J2 back plate connecting plug-in, a main logic plug-in and a multifunctional interface plug-in, wherein the VME case adopts an international standard architecture, and a power supply is installed on the VME case; the VME controller adopts a VME5500 plug-in; the main logic plug-in adopts the size of a standard 6U VME plug-in, and is attached with a Xilinx FPGA chip of programmable logic resources; the VME J2 backplane connecting plug-in is used for reversely buckling the VME backplane, so that the main logic plug-in and the multifunctional interface plug-in can interact with 80 paths of I/O signals at most through the plug-in.
The multifunctional interface plug-in comprises six types: the optical signal type input interface plug-in board, the optical signal type output interface plug-in board, the contact signal type input interface plug-in board, the contact signal type output interface plug-in board, the 5V/3.3V TTL signal type input interface plug-in board, the 5V/3.3V TTL signal type output interface plug-in board.
The main logic plug-in adopts XC6SLX100T-2FGG900C produced by Xilinx corporation as an FPGA logic chip, and an auxiliary module/interface in the main logic plug-in mainly comprises a plurality of voltage modules, an onboard 100MHz crystal oscillator interface, a VME bus interface, a VME J2 custom 80-path I/O interface, a high-speed optical fiber transceiving interface, an external radio frequency signal input interface and the like.
The VME J2 backboard connecting plug-in adopts 6 96PIN European connectors which are sequentially arranged according to the spacing of the standard VME backboard connectors, the design value of the plug-in appearance mechanical dimension is 3730mil by 4548mil, and the VME case backboard is convenient to reversely buckle.
The VME J2 backboard connecting plug-in units are arranged at a standard VME connector pitch of 800mil, and the 4 th slot connector of the VME case is defined as a master connector, and the rest five slots are defined as slave connectors.
The integrated system framework adopts a standard 7-slot VME case, and 1 VME controller, 2 multifunctional interface plug-ins, 1 main logic plug-in and 3 multifunctional interface plug-ins which are provided with VME5500 plug-ins are sequentially inserted from bottom to top, an external radio frequency signal port of each main logic plug-in is connected with a radio frequency signal, an input/output port of each optical signal type plug-in is connected with a multimode optical fiber, an input/output port of each contact signal type plug-in is connected with a common cable, and a network port of the controller VME5500 is connected with a network port of a PC.
The design and implementation principle of the integrated system architecture for realizing the time sequence system is as follows: according to the requirements of small and medium accelerators on a timing system, the frequency, the pulse width and the time delay of a timing signal can be adjusted on line in real time, and certain requirements are made on the adjustment range and the accuracy, and in addition, the timing signal needs to be synchronous with a radio frequency signal; the main logic plug-in utilizes an AD9515 chip to divide an external access signal such as a 324MHz radio frequency signal 4 into 81MHz square wave differential clock signals, the signals are transmitted to a global clock pin of the FPGA after impedance matching, a series of timing signals are generated by adopting a counting mode, and the timing signals are synchronous with the radio frequency signals; then, self-defining 16 paths of timing signals, and setting 7 registers with 16 bits for each path of timing signals, wherein the registers are respectively recorded as: the accelerator comprises an enabling register, a frequency register A, a frequency register B, a pulse width register A, a pulse width register B, a delay register A and a delay register B, wherein 7 registers are arranged in real time on line, so that the frequency, the pulse width and the mutual delay of time sequence signals meet the actual operating requirements of the accelerator.
The design and implementation principle of the integrated system architecture for realizing the rapid machine protection system is as follows: according to the physical requirements of small and medium accelerators on a rapid machine protection system, the working state signals of all equipment are rapidly collected and monitored in real time, when a fault occurs, after rapid logic processing, time sequence and power permission signals for stopping the relevant equipment are timely sent out, and after the fault is confirmed to be not output any more, the time sequence and power permission signals of the relevant equipment are synchronously recovered.
The invention has the beneficial effects that: the invention aims at the requirements of time sequence and rapid machine protection of small and medium-sized accelerators, and invents a time sequence and rapid protection system integrated architecture and practice based on low cost and high flexibility, and the result shows that the system has higher flexibility, easy maintenance and higher reliability through simple I/O pin configuration and FPGA programmable logic, and can efficiently solve a certain number of optical fiber signals, contact signals or 5V/3.3V TTL signals in the small and medium-sized particle accelerators, reliably and stably carry out high-efficiency interaction such as signal input/output and the like, and the integration realizes rapid logic processing, time sequence design function and the like, thereby meeting the requirements of accelerator physics on a time sequence system and a rapid machine protection system.
Drawings
FIG. 1 is a diagram of the hardware layout of the integrated system architecture of the present invention.
FIG. 2 is a PCB view of a main logic card of the present invention.
FIG. 3 is a PCB diagram of a VME J2 backplane connector insert of the present invention.
Fig. 4 is a PCB diagram of an optical signal type input package in the present invention.
Fig. 5 is a PCB diagram of an optical signal type output package in the present invention.
Fig. 6 is a PCB diagram of a contact signal type input card in the present invention.
Fig. 7 is a PCB diagram of a contact signal type output package in the present invention.
FIG. 8 is a PCB diagram of a 5V/3.3V TTL signal type input plug in accordance with the present invention.
FIG. 9 is a PCB diagram of the 5V/3.3V TTL signal type output package of the present invention.
Reference is made to the accompanying drawings in which: the system comprises a 1-VME case, a 2-optical signal type output interface plug-in, a 3-optical signal type input interface plug-in, a 4-main logic plug-in, a 5-contact signal type input interface plug-in, a 6-contact signal type output interface plug-in and a 7-VME controller.
Detailed Description
The following detailed description of the embodiments of the invention is provided in conjunction with the drawings of the specification:
as shown in fig. 1-9, the main hardware of the integrated system architecture includes a VME chassis 1, a VME controller 7, a main logic plug-in 4, a multifunctional interface plug-in, and a VME J2 backplane connection plug-in, the VME chassis 1 adopts an international standard architecture, and a high-stability, high-reliability linear commercial power supply is installed on the VME chassis 1; the VME controller 7 adopts VME5500 plug-in manufactured by Emerson; the main logic plug-in 4 adopts the size of a standard 6U VME plug-in, and is attached with a Xilinx FPGA chip with high performance and programmable logic resources; the VME J2 backplane connection plug-in is used for reversely buckling the VME backplane, so that the main logic plug-in 4 and the multifunctional interface plug-in can interact with 80 paths of I/O signals at most through the plug-in.
The main logic plug-in 4 adopts XC6SLX100T-2FGG900C produced by Xilinx corporation as an FPGA logic chip, and an auxiliary module/interface in the main logic plug-in 4 mainly comprises a plurality of voltage modules, an onboard 100MHz crystal oscillator interface, a VME bus interface, a VME J2 customized 80-path I/O interface, a high-speed optical fiber transceiving interface, an external radio frequency signal input interface and the like; in this embodiment, the main logic plug-in 4 is provided with a 5V/12V external power input interface, a 100MHz crystal oscillator, two rf signal processing chips AD9515, two 96PIN standard VME connectors, a VME J280I/O interface, 8 LEDs, and the like; in specific implementation, as the main logic plug-in 4 is provided with two external power supply input interfaces, when the VME case 1 is in joint debugging, a 5V power supply is taken from the VME back plate to supply power; when debugging the single board in the laboratory, a 12V independent power supply is used for supplying power, wherein a 100MHz crystal oscillator is mainly used for the single board logic debugging and heartbeat function realization of a main logic plug-in 4; the two radio frequency signal processing chips AD9515 are mainly used for converting an external access signal such as a 324MHz/74MHz radio frequency signal into an 81MHz/74MHz LVDS clock signal, so that the external access signal can be conveniently received by the FPGA and transmitted to a global clock chain, a serial time sequence signal generated by adopting a counting mode is synchronous with the external access radio frequency signal by taking the global clock as a reference signal, and the time sequence requirements of debugging and running of an accelerator are met; the VME J1 connector realizes VME bus data reading and 5V power supply, and the VME J2 connector realizes one-to-one correspondence of 80 paths of I/O signals and FPGA I/O PINs; 80 paths of I/O signals of the VME J2 connector are connected to FPGA I/O pins through five 74ALVC164245 chips, and the input/output mode of each 74ALVC164245 chip is independently configured through FPGA main logic, so that the receiving/sending of the 80 paths of I/O signals is realized, and the physical requirements of a time sequence system and a rapid machine protection system are met; the 8 LEDs are mainly used for displaying the state of the FPGA register in real time when the system is debugged and operated.
The technical principle of the implementation of the various voltage modules is as follows: in order to meet the requirements of various levels of an FPGA chip, external input stable 12V/5V voltage is used as input voltage, and 4 high-performance 16A rated non-isolated power supply modules PTH08T220WAD produced by TEXAS INSTRUMENTRENTS company are adopted to respectively output stable 3.3V, 2.5V, 1.2V and 1.8V; the generated stable 1.8V voltage is an input voltage, and two TPS74401 KTWRGs which are manufactured by TEXAS INSTRUMENTS and can quickly respond to a transient state are used to output two special voltages MGTAVCC1 and MGTAVCC2 of a high-speed serial link.
The technical principle of realization of the onboard 100MHz crystal oscillator interface is as follows: a FXO-LC725R-100 crystal oscillator produced by Fox Electronics is adopted to provide a high-stability clock source with +/-50 ppm and LVDS output, and the high-stability clock source is input to an FPGA global clock pin after impedance matching.
The technical principle of the VME bus interface is as follows: the interaction between the main logic plug-in 4 and a VME J2 back panel hardware link is realized by adopting a high-reliability I/O level switching chip SN74ALVTHR162245DGGR and SN74ALVTH162244DGGR produced by TEXAS INSTRUMENTMENTS company; the read-write of a 16-bit register is realized by using VHDL according to the read-write principle of the standard VME bus of A24D32, namely, the reliable configuration and the effective monitoring of the main logic plug-in 4 are realized by the VEM bus.
The technical principle for realizing the VME J2 customized 80-path I/O interface is as follows: five high-reliability I/O level switching chips SN74ALVTHR162245DGGR manufactured by TEXAS INSTRUMENTENTS company are adopted to realize the custom pin interface of 80-channel I/O and VME J2; two pins capable of setting 16 paths of I/O transmission directions of each chip are connected into the main logic plug-in 4, and the programmable logic of the main logic plug-in 4 selects the 16 paths of I/O transmission directions according to actual needs.
The technical principle of the realization of the high-speed optical fiber transceiving interface is as follows: the method is realized by adopting a high-speed serial interface of a gigabit multi-mode SFP optical module FTLF8524P2BNV produced by Finisar company and a main logic plug-in 4, and is mainly used for 80-path I/O signal interaction between sites.
The technical principle of the external radio frequency signal input interface is as follows: an AD9515 chip produced by ANALOG DEVICES company is adopted to convert an external radio frequency input signal into a differential LVDS clock signal, the differential LVDS clock signal is transmitted to an FPGA global clock pin after impedance matching, the clock signal is used as a signal source, time sequence design is carried out through a classical counting method, and a generated time sequence signal is strictly synchronous with the external radio frequency input signal.
The VME J2 backplane connecting plug-in is used for reversely buckling a VME J2 backplane, so that the main logic plug-in 4 and the multifunctional interface plug-in can carry out 80 paths of I/O signal interaction at most through the VME J2 backplane connecting plug-in; the VME J2 backplane connection plug-in adopts 6 96PIN European connectors, and is arranged in sequence according to the spacing of standard VME backplane connectors, more specifically, the spacing of standard VME connectors is 800mil, and the plug-in appearance mechanical dimension design value is as follows: 3730mil 4548mil, which is convenient for reversely buckling the back plate of the VME case 1; according to a convention used by the 7-slot VME case 1, the lowest slot position of the case is defined as the 1 st slot position, and the rest is repeated until the uppermost slot position of the case is defined as the 7 th slot position; because the layout of 6 connectors on the VME J2 backplane connector determines the slot position of the main logic card 4 and the multifunctional interface card in the VME chassis 1, that is, the main logic card 4 can only be inserted into the 4 th slot position of the VME, and the multifunctional interface card can be inserted into all slots except the 1 st and 4 th slots.
In order to facilitate reasonable wiring, more specifically to optimize 80 paths of I/O interface wiring, the 3 rd connector is defined as a master connector, that is, the 4 th slot position connector of the VME case 1 is defined as a master connector, and the rest connectors are defined as slave connectors; namely, the other five slot positions are slave connectors; the 80 paths of I/O interfaces of the main connector are distributed in A, C, D, Z four rows, wherein the signals connected to the C row are arranged in a signal-signal mode, and the signals connected to the A, D, Z three rows are arranged in a signal-GND-signal mode; the 80I/O interfaces of the main connector correspond to the 80I/O interfaces of the main logic plug-in 4VME J2 one by one, and the 80I/O signals can freely interact by setting the transmission direction of the I/O ports of the main logic plug-in 4.
80 paths of I/O interfaces of the master connector are directly connected with 16 paths of I/O interfaces of each slave connector in a point-to-point mode; more specifically, each 16-path I/O interface of the slave connector is arranged in the A row of the connector in a signal-GND-signal mode, and each 16-path I/O interface of the slave connector establishes a link with the 16-path I/O interface of the master connector in a point-to-point mode; 16I/O interfaces of the slave connector correspond to 16I/O interfaces of the multifunctional interface plug-in VME J2 one by one;
the main connector can only be connected with the main logic plug-in 4, and 80 paths of I/O interfaces of the main connector correspond to 80 paths of I/O signals of the main logic plug-in 4VME J2 one by one; the slave connector can only be connected with the multifunctional plug-in, and the 16 paths of I/O interfaces of the slave connector are in one-to-one correspondence with the 16 paths of I/O signals of the multifunctional plug-in VME J2.
The main connector can receive signals of any one slave connector I/O interface and can also send signals to any one slave connector I/O interface, and free interaction of 80 paths of I/O signals is flexibly realized.
The multifunctional interface plug-in comprises six types: the optical signal type input interface plug-in module comprises an optical signal type input interface plug-in module 3, an optical signal type output interface plug-in module 2, a contact signal type input interface plug-in module 5, a contact signal type output interface plug-in module 6, a 5V/3.3V TTL signal type input interface plug-in module and a 5V/3.3V TTL signal type output interface plug-in module; the six types of interface plug-ins all adopt the following same technical design elements: (1) the PCB layout is a laminated TOP-GND-POWER-BOTTOM, wherein the plate thickness is 2.4mm, and the PCB is developed by adopting standard 6UVME size 233 x 160 mm; (2) acquiring a 5V voltage-stabilized power supply of the VME standard back plate from power supply PINs of connectors of VME J1 and J2 by adopting standard 96PIN European VME J1 and J2 connectors; (3) the fast transient response and low noise LDO voltage stabilizer LT1764EQ-3.3 produced by LINEAR company is adopted to realize the conversion from 5V to 3.3V; the 16 paths of I/O interfaces are arranged in the A row of the VME J2 connector in a signal-GND-signal mode and correspond to the 16 paths of I/O interfaces of the slave connector of the VME J2 backboard connecting plug-in unit one by one; (4) the 16 paths of I/O signal transmission are realized to have the same time delay by adopting an equal-length wiring mode; (5) level conversion of 8 paths of I/O signals is respectively realized by adopting two high-reliability I/O level switching chips 74ALVC164245 produced by TEXAS INSTRUMENTS company; wherein the I/O signal level of the multifunctional interface plug-in is designed to be 3.3V; the I/O signal level of the VME J2 backplane connector is designed to be 5V to enhance tamper resistance.
The optical signal type input interface plug-in 3 mainly functions to access external 16 optical signals, and more specifically, mainly functions to access 16 optical signals transmitted by multimode optical fibers to a slave connector of a VME J2 backplane, and mainly includes a transmission link: optical signal → turn to TTL signal → optical signal type input interface plug-in 3VME J2 connector I/O interface → chassis VME J2 backplane slave connector → chassis VME J2 backplane master connector → master logic plug-in 4VME J2 connector I/O interface → master logic plug-in 4; the implementation method and the technical elements are mainly that 16 optical signal receiving devices HFBR-2412RX produced by Agilent Technologies are adopted to respectively receive 16 paths of optical signals input by multimode optical fibers, and pi-type filtering is adopted to obtain TTL signals; according to the protection requirement of the rapid machine and the interlocking redundancy design principle, the module is logically defined: when the multimode fiber input is in a no-light state, the logic input signal level is 3.3V TTL; when the multimode fiber input is in a light state, the logic input signal level is 0V TTL; and the acquired 16 paths of TTL signals are in one-to-one correspondence with 16 paths of I/O interfaces of the VME J2 connector and are sent to the VMEJ2 backplane connector.
The optical signal type output interface card 2 mainly functions to output 16 optical signals, and more specifically, mainly functions to output 16I/O signals of the chassis VME J2 backplane from the connector as optical signals, and mainly includes a transmission link: main logic plug-in 4 → main logic plug-in 4VME J2 connector I/O interface → chassis VME J2 backplane main connector → chassis VME J2 backplane slave connector → plug-in VME J2 connector I/O interface → transfer TTL signal → optical signal; the implementation method and the technical elements are mainly that 16 pieces of 74ACT00 produced by ST Microelectronics company are adopted to respectively receive 16 paths of I/O signals of a VME J2 connector, and each path of I/O signal is independently driven by a three-level logic AND gate to generate TTL signals; the 16 TTL signals respectively drive 16 optical signal transmitters HFBR-1414TX manufactured by Agilent Technologies to realize 16 optical signal outputs; according to the protection requirement of the rapid machine and the interlocking redundancy design principle, the module is logically defined: when the logic output signal is a 5V TTL signal, the output of the optical signal transmitter is in a non-optical state; when the logic output signal is a 0V TTL signal, the output of the optical signal transmitter is in an optical state.
The contact signal type input interface card 5 mainly functions to input 16-path 24V contact type signals, and more specifically, mainly functions to connect 16-path 24V contact signals transmitted by cables to a slave connector of a backplane of a chassis VME J2, and mainly transmits a link: contact signal → turn to TTL signal → contact signal type input interface card 5VME J2 connector I/O interface → chassis VME J2 backplane slave connector → chassis VME J2 backplane master connector → master logic card 4VME J2 connector I/O interface → master logic card 4; the method and the technical elements for realizing the voltage stabilizing circuit are mainly that 4 stable 24V voltage sources are respectively generated by 4 5V-to-24V power supply modules RN0524S produced by Vishay Siliconix company, and each stable 24V voltage source provides output voltage for 4 paths of contact signals; secondly, 4 PCB board level receiving devices IC 2,5/8-GF-5, 08-1825187 produced by Phoenix company are adopted as contact type signal interface devices, each interface device is responsible for inputting 4 paths of contact type signals, and the 4 paths of contact type signals share one output power supply; the FOD060L of a 16-path optical signal receiving device produced by Fairchild Semiconductor company is adopted to receive 16-path contact signals respectively, FOD060L input logic belongs to CMOS logic, the trigger level of logic inversion is 12V, and the problem of false triggering caused by long-distance cable transmission is solved; acquiring a 3.3V TTL signal by adopting pi-type filtering; according to the protection requirement of the rapid machine and the interlocking redundancy design principle, the module is logically defined: when the external contact input is in a disconnected state, the logic input signal level is 3.3V TTL; when the external contact input is in a closed state, the logic input signal level is 0V TTL. Due to the fact that the input port of the high-speed optical coupler receiver FOD060L has positive and negative polarities, strict attention needs to be paid when the high-speed optical coupler receiver FOD060L is implemented.
The contact signal type output interface plug-in 6 mainly functions to output 16 contact signals, and more specifically, mainly functions to output 16I/O signals of the chassis VME J2 backplane from the connector as contact signals, and mainly includes a transmission link: main logic plug-in 4 → main logic plug-in 4VME J2 connector I/O interface → chassis VME J2 backplane main connector → chassis VME J2 backplane slave connector → plug-in VME J2 connector I/O interface → transfer to TTL signal → contact signal; the implementation method and the technical elements are mainly that 16 NPN type triodes 8050 produced by Micro Electronics company are adopted to respectively receive 16 paths of I/O signals of a VMEJ2 connector, each path of I/O signal independently passes through the base level of a triode, and a collector outputs a 5V TTL signal logic level; secondly, respectively receiving 5V TTL signals output by 16 triode collector electrodes by adopting a 16-path high-speed optical coupler transmitter AQV214 produced by Panasonic Semiconductor company to realize 16-path contact signal output; according to the protection requirement of the rapid machine and the interlocking redundancy design principle, the module is logically defined: when the level of the logic output signal is 5V TTL, the contact output is in a disconnected state; when the level of the logic output signal is 0V TTL, the contact output is in a closed state; due to the fact that the output port of the high-speed optical coupler transmitter AQV214 has positive and negative polarities, strict attention needs to be paid when the high-speed optical coupler transmitter AQV is implemented.
The 5V/3.3V TTL signal type input interface plug-in has the main functions of inputting 16 paths of 5V/3.3V TTL electric signals, and more particularly is mainly used for connecting 16 paths of optical signals transmitted by a 50 omega coaxial line into a VME J2 back plate slave connector, and a main transmission link: TTL signal → TTL signal input type interface plug VME J2 connector I/O interface → chassis VME J2 backplane slave connector → chassis VME J2 backplane master connector → main logic plug 4VME J2 connector I/O interface → main logic plug 4; the method and the technical elements for realizing the method are mainly that 16 single-base EPL.00.250.NTN produced by LEMO company are adopted to respectively receive 16 paths of electric signals; secondly, impedance matching is realized by adopting a serial termination mode, and the signal integrity is improved; the 16-channel high-speed electric signal receiving device NC7NZ34 produced by Fairchild Semiconductor company is adopted to respectively receive the input of 16-channel electric signals; according to the protection requirement of the rapid machine and the interlocking redundancy design principle, the module is logically defined: when an externally accessed electric signal is in a 5V/3.3V TTL state, the level of a logic input signal is 3.3V TTL; when the externally accessed electric signal is in a 0V TTL state, the logic input signal level is 0V TTL.
The 5V/3.3V TTL signal type output interface card has a main function of outputting 16 paths of 5V/3.3V TTL electrical signals, and more particularly, is mainly used for outputting 16 paths of I/O signals of the VME J2 backplane of the chassis from the connector as TTL signals, and is mainly a transmission link: main logic plug-in 4 → main logic plug-in 4VME J2 connector I/O interface → chassis VME J2 backplane main connector → chassis VME J2 backplane slave connector → plug-in VME J2 connector I/O interface → transfer TTL signal → TTL signal; the method and the technical elements for realizing the method are mainly that 16 single-base EPL.00.250.NTN produced by LEMO company are adopted to respectively send 16 paths of electric signals; secondly, impedance matching is realized by adopting a serial termination mode, and the signal integrity is improved; moreover, a 16-channel high-speed electric signal driving chip NC7NZ34 produced by Fairchild Semiconductor company is adopted to respectively improve the output current of 16-channel electric signals; according to the protection requirement of the rapid machine and the interlocking redundancy design principle, the module is logically defined: when the level of the logic output signal is 5V TTL, the output of the electric signal is in a 5V/3.3V TTL state; when the logic output signal level is 0V TTL, the electric signal output is in a 0V TTL state.
The design and implementation principle of the integration of the integrated system architecture for the accelerator timing system and the rapid machine protection system is as follows: adopt a standard 7 groove VME machine case 1, from the bottom up, insert 1 VME controller 7, 2 multi-functional interface plug-ins, 1 main logic plug- ins 4, 3 multi-functional interface plug-ins that are furnished with VME5500 plug-ins in proper order, wherein, multi-functional interface plug-ins include six types: light signal type input interface plug-in 3, light signal type output interface plug-in 2, contact signal type input interface plug-in 5, contact signal type output interface plug-in 6, 5V/3.3V TTL signal type input interface plug-in, 5V/3.3VTTL signal type output interface plug-in can select wantonly, collocation according to actual demand. In addition, an external radio frequency signal port of the main logic plug-in 4 is accessed with a radio frequency signal, an input/output port of the optical signal type plug-in is accessed with a multimode optical fiber, an input/output port of the contact signal type plug-in is accessed with a common cable, and a network port of the controller VME5500 is accessed with a network port of a PC.
The design and implementation principle of an integrated system architecture realization timing system for an accelerator timing system and a rapid machine protection system is as follows: according to the requirements of small and medium accelerators on a timing system, the frequency, the pulse width and the time delay of a timing signal can be adjusted on line in real time, and certain requirements are made on the adjustment range and the accuracy, and in addition, the timing signal needs to be synchronous with a radio frequency signal; the main logic plug-in 4 utilizes an AD9515 chip to divide an external access signal such as a 324MHz radio frequency signal 4 into 81MHz square wave differential clock signals, transmits the signals to a global clock pin of the FPGA after impedance matching, and generates a series of timing signals by adopting a counting mode, wherein the timing signals are synchronous with the radio frequency signals; then, self-defining 16 paths of timing signals, and setting 7 registers with 16 bits for each path of timing signals, wherein the registers are respectively recorded as: the system comprises an enabling register, a frequency register A, a frequency register B, a pulse width register A, a pulse width register B, a delay register A and a delay register B, wherein the definition and the use description of the 7 registers are as follows: enabling the register value to be 0, indicating that the time sequence signal is not output, and otherwise indicating that the time sequence signal is output; the frequency register A sets the output frequency of the time sequence signal, and the step length is adjusted: 1Hz, regulating range: 0 to 65 kHz; the frequency register B sets the output frequency of the time sequence signal, and the step length is adjusted: 1Hz, regulating range: 65 kHz-81 MHz; the pulse width register A adjusts the pulse width of the time sequence signal, and the step length is adjusted: 12.3ns, adjustment range: 0-65535 x 12.3 ns; the pulse width register B adjusts the pulse width of the time sequence signal, and the step length is adjusted: 806us, adjustment range: 806-65535 × 806 us; the delay register A adjusts the delay of the time sequence signal, and the step length is adjusted: 12.3ns, adjustment range: 0-65535 x 12.3 ns; the delay register B adjusts the delay of the timing signal, the adjustment step size 806us, the adjustable range: 806-65535 × 806 us; the 7 registers are arranged in real time on line, so that the frequency, the pulse width and the mutual time delay of the time sequence signals meet the actual running requirements of the accelerator.
The design and implementation principle of the integrated system architecture for the accelerator timing system and the rapid machine protection system for realizing the rapid machine protection system is as follows: according to the physical requirements of small and medium accelerators on a rapid machine protection system, the working state signals of all equipment are rapidly collected and monitored in real time, when a fault occurs, after rapid logic processing, time sequence and power permission signals for stopping the relevant equipment are timely sent out, and after the fault is confirmed to be not output any more, the time sequence and power permission signals of the relevant equipment are synchronously recovered. The specific operating scheme is as follows:
(1) the optical signal type input interface plug-in 3 can simultaneously/independently access 16 optical signals; the optical signal type output interface plug-in 2 can simultaneously/independently output 16 optical signals; the contact signal type input interface plug-in 5 can simultaneously/independently access 16 paths of contact type interlocking signals; the contact signal type output interface plug-in 6 can simultaneously/independently output 16 paths of contact interlocking signals; 3.3V/5V TTL signal input type interface plug-in can simultaneously/independently access 16 paths of TTL type interlocking signals; the 3.3V/5V TTL signal output type interface plug-in can simultaneously/independently output 16 TTL type signals.
(2) All optical input signals related to the interlocking equipment are connected into the optical signal type input interface plug-in 3 one by one; all optical output signals related to the interlocking equipment are connected out from the optical signal type output interface plug-in 2 one by one; all contact input signals related to the interlocking equipment are connected into a contact signal type input interface plug-in 5 one by one; all contact type output signals related to the interlocking equipment are connected out from a contact signal type output interface plug-in unit 6 one by one; all 3.3V/5V TTL input signals related to interlocking equipment are accessed into TTL signal type input interface plug-ins one by one; all 3.3V/5V TTL output signals related to the interlocking equipment are connected out from the TTL signal type output interface plug-in one by one.
(3) To improve operating efficiency, two beam-stop protection modes are defined and developed: a permanent beam stop protection mode and an instantaneous beam stop protection mode; the permanent beam-stopping protection mode is mainly used for timely sending out a timing sequence and power permission signal for stopping the related equipment by the system when the interlocking equipment has a permanent fault, synchronously recovering the timing sequence and power permission signal of the related equipment when no beam output is confirmed, and outputting beams after the fault of the equipment is repaired. The instantaneous beam-stopping protection mode is mainly aimed at high-voltage high-power equipment which can be quickly restored to a normal state after being instantaneously in a fault state due to high-voltage ignition, when the fault state occurs, a timing sequence and power permission signal for stopping the relevant equipment is sent out firstly, and after vacuum recovery, the timing sequence and power permission signal for synchronously restoring the relevant equipment is recovered, and beam discharging is continued.
(4) Aiming at the characteristic of contact type signal interlocking input, an onboard 100MHz clock is adopted to monitor in real time by taking 10ns as time particles, 2ms digital filtering is firstly carried out to determine whether the signal is a fault signal, and if the signal is determined, a permanent beam stopping protection mode is immediately executed; aiming at the interlocking input characteristic of optical signals, an onboard 100MHz clock is adopted to carry out real-time monitoring by taking 10ns as time particles, 100ns digital filtering is firstly carried out to confirm whether the signals are fault signals, if the signals are in fault, an instant beam stop protection mode is firstly executed, the fault duration is simultaneously monitored, if the fault duration does not exceed 5s, timing sequence and power permission signals of related equipment are synchronously restored, and if the fault duration exceeds 5s, a permanent beam stop protection mode is executed.
(5) The time overhead of the rapid machine protection system mainly comprises time consumed for accessing an interlocking signal transmission link, time consumed for logically judging the main logic plug-in 4, time consumed for executing interlocking signal transmission and the like. Taking an optical signal interlocking input signal as an example, the access transmission link mainly depends on the length of a multimode optical fiber from the local interlocking equipment to the optical signal type input interface plug-in 3; the transmission link is implemented mainly depending on the length of the multimode optical fiber from the optical signal type output interface card 2 to the interlock device involved in the stop sequence. The distribution of medium and small-sized accelerator equipment is moderate or small, the bending of optical fiber wiring is considered, the whole transmission optical fiber is about 200 meters, the total transmission link time is about 1us calculated by the optical fiber transmission speed of 5 ns/s; the whole signal link mainly comprises: optical signal → turn to TTL signal → plug-in VME J2 connector I/O interface → chassis VME J2 backplane slave connector → chassis VME J2 backplane master connector → main logic plug 4 signal logic process → main logic plug 4VME J2 connector I/O interface → chassis VME J2 backplane master connector → chassis VME J2 backplane slave connector → plug-in VME J2 connector I/O interface → turn to TTL signal → optical signal, etc., consuming approximately 1us of time; therefore, the total protection logic time overhead is about 2us, and compared with the ms-order consumed by the common PLC protection, the physical requirement of rapid machine protection can be realized.
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