CN110956998A - Memory testing device and system - Google Patents
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- CN110956998A CN110956998A CN201911211318.3A CN201911211318A CN110956998A CN 110956998 A CN110956998 A CN 110956998A CN 201911211318 A CN201911211318 A CN 201911211318A CN 110956998 A CN110956998 A CN 110956998A
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Abstract
The application provides a memory testing device and a system, and relates to the field of memories. The memory testing device comprises a register component, a command analysis component, a testing control component and a testing result acquisition component, wherein the register component is used for receiving a testing instruction sent by a testing machine and generating a control instruction according to the testing instruction, the command analysis component is used for analyzing the control instruction and generating a testing trigger signal so as to control the testing control component to work, the testing control component is used for generating a testing time sequence during working so as to test a memory to be tested, and the testing result acquisition component is used for acquiring a testing result of the memory to be tested and sending the testing result to the register component so as to enable the testing machine to determine whether the memory to be tested is qualified or not by reading the testing result. The memory testing device and the memory testing system have the advantage of improving testing efficiency.
Description
Technical Field
The present disclosure relates to the field of memories, and more particularly, to a memory testing apparatus and system.
Background
The memory is a memory component for storing data, instructions, and the like in the electronic computer. At present, due to the popularization of computers, memories are also widely used.
After the memory is manufactured, the memory typically needs to be tested to ensure that the memory is good for use.
At present, the test is realized for setting up the test environment through setting up on the test board to traditional test mode, however, when needs test, need just can set up the test environment through complicated debugging on the test board, consequently not high to the efficiency of software testing of memory.
Disclosure of Invention
An object of the application is to provide a memory testing device to when solving among the prior art and directly detecting the memory through the test board, problem that efficiency of software testing is not high.
Another objective of the present application is to provide a memory test system to solve the problem in the prior art that the test efficiency is not high when the memory is directly tested by the test machine.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
on one hand, the embodiment of the invention provides a memory testing device, which is applied to a memory testing system, the memory testing system also comprises a testing machine table and a memory to be tested, the memory testing device comprises a register component, a command analysis component, a testing control component and a testing result acquisition component, the register component is respectively connected with the testing machine table, the command analysis component and the testing result acquisition component, and the testing control component is respectively connected with the memory to be tested and the command analysis component;
the register component is used for receiving a test instruction sent by the test machine and generating a control instruction according to the test instruction;
the command analysis component is used for analyzing the control instruction and generating a test trigger signal so as to control the test control component to work;
the test control component is used for generating a test time sequence during working so as to test the memory to be tested;
the test result acquisition component is used for acquiring a test result of the memory to be tested and sending the test result to the register component, so that the test machine platform can determine whether the memory to be tested is qualified or not by reading the test result.
On the other hand, the embodiment of the invention also provides a memory test system, which comprises a test machine, a memory to be tested and the memory test device, wherein the test machine, the memory test device and the memory to be tested are sequentially connected, and the test machine is used for testing the memory to be tested through the memory test device.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a memory testing device and a system, wherein the memory testing system comprises a testing machine table and a memory to be tested, the memory testing device comprises a register component, a command analysis component, a testing control component and a testing result acquisition component, the register component is respectively connected with the testing machine table, the command analysis component and the testing result acquisition component, the testing control component is respectively connected with the memory to be tested and the command analysis component, and the testing result acquisition component is also connected with the register component. The device comprises a register component, a command analysis component, a test result acquisition component and a register component, wherein the register component is used for receiving a test instruction sent by a test machine and generating a control instruction according to the test instruction, the command analysis component is used for analyzing the control instruction and generating a test trigger signal to control the test control component to work, the test control component is used for generating a test time sequence during work so as to test a memory to be tested, the test result acquisition component is used for acquiring a test result of the memory to be tested and sending the test result to the register component so that the test machine can determine whether the memory to be tested is qualified or not by reading. On one hand, the memory is tested through the test instruction sent by the test machine, and then the test result in the memory test device is read through the test machine, so that the effect of testing the memory is achieved. On the other hand, the test machine table only needs to send a test instruction, so that a test environment does not need to be set up for complex debugging of the test machine table, and the effect of improving the test efficiency is achieved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram of a memory testing apparatus according to an embodiment of the present disclosure.
Fig. 2 is a schematic block diagram of another memory test apparatus according to an embodiment of the present disclosure.
Fig. 3 is a block diagram of a control register according to an embodiment of the present disclosure.
In the figure: 100-memory test device; 110-a register component; 111-configuration registers; 112-a control register; 1121-soft reset register; 1122-test trigger register; 113-a status register; 114-a test result register; 120-a command parsing component; 130-test control components; 131-an all-zero test control component; 132-word line and bit line test control components; 133-pre-programming a test control component; 140-a test result acquisition component; 200-a test machine; 300-memory to be tested.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
First embodiment
As described in the background, existing memories typically require testing after production. For example, OTP (OneTime programmable) memory, generally, the test that the integrated OTP chip needs to do in the stage of machine test includes:
1. a full zero Test (Blank Check Test) for detecting whether the memory space of the chip is all zero, and if the memory space is all zero, the chip should be divided into good chips; if there is a bit detected to be 1, then the chip should be broken into garbage.
2. Word Line and Bit Line Integrity Test (Word Line and Bit Line Integrity Test) is performed to check the Integrity of Word lines and Bit lines of the OTP memory space and whether the corresponding peripheral circuits have serious defects.
3. A Pre-program Test (Pre-program Test) is performed to screen out chips with serious defects in the programmed circuit before they are actually programmed.
Because the traditional OTP chip does not contain an all-zero test hardware circuit, a word line and bit line integrity test circuit and a pre-programming test circuit, a complex debugging and testing environment is required to be built on a testing machine to realize the testing functions of the three, and the efficiency of screening the OTP chip is low. Meanwhile, the pins of the tested OTP chip are directly connected with the test machine table, so that the pins of the OTP chip can be damaged or adversely affected in the test process, and the performance of the OTP chip is reduced.
In view of this, embodiments of the present invention provide a memory testing apparatus, so as to achieve the functions of testing a hardware circuit, a word line and bit line integrity test circuit, and a pre-programmed test circuit through the hardware circuit, and simplify a test instruction by simulating a CPU register access manner through a testing machine, and avoid building a complex test environment, thereby greatly improving test efficiency, and avoiding the testing machine from directly contacting pins of a memory, so as to achieve the purpose of protecting the pins of the memory.
The following provides an exemplary description of a memory test apparatus according to an embodiment of the present invention:
first, referring to fig. 1, it should be noted that the memory test apparatus 100 is applied to a memory test system, and the memory test system further includes a test machine 200 and a memory 300 to be tested. The testing machine 200 is a machine for sending a testing instruction, and the memory 300 to be tested is a memory to be tested after production is completed.
It should be noted that the memory testing apparatus 100 is respectively connected to the testing machine 200 and the memory 300 to be tested, so that the testing machine 200 tests the memory 300 to be tested through the memory testing apparatus 100. In addition, in the testing process, a plurality of memories 300 to be tested may be sequentially tested by the memory testing apparatus 100, that is, the memories 300 to be tested are tested one by one, or the memories 300 to be tested may be divided into a plurality of batches, each batch includes a plurality of memories, and the memories are tested in batches by the memory testing apparatus 100, that is, a plurality of memories are tested at the same time, which is not limited in this application.
As a possible implementation manner of the present application, the memory testing apparatus 100 includes a register element 110, a command parsing element 120, a test control element 130, and a test result obtaining element 140, where the register element 110 is connected to the testing machine 200, the command parsing element 120, and the test result obtaining element 140, the test control element 130 is connected to the memory 300 to be tested and the command parsing element 120, and the test result obtaining element 140 is further connected to the register element 110.
In the process of testing the memory, firstly, the register component 110 is used for receiving a test instruction sent by the test machine 200, a control instruction is generated according to the test instruction, then the command analysis component 120 is used for analyzing the control instruction, and a test trigger signal is generated so as to control the test control component 130 to work; and the test control component 130 generates a test timing sequence during operation, so as to test the memory 300 to be tested; finally, the test result of the memory 300 to be tested is obtained by the test result obtaining component 140, and the test result is sent to the register component 110, so that the test machine 200 can determine whether the memory 300 to be tested is qualified by reading the test result.
In a first aspect, the present application utilizes a hardware circuit of the memory testing apparatus 100 to test the memory, that is, the memory is tested by a test instruction sent by the testing machine 200, and then a test result in the memory testing apparatus 100 is read by the testing machine 200, so as to achieve an effect of testing the register. In a second aspect, since the memory testing apparatus 100 provided in the present application is connected to the memory to be tested and the testing machine 200 respectively, direct contact between the testing machine and the memory pins is avoided, and possible damage and adverse effects of the memory pins in the testing process due to the testing machine 200 are avoided. In the third aspect, since the test machine 200 only needs to send a test instruction, the test machine 200 does not need to be debugged and tested in a complicated manner, so that the test efficiency is improved, and the test cost is saved.
In addition, referring to fig. 2, as a possible implementation manner of the present application, the testing control component 130 includes an all-zero testing control component 131, a word line and bit line testing control component 132, and a pre-programmed testing control component 133, and the all-zero testing control component 131, the word line and bit line testing control component 132, and the pre-programmed testing control component 133 are respectively connected to the command parsing component 120 and the memory to be tested. That is, the memory test apparatus 100 according to the present invention implements a test function for a memory by a hardware circuit. Through the simple configuration of the test machine 200 to the memory test device 100, any one of the all-zero test control component 131, the word line and bit line test control component 132, and the pre-programmed test control component 133 in the memory test device 100 can be triggered to operate, so as to complete the specified test, and read the test result through the test machine 200.
As an alternative implementation manner, the register element 110 includes a configuration register 111, a control register 112, a status register 113, and a test result register 114, wherein the configuration register 111 is used for calculating, according to a clock sent by the test machine 200, a time corresponding to the flipping of the test control element 130 including the all-zero test control element 131, the word line and bit line test control element 132, and the pre-programmed test control element 133. That is, in the present application, in order to avoid confusion during the testing process, only one of the all-zero test control module 131, the word line and bit line test control module 132, and the pre-programmed test control module 133 can operate at a time, for example, for a memory, first, the all-zero test control module 131 is used to test whether the storage space is all zero, then the word line and bit line test control module 132 is used to test the integrity of the word line and bit line and whether the corresponding peripheral circuit has defects, and finally the pre-programmed test control module 133 is used to test whether the programmed circuit has defects. The configuration register 111 can calculate the time for each component to flip, and then determine what type of test the memory test device 100 is performing at a certain point in time.
The configuration register 111 is further configured to configure the all-zero test control component 131, the word line and bit line test control component 132, or the pre-programmed test control component 133 as a target control component, so as to achieve an effect of enabling the target control component to be in a state to be operated, where the command parsing component 120 controls the target control component in the state to be operated after generating the test trigger signal. For example, for a batch of memories, all-zero testing is required, followed by word line and bit line testing, and finally pre-programmed testing. The configuration register 111 will configure the all-zero test control component 131 to operate first, configure the word line and bit line test control component 132 to operate after the all-zero test is normal, and configure the pre-programmed test control component 133 to operate finally after the word line and bit line test is normal. Meanwhile, since the configuration register 111 can flip the corresponding time of each control component, it can accurately configure which control component should operate at each time point. For example, the time corresponding to the flipping of the all-zero test control component 131 is 1S, the time corresponding to the flipping of the word line and bit line test control component 132 is 2S, and the time corresponding to the flipping of the pre-programmed test control component 133 is 3S, after receiving the test instruction, the configuration register 111 configures the all-zero test control component 131 to be in a state to be operated, so that after the command parsing component generates the test trigger signal, the all-zero test control component 131 is controlled to operate; after receiving the test instruction by 1S, the configuration register 111 configures the word line and bit line test control component 132 to be in a state to be operated, so that after the command analysis component generates the test trigger signal, the word line and bit line test control component 132 is controlled to operate; 3S after receiving the test instruction, the configuration register 111 configures the pre-programmed test control component 133 to be in a state to be operated, so that the pre-programmed test control component 133 is controlled to operate after the command parsing component generates the test trigger signal.
The control register 112 is used for resetting the memory testing apparatus 100 and generating a test start signal, so that the command parsing component 120 controls the components to be operated according to the test start signal.
As a possible implementation manner of the present application, please refer to fig. 3, the control register 112 includes a soft reset register 1121 and a test trigger register 1122. The soft reset register 1121 is used for resetting the memory test apparatus 100; that is, when the memory test is required, the soft reset register 1121 resets the memory test apparatus 100 provided by the present invention, and completes the reset operation before the test, so as to reduce the error occurring in the test process.
After the configuration register 111 is configured, the test trigger register 1122 controls the all-zero test control element 131, the word line and bit line test control element 132, or the pre-programmed test control element 133 to operate when receiving the test command sent by the test machine 200. The test instruction according to the present invention refers to the internal test instruction that the test machine 200 writes the test trigger register 1122 through the bus, and then triggers the memory test device 100 to start executing. For example, when the test trigger register 1122 is not triggered, the value stored therein is 0, and when the test machine 200 writes 1 in the trigger register, it indicates that the test trigger register 1122 has been triggered, and the test is started.
The status register 113 is used to record whether the testing of the all-zero test control component 131, the word line and bit line test control component 132, or the pre-programmed test control component 133 is complete. That is, the all-zero test control component 131, the word line and bit line test control component 132, and the pre-programmed test control component 133, send corresponding test completion signals to the status register 113 after the test is completed. For example, when the test is not completed, the all-zero test control component 131, the word line and bit line test control component 132, or the pre-programmed test control component 133 sends a low level signal to the status register 113, and the status register 113 stores a value of 0 at this time; when the test is completed, the all-zero test control component 131, the word line and bit line test control component 132, or the pre-programmed test control component 133 sends a high signal to the status register 113, and the status register 113 stores a value of 1. The test tool 200 can determine whether the testing of the all-zero test control element 131, the word line and bit line test control element 132, or the pre-programmed test control element 133 is complete by reading the value stored in the status register 113.
The test result register 114 is used for storing the test result acquired by the test result acquiring component 140. So that the testing machine 200 can query the bus to determine whether the three tests of the memory pass or not by the testing machine 200 passing the test result. Since the test circuit is used to test the slices of the memory during the testing of the machine 200, the present invention provides test results that only indicate whether the test results pass or not. For example, when the test result fails, the test result stored in the test result register 114 is 0; when the test result passes, the test result stored in the test result register 114 is 1.
It is understood that the test station 200 will always read the value in the status register 113 to determine whether the test is completed, and when the value in the status register 113 is 1 (i.e. indicating that the test is completed), the test station 200 will continue to read the value in the test result register 114 to determine whether the memory under test is a good chip. As an implementation of the present application, when all three tests pass, the test result stored in the test result register 114 is 1, and the memory is determined to be a good chip. Of course, as another implementation of the present application, the memory testing apparatus 100 may also test only one or two functions, for example, only pre-programming the memory to test if it is determined that the total storage space of the memory is zero and the sub-lines and the bit lines are completed, and then when the programming is passed, the test result stored in the test result register 114 is 1.
The command parsing component 120 is configured to complete parsing of the corresponding test command according to the value of the register configured by the test machine 200, i.e. the control instruction according to the present invention refers to the value of each register in the register component 110. The command parsing component 120 generates the test trigger signals of the corresponding three test circuits (i.e. the three control components) according to the value of the test trigger register 1122, so that one of the three test circuits starts to operate. Wherein the specifically operating test circuit is configured via a configuration register 111.
The following is a description of the specific operation of the all-zero test control component 131, the word line and bit line test control component 132, and the pre-programmed test control component 133:
after the command parsing component 120 generates the test trigger signal, any one of the all-zero test control component 131, the word line and bit line test control component 132 and the pre-programmed test control component 133 is controlled to operate according to the test trigger signal.
When the all-zero test control component 131 works, the all-zero test control component 131 is used for generating a first test timing sequence so as to perform an all-zero test on the memory 300 to be tested; when the word line and bit line test control component 132 is operating, the word line and bit line test control component 132 is configured to generate a second test timing sequence to perform an integrity test on the memory 300 to be tested; when the pre-programmed test control component 133 is operating, the pre-programmed test control component 133 is configured to generate a third test timing sequence for performing the pre-programmed test on the memory under test 300.
As an alternative implementation manner of the present application, the memory 300 to be tested includes a plurality of memory cells, the all-zero test control component 131 includes a first state machine and a corresponding control circuit, the word line and bit line test control component 132 includes a second state machine and a corresponding control circuit, and the pre-programmed test control component 133 includes a third state machine and a corresponding control circuit. The first state machine, the second state machine or the third state machine is used for sequentially generating the test time sequence and the test address of each memory unit until the test passing signals of all the memory units are received or the test failing signal of any one memory unit is received.
Also, the test result acquisition component 140 is connected to the all-zero test control component 131, the word line and bit line test control component 132, and the pre-programmed test control component 133, respectively. Taking the all-zero test control component 131 as an example for explanation, when the command parsing component 120 generates the test trigger signal to control the all-zero test control component 131 to start working, the all-zero test control component 131 generates a timing sequence of memory pins meeting an all-zero test, the tested memory works according to the test timing sequence and outputs feedback information, when the feedback information meets expectations (that is, the feedback information is a preset value), the test result obtaining component 140 generates a test passing signal and sends the test passing signal to the first state machine, and the first state machine generates a next test address according to the test passing signal until the test passing signals of all the memory cells are received or the test failing signal of any memory cell is received.
That is, the all-zero test control component 131 sequentially performs the all-zero test on each memory cell in the memory, and the all-zero test control component 131 generates a corresponding test address for each memory cell, for example, when the all-zero test control component 131 tests one of the memory cells, the generated test address is 1, and a corresponding test timing sequence is generated at the same time. When the feedback result output by the memory according to the test timing sequence and the test address is all 0, it indicates that all the storage spaces corresponding to the storage unit are zero, and the test result obtaining component 140 determines that the current address passes the test after obtaining the feedback information, and at this time, the test result obtaining component 140 generates a test passing signal and sends the test passing signal and the current test address together to the all-zero test control component 131.
When the all-zero test control module 131 receives the test pass signal and the current test address, it automatically generates the next test address, for example, the test address is 5, and continues to perform the above operations. Until all the memory cells of the whole memory are tested, or memory cells with failed test results appear.
If all the memory spaces have been tested, the first state machine returns to the idle state, and at this time, the state register 113 receives a corresponding signal, so that the state register 113 is set to 1, which indicates that the test is completed, and the value of the test result register 114 is set to 1, which indicates that the test result passes. It should be noted that, if a test result of a certain test address fails during the test process, the all-zero test is stopped, the first state machine returns to the idle state, the state register 113 is set to 1, which indicates that the test is completed, meanwhile, the test result of the test result register 114 is set to 0, which indicates that the test fails, and after the test machine 200 queries the value of the register, the all-zero test is completed, and the test result fails.
It can be understood that the byte and bit line test control component 130 and the pre-programmed test component are implemented in a manner similar to the implementation manner of the all-zero test control component 131, and all test spaces are tested to pass the test result, that is, the second state machine and the third state machine respectively generate the test timing sequence and the test address in sequence and test the memory cells in the memory one by one. If the test procedure finds that a certain memory address fails, the test is stopped, the test status register 113 is set to 1 to indicate that the test is completed, and the test result register 114 is set to 0 to indicate that the test fails. The three realize the memory test time sequence meeting the respective test requirements through hardware circuits. That is, the memory test apparatus 100 provided in the present invention completes the test of different functions of the memory by generating the control timing sequence satisfying the pins.
As a possible implementation manner of the present application, in order to complete testing of the memory more efficiently, the first state machine, the second state machine, or the third state machine generates the test address in an automatic increment manner. For example, when the first state machine tests the first memory cell, the test address generated is 1, the test address generated when testing the second memory cell is 2, the test address generated when testing the second memory cell is 3, and so on.
Meanwhile, optionally, the state register 113 is further configured to store values of the first state machine, the second state machine, and the third state machine, so as to determine jump states of the first state machine, the second state machine, and the third state machine. For example, when the first state machine is operating, after the test of the first storage space is completed, the value of the first state machine stored in the state register 113 is 1; when the test of the first storage space is completed, the value of the first state machine stored in the state register 113 is 11; when the test of the third storage space is completed, the value of the first state machine stored in the state register 113 is 111, and so on. Further, the test machine 200 can read the value in the status register 113 to determine which status the state machine body jumps to, which is more convenient.
Optionally, the test result obtaining component 140 includes a test result processing component and a test result determining component, where the test result processing component implements simple processing on the test result, and since the 3-bit physical address implemented in the embodiment of the present application corresponds to the 1-bit logical address, the result output by the physical address needs to be cached and spliced, so that the value of the 1-time logical address is read at a time.
The test result judging component judges whether the memory output meets the expectation or not according to the memory output, if so, a corresponding signal is generated and used for jumping to generate a next test address by the state machine of each test component, for example, for an all-zero test, the preset value is 0000, if the memory output is 0000, the output of the memory unit meets the expectation, and the test of the memory unit passes. If not desired, for example, the output of the memory is 0001 or 0010, the test result determination component may generate a test fail signal and send the test fail signal to the test result register 114.
As an alternative implementation manner of the present application, when the test fails, the test result determining component may set the status register 113 to 1, and set the test result register 114 to 0, which indicates that the test is completed and the test result is a test failure. When all the memory cells pass the test, the test result determination component sets the test result register 114 to 1.
In conclusion, the memory testing device provided by the application realizes the testing of different functions of the memory through the hardware circuit, thereby simplifying the machine testing environment, improving the testing efficiency through the testing vector and saving the testing cost. Meanwhile, the test machine completes the control of the test and the query of the test result by accessing the register, the operation is simple, the judgment of the test machine on the test result is simplified, and the test machine is prevented from directly contacting with the pins of the memory, so that the pins of the memory are protected, and the pins of the memory are prevented from being damaged or badly influenced by the test machine.
Second embodiment
Referring to fig. 1 and fig. 2, an embodiment of the invention further provides a memory test system, which includes a test machine 200, a memory 300 to be tested, and the memory test apparatus 100 according to the first embodiment, wherein the test machine 200, the memory test apparatus 100, and the memory 300 to be tested are sequentially connected, and the test machine 200 is used for testing the memory 300 to be tested through the memory test apparatus 100. Since the hardware and the corresponding operation principle of the memory test apparatus 100 have been described in detail in the first embodiment, this embodiment will not be described again.
In summary, the present invention provides a memory testing device and system, the memory testing system further includes a testing machine and a memory to be tested, the memory testing device includes a register component, a command parsing component, a test control component, and a test result obtaining component, the register component is respectively connected to the testing machine, the command parsing component, and the test result obtaining component, the test control component is respectively connected to the memory to be tested and the command parsing component, and the test result obtaining component is further connected to the register component. The device comprises a register component, a command analysis component, a test result acquisition component and a register component, wherein the register component is used for receiving a test instruction sent by a test machine and generating a control instruction according to the test instruction, the command analysis component is used for analyzing the control instruction and generating a test trigger signal to control the test control component to work, the test control component is used for generating a test time sequence during work so as to test a memory to be tested, the test result acquisition component is used for acquiring a test result of the memory to be tested and sending the test result to the register component so that the test machine can determine whether the memory to be tested is qualified or not by reading. On one hand, the memory is tested through the test instruction sent by the test machine, and then the test result in the memory test device is read through the test machine, so that the effect of testing the register is achieved. On the other hand, the test machine table only needs to send a test instruction, so that a test environment does not need to be set up for complex debugging of the test machine table, and the effect of improving the test efficiency is achieved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A memory testing device is characterized by being applied to a memory testing system, wherein the memory testing system further comprises a testing machine table and a memory to be tested, the memory testing device comprises a register component, a command analysis component, a testing control component and a testing result acquisition component, the register component is respectively connected with the testing machine table, the command analysis component and the testing result acquisition component, and the testing control component is respectively connected with the memory to be tested and the command analysis component;
the register component is used for receiving a test instruction sent by the test machine and generating a control instruction according to the test instruction;
the command analysis component is used for analyzing the control instruction and generating a test trigger signal so as to control the test control component to work;
the test control component is used for generating a test time sequence during working so as to test the memory to be tested;
the test result acquisition component is used for acquiring a test result of the memory to be tested and sending the test result to the register component, so that the test machine platform can determine whether the memory to be tested is qualified or not by reading the test result.
2. The memory test apparatus of claim 1, wherein the test control components include an all-zero test control component, a word line and bit line test control component, and a pre-programmed test control component, the all-zero test control component, the word line and bit line test control component, and the pre-programmed test control component each being connected to the command parsing component, the memory to be tested, respectively; wherein;
the command analysis component is used for generating a test trigger signal so as to control any one of the all-zero test control component, the word line and bit line test control component and the pre-programmed test control component to work;
when the all-zero test control assembly works, the all-zero test control assembly is used for generating a first test time sequence so as to carry out all-zero test on the memory to be tested;
when the word line and bit line test control assembly works, the word line and bit line test control assembly is used for generating a second test time sequence so as to carry out integrity test on the memory to be tested;
when the pre-programmed test control assembly works, the pre-programmed test control assembly is used for generating a third test time sequence so as to carry out the pre-programmed test on the memory to be tested.
3. The memory testing apparatus of claim 2, wherein the memory under test comprises a plurality of memory cells, the all-zero test control component comprises a first state machine, the word line and bit line test control component comprises a second state machine, and the pre-programmed test control component comprises a third state machine;
the first state machine, the second state machine or the third state machine is used for sequentially generating a test time sequence and a test address of each memory unit until a test passing signal of all the memory units is received or a test failing signal of any one memory unit is received.
4. The memory test apparatus of claim 3, wherein the test result acquisition component is further connected to the all-zero test control component, the word line and bit line test control component, and the pre-programmed test control component, respectively;
the first state machine, the second state machine or the third state machine is used for generating a test time sequence and a test address of any one memory cell;
the test result acquisition component is used for acquiring feedback information output by the memory to be tested according to the test time sequence and the test address;
when the feedback information is a preset value, the test result acquisition component generates a test passing signal and sends the test passing signal to the first state machine, the second state machine or the third state machine;
the first state machine, the second state machine or the third state machine is used for generating a next test address according to the test pass signal until the test pass signals of all the memory units are received or the test fail signal of any memory unit is received.
5. The memory test apparatus of claim 4, wherein the test result obtaining component is further configured to generate a test success signal to the register component when all memory cells have passed the test;
or when any one memory cell fails to pass the test, generating a test failure signal and sending the test failure signal to the register component.
6. The memory testing apparatus of claim 3, wherein the first state machine, the second state machine, or the third state machine generates a test address in an auto-increment manner.
7. The memory test apparatus of claim 1, wherein the register components include a configuration register, a control register, a status register, and a test result register, the test control components include an all-zero test control component, a word line and bit line test control component, and a pre-programmed test control component;
the configuration register is used for calculating the time corresponding to the overturning of the all-zero test control assembly, the word line and bit line test control assembly and the pre-programmed test control assembly according to the clock sent by the test machine, and configuring the all-zero test control assembly, the word line and bit line test control assembly or the pre-programmed test control assembly as a target control assembly so as to enable the target control assembly to be in a state to be operated;
the control register is used for resetting the memory testing device and generating a testing start signal so that the command analysis component controls the target control component to work according to the testing start signal;
the state register is used for recording whether the testing of the all-zero testing control assembly, the word line and bit line testing control assembly or the pre-programmed testing control assembly is finished or not;
the test result register is used for storing the test result obtained by the test result obtaining component.
8. The memory test apparatus of claim 7, wherein the all-zero test control component comprises a first state machine, the word line and bit line test control component comprises a second state machine, and the pre-programmed test control component comprises a third state machine;
the state register is further configured to store values of the first state machine, the second state machine, and the third state machine to determine jump states of the first state machine, the second state machine, and the third state machine.
9. The memory test apparatus of claim 7, wherein the control register comprises a soft reset register and a test trigger register;
the soft reset register is used for resetting the memory test device;
the test trigger register is used for controlling the all-zero test control assembly, the word line and bit line test control assembly or the pre-programmed test control assembly to work when receiving a test instruction sent by the test machine.
10. A memory test system, comprising a test machine, a memory to be tested and the memory test device as claimed in any one of claims 1 to 9, wherein the test machine, the memory test device and the memory to be tested are connected in sequence, and the test machine is configured to test the memory to be tested through the memory test device.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112179405A (en) * | 2020-09-01 | 2021-01-05 | 河北汉光重工有限责任公司 | Detection system for testing ship air intake and exhaust system |
| WO2023019658A1 (en) * | 2021-08-16 | 2023-02-23 | 长鑫存储技术有限公司 | Memory testing method, device and apparatus |
| CN118859784A (en) * | 2024-07-02 | 2024-10-29 | 湖南开鸿智谷数字产业发展有限公司 | Control logic self-learning method, control method, device, storage medium and product |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH095402A (en) * | 1995-06-22 | 1997-01-10 | Advantest Corp | Semiconductor memory test device |
| CN101458971A (en) * | 2008-12-02 | 2009-06-17 | 炬力集成电路设计有限公司 | Test system and method for built-in memory |
| US20110185239A1 (en) * | 2007-09-28 | 2011-07-28 | Oki Semiconductor Co., Ltd. | Semiconductor testing apparatus and method |
| CN102183726A (en) * | 2011-03-16 | 2011-09-14 | 建荣集成电路科技(珠海)有限公司 | Field programmable gate array (FPGA)-based integrated circuit chip testing system and method |
| CN103093829A (en) * | 2011-10-27 | 2013-05-08 | 迈实电子(上海)有限公司 | Memory test system and memory test method |
| CN104200846A (en) * | 2014-07-23 | 2014-12-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN105989900A (en) * | 2015-03-05 | 2016-10-05 | 展讯通信（上海）有限公司 | System on chip and measurement of lowest working voltage of embedded memory of system on chip |
| CN106024066A (en) * | 2016-05-06 | 2016-10-12 | 北京润科通用技术有限公司 | SRAM detection method and system |
| CN110058147A (en) * | 2019-05-27 | 2019-07-26 | 眸芯科技（上海）有限公司 | Chip test system and method based on fpga |
| CN110289041A (en) * | 2019-06-25 | 2019-09-27 | 浙江大学 | A memory detection device combining BIST and ECC in a system chip |
-
2019
- 2019-12-02 CN CN201911211318.3A patent/CN110956998B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH095402A (en) * | 1995-06-22 | 1997-01-10 | Advantest Corp | Semiconductor memory test device |
| US20110185239A1 (en) * | 2007-09-28 | 2011-07-28 | Oki Semiconductor Co., Ltd. | Semiconductor testing apparatus and method |
| CN101458971A (en) * | 2008-12-02 | 2009-06-17 | 炬力集成电路设计有限公司 | Test system and method for built-in memory |
| CN102183726A (en) * | 2011-03-16 | 2011-09-14 | 建荣集成电路科技(珠海)有限公司 | Field programmable gate array (FPGA)-based integrated circuit chip testing system and method |
| CN103093829A (en) * | 2011-10-27 | 2013-05-08 | 迈实电子(上海)有限公司 | Memory test system and memory test method |
| CN104200846A (en) * | 2014-07-23 | 2014-12-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN105989900A (en) * | 2015-03-05 | 2016-10-05 | 展讯通信（上海）有限公司 | System on chip and measurement of lowest working voltage of embedded memory of system on chip |
| CN106024066A (en) * | 2016-05-06 | 2016-10-12 | 北京润科通用技术有限公司 | SRAM detection method and system |
| CN110058147A (en) * | 2019-05-27 | 2019-07-26 | 眸芯科技（上海）有限公司 | Chip test system and method based on fpga |
| CN110289041A (en) * | 2019-06-25 | 2019-09-27 | 浙江大学 | A memory detection device combining BIST and ECC in a system chip |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112179405A (en) * | 2020-09-01 | 2021-01-05 | 河北汉光重工有限责任公司 | Detection system for testing ship air intake and exhaust system |
| WO2023019658A1 (en) * | 2021-08-16 | 2023-02-23 | 长鑫存储技术有限公司 | Memory testing method, device and apparatus |
| CN118859784A (en) * | 2024-07-02 | 2024-10-29 | 湖南开鸿智谷数字产业发展有限公司 | Control logic self-learning method, control method, device, storage medium and product |
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|---|---|
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