CN110931515B - Array substrate, display panel and display device - Google Patents

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate includes a display area and a stepped area; a substrate; a plurality of data lines located in the display area; the plurality of data lines extend along a second direction and extend along the arrayed in the first direction; and a plurality of fan-out traces located in the step area, the fan-out traces are electrically connected to the data lines, and used for providing data signals to the data lines; the plurality of fan-out traces include: The first fan-out trace located in the first metal layer, the second fan-out trace located in the second metal layer, and the third fan-out trace located in the third metal layer; in the direction perpendicular to the substrate, the first fan-out trace is The second metal layer is located on the side of the first metal layer away from the substrate, the third metal layer is located on the side of the second metal layer away from the first metal layer, and the first fan out The line does not overlap with the vertical projection of the second fan-out trace on the substrate. The present invention can reduce the frame and increase the screen ratio.

Description

Array substrate, display panel and display device

technical field

The present invention relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.

Background technique

With the development of science and technology and the progress of society, people's dependence on the exchange and transmission of information is increasing day by day. As the main carrier and material basis for information exchange and transmission, display devices have become the research focus of many scientists.

Now, display panels and display devices with a high screen-to-body ratio and narrow bezels are increasingly becoming a trend. However, many fan-out traces need to be set in the step area, so that the width of the step area cannot be reduced.

SUMMARY OF THE INVENTION

The present invention provides an array substrate, a display panel and a display device, so as to reduce the frame and increase the screen ratio.

In a first aspect, an embodiment of the present invention provides an array substrate, including a display area and a stepped area;

substrate;

a plurality of data lines located in the display area; the plurality of data lines extend along the second direction and are arranged along the first direction;

and a plurality of fan-out traces located in the step area, the fan-out traces are electrically connected to the data lines, and used for providing data signals to the data lines; the plurality of fan-out traces include a first metal layer The first fan-out trace, the second fan-out trace located in the second metal layer, and the third fan-out trace located in the third metal layer; in the direction perpendicular to the substrate, the second metal layer is located in the The first metal layer is located on a side away from the substrate, the third metal layer is located at a side of the second metal layer away from the first metal layer, and the first fan-out trace is connected to the first metal layer. The vertical projections of the two fan-out traces on the substrate do not overlap.

In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate described in the first aspect.

In a third aspect, an embodiment of the present invention provides a display device, including the display panel described in the second aspect.

In the array substrate provided by the embodiment of the present invention, a plurality of fan-out traces are respectively disposed on the first metal layer, the second metal layer, and the third metal layer, compared to the fact that the plurality of fan-out traces are disposed in one metal layer or two metals In terms of layers, the spacing between two adjacent fan-out traces can be reduced, thereby reducing the area occupied by the fan-out traces in the step area, reducing the width of the step area, reducing the frame, and increasing the screen-to-screen ratio. In addition, setting the first fan-out wiring and the second fan-out wiring to not overlap can also prevent the first fan-out wiring and the second fan-out wiring from generating overlapping capacitance on the basis of reducing the frame, thereby preventing the first fan-out wiring Increased load on outgoing traces and second fanout traces.

Description of drawings

FIG. 1 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present invention;

Fig. 2 is the enlarged structural schematic diagram of S1 area in Fig. 1;

Fig. 3 is a schematic cross-sectional structure along the AA' direction in Fig. 2;

Fig. 4 is the cross-sectional structure schematic diagram along BB' direction in Fig. 1;

FIG. 5 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention;

FIG. 6 is a schematic top-view structure diagram of another array substrate according to an embodiment of the present invention;

FIG. 7 is a schematic top-view structural diagram of another array substrate according to an embodiment of the present invention;

8 is a schematic top-view structural diagram of a fan-out wiring in an array substrate according to an embodiment of the present invention;

9 is a schematic top-view structural diagram of a fan-out trace in another array substrate according to an embodiment of the present invention;

FIG. 10 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention;

FIG. 11 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention;

FIG. 12 is a schematic top-view structure diagram of another array substrate according to an embodiment of the present invention;

FIG. 13 is a schematic top-view structural diagram of another array substrate according to an embodiment of the present invention;

FIG. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

1 is a schematic top view of an array substrate according to an embodiment of the present invention, FIG. 2 is an enlarged schematic view of the S1 area in FIG. 1 , FIG. 3 is a schematic cross-sectional structure along the direction AA′ in FIG. 2 , and FIG. A schematic cross-sectional structure diagram in the direction of BB′ in FIG. 1 , referring to FIGS. 1 , 2 , 3 and 4 , the array substrate includes a display area A1 and a step area A2 . The array substrate includes a substrate 10 , a plurality of data lines 22 and a plurality of fan-out traces 30 . The plurality of data lines 22 are located in the display area A1, and the plurality of data lines 22 extend along the second direction and are arranged along the first direction. A plurality of fan-out traces 30 are located in the step area A2 , and the fan-out traces 30 are electrically connected to the data lines 22 for providing data signals to the data lines 22 . The plurality of fan-out traces 30 include a first fan-out trace 31 located in the first metal layer M1, a second fan-out trace 32 located in the second metal layer M2, and a third fan-out trace 33 located in the third metal layer M3. In the direction perpendicular to the substrate 10, the second metal layer M2 is located on the side of the first metal layer M1 away from the substrate 10, the third metal layer M3 is located on the side of the second metal layer M2 away from the first metal layer M1, Moreover, the vertical projections of the first fan-out traces 31 and the second fan-out traces 32 on the substrate 10 do not overlap.

It should be noted that the actual array substrate includes a large number of data lines 22 and a large number of fan-out lines 30 , and the numbers of data lines 22 and fan-out lines 30 shown in FIG. limit.

In the array substrate provided by the embodiment of the present invention, a plurality of fan-out traces are respectively disposed on the first metal layer, the second metal layer, and the third metal layer, compared to the fact that the plurality of fan-out traces are disposed in one metal layer or two metals In terms of layers, the spacing between two adjacent fan-out traces can be reduced, thereby reducing the area occupied by the fan-out traces in the step area, reducing the width of the step area, reducing the frame, and increasing the screen-to-screen ratio. In addition, setting the first fan-out wiring and the second fan-out wiring to not overlap can also prevent the first fan-out wiring and the second fan-out wiring from generating overlapping capacitance on the basis of reducing the frame, thereby preventing the first fan-out wiring Increased load on outgoing traces and second fanout traces.

Optionally, referring to FIG. 1 , FIG. 3 and FIG. 4 , the array substrate further includes a plurality of scan lines 21 , the plurality of scan lines 21 are located in the display area A1 , and the plurality of scan lines 21 extend along the first direction and are arranged along the second direction . The scan lines 21 are located in the first metal layer M1, and the second metal layer M2 is located between the first metal layer M1 and the film layer where the data lines 22 are located. In the embodiment of the present invention, the first fan-out traces 31 and the scan lines 21 are on the same layer, the second fan-out traces 32 are located between the first fan-out traces 31 and the film layer where the data lines 22 are located, and the first fan-out traces 31 and the The distance between the two fan-out traces 32 is relatively close, so it is especially necessary to set the first fan-out trace 31 and the second fan-out trace 32 to not overlap to prevent the first fan-out trace 31 and the second fan-out trace 32 from overlapping capacitance.

Optionally, referring to FIG. 3 and FIG. 4 , the first metal layer M1 and the second metal layer M2 use the same material. Then the first fan-out traces 31 located in the first metal layer M1 and the second fan-out traces 32 located in the second metal layer M2 are made of the same material, and the first fan-out traces 31 and the second fan-out traces 32 have the same resistance Therefore, the difference between the voltage drops on the first fan-out trace 31 and the second fan-out trace 32 is reduced, so that the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 are the same or similar degree of attenuation to ensure display uniformity.

Optionally, referring to FIG. 2 and FIG. 3 , the line width of the first fan-out wiring 31 is equal to the line width of the second fan-out wiring 32 . The line width of the first fan-out trace 31 is the width of the first fan-out trace 31 perpendicular to its extension direction, and the line width of the second fan-out trace 32 is the width of the second fan-out trace 32 perpendicular to its extension direction. width. In the embodiment of the present invention, the first fan-out trace 31 and the second fan-out trace 32 are made of the same material, and the line width of the first fan-out trace 31 is equal to that of the second fan-out trace 32, thereby further reducing the The difference between the voltage drops on the first fan-out trace 31 and the second fan-out trace 32 is reduced, so that the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 have the same or similar degree of attenuation, to ensure display uniformity.

1 , a plurality of scan lines 21 and a plurality of data lines 22 intersect to form a plurality of sub-pixels 110, and the plurality of sub-pixels 110 are arranged in an array in the display area A1. One end of the fan-out trace 30 is electrically connected to the data line 22 , and the other end of the fan-out trace 30 is electrically connected to the driver chip 40 , and the driver chip 40 is bound to the step area A2 of the array substrate. The driver chip 40 provides data signals to the data lines 22 through the fan-out traces 30 .

Exemplarily, as shown in FIGS. 1 , 2 , and referring to FIGS. 3 and 4 , the array substrate further includes a buffer layer 11 , a gate insulating layer 12 , a first dielectric layer 13 , a second The dielectric layer 14 , the first organic layer 15 , the planarization layer 16 and the pixel defining layer 17 . The array substrate further includes a pixel driving circuit and a light-emitting unit 70 . The pixel driving circuit is electrically connected to the light-emitting unit 70 , and the pixel driving circuit is used to provide driving voltage or driving current for the light-emitting unit 70 . The pixel driving circuit includes a thin film transistor 50 and a storage capacitor 60 , and the thin film transistor 50 includes a source electrode 51 , a gate electrode 52 , a semiconductor layer 53 and a drain electrode 54 . The storage capacitor 60 includes a first electrode plate 61 and a second electrode plate 62 . The light emitting unit 70 includes a first electrode 71 , a light emitting functional layer 72 and a second electrode 73 . The light-emitting functional layer 72 is located between the first electrode 71 and the second electrode 73, and the holes injected by the first electrode 71 and the electrons injected by the second electrode 73 combine to form excitons in the light-emitting functional layer 72, and the excitons transition to generate photons so that the light emitting unit 70 emits light. The scan line 21 , the gate electrode 52 and the first electrode plate 61 are located on the first metal layer M1 , and the first metal layer M1 is located between the gate insulating layer 12 and the first dielectric layer 13 . The second electrode plate 62 is located on the second metal layer M2. The data line 22 , the source electrode 51 and the drain electrode 54 are located on the same layer, and the data line 22 is located on the side of the second metal layer M2 away from the substrate 10 . The data line 22 may be electrically connected to the first fan-out line 31 through a via hole, and the data line 22 may be electrically connected to the second fan-out line 32 through a via hole.

Optionally, referring to FIG. 4 , the third metal layer M3 is located on the side of the film layer where the data lines 22 are located away from the substrate 10 . Therefore, the third fan-out trace 33 is located on the side of the film layer where the data line 22 is located away from the substrate 10 , and the distance between the third fan-out trace 33 and the first fan-out trace 31 and the second fan-out trace 32 is relatively long, which avoids the need for the first fan-out trace 31 and the second fan-out trace 32 The adverse electrical effects of the three fan-out traces 33 on the first fan-out trace 31 and the second fan-out trace 32 .

Exemplarily, referring to FIG. 4 , the third fan-out traces 33 are located on the side of the film layer where the data lines 22 are located away from the substrate 10 , and the third fan-out traces 33 are electrically connected to the data lines 22 through vias.

Optionally, referring to FIG. 4 , the array substrate further includes a first insulating layer 81 and a second insulating layer 82 , the first insulating layer 81 is located between the first metal layer M1 and the second metal layer M2 , and the second insulating layer 82 is located between the first metal layer M1 and the second metal layer M2 . Between the third metal layer M3 and the film layer where the data lines 22 are located, the thickness of the second insulating layer 82 is greater than that of the first insulating layer 81 . In the embodiment of the present invention, the thickness of the second insulating layer 82 is greater than the thickness of the first insulating layer 81, and the second insulating layer 82 has a larger thickness, so that the third fan out in the direction perpendicular to the plane of the substrate 10 The distance between the line 33 and the data line 22 is relatively large, and the distance between the third fan-out routing 33 and the first fan-out routing 31 and the second fan-out routing 32 is relatively far, which further prevents the third fan-out routing 33 from affecting the first fan-out routing. The adverse electrical effects of the outgoing traces 31 and the second fan out traces 32 .

For example, referring to FIG. 4 , the first insulating layer 81 includes the first dielectric layer 13 , and the first insulating layer 81 is an inorganic layer. The second insulating layer 82 includes the first organic layer 15 . The thickness of the first organic layer 15 is greater than that of the first dielectric layer 13 . A first dielectric layer 13 is spaced between the first metal layer M1 and the second metal layer M2, and a second dielectric layer 14 and a first organic layer 15 are spaced between the second metal layer M2 and the third metal layer M3. In a direction perpendicular to the plane of the substrate 10, the distance between the third metal layer M3 and the first metal layer M1 is farther, and the distance between the third metal layer M3 and the second metal layer M2 is farther. Therefore, the distance between the third fan-out trace 33 and the first fan-out trace 31 and the second fan-out trace 32 is relatively long.

FIG. 5 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention. Referring to FIG. 5 , the second insulating layer 82 includes a planarization layer 16 and a pixel defining layer 17 , and the planarizing layer 16 is located between the pixel defining layer 17 and the second insulating layer 17 . between the three metal layers M3. In the embodiment of the present invention, the second insulating layer 82 includes the planarization layer 16 and the pixel defining layer 17 , thereby further increasing the thickness of the second insulating layer 82 and increasing the distance between the third fan-out trace 33 and the first fan-out trace 31 . distance, and increasing the distance between the third fan-out trace 33 and the second fan-out trace 32 , further avoids the adverse electrical influence of the third fan-out trace 33 on the first fan-out trace 31 and the second fan-out trace 32 .

Exemplarily, referring to FIG. 5 , the third fan-out traces 33 and the second electrodes 73 are in the same layer and use the same material, and the third fan-out traces 33 and the second electrodes 73 can be formed in the same process, thereby saving the process. .

6 is a schematic top-view structure diagram of another array substrate provided by an embodiment of the present invention. Referring to FIG. 6 , a display area A1 includes a plurality of pixels 100 arranged in an array, the pixel 100 includes a plurality of sub-pixels 110 , and the plurality of sub-pixels 110 includes a first A sub-pixel 101 , a second sub-pixel 102 and a third sub-pixel 103 . Along the second direction, the data lines 22 electrically connected to the plurality of first sub-pixels 101 and the plurality of second sub-pixels 102 are the first data lines 221, and the data lines 22 electrically connected to the plurality of third sub-pixels 103 are the first data lines 221. Two data lines 222 . A first data line 221 is electrically connected with a first fan-out line 31 or a second fan-out line 32 , and a second data line 222 is electrically connected with a third fan-out line 33 . In the embodiment of the present invention, some of the first sub-pixels 101 are electrically connected to the first fan-out traces 31 , and another part of the first sub-pixels 101 are electrically connected to the second fan-out traces 32 . Similarly, some of the second sub-pixels 102 are electrically connected to each other. To the first fan-out trace 31, another part of the second sub-pixel 102 is electrically connected to the second fan-out trace 32, the first fan-out trace 31 located in the first metal layer M1 and the second fan-out trace located in the second metal layer M2 The wire 32 is made of the same material, and the first fan-out wire 31 and the second fan-out wire 32 have the same resistivity, thereby reducing the voltage drop difference between the first fan-out wire 31 and the second fan-out wire 32, Make the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 have the same or similar degree of attenuation, so that the first sub-pixel 101 that receives the data signal transmitted by the first fan-out trace 31 and the second fan-out The first sub-pixel 101 that transmits the data signal from the wire 32 has the same or similar luminance, so that the second sub-pixel 102 that receives the data signal from the first fan-out wire 31 and the second sub-pixel 102 that receives the second fan-out wire 32 transmit the data signal The second sub-pixels 102 have the same or similar luminous brightness to ensure display uniformity.

Optionally, referring to FIG. 6 , the pixel 100 includes a plurality of sub-pixels 110 arranged in a 2*3 arrangement, and a row of sub-pixels 110 arranged in the first direction includes a first sub-pixel 101, a third sub-pixel 103 and a second sub-pixel 102, Another row of sub-pixels 110 arranged in the first direction includes a second sub-pixel 102 , a third sub-pixel 103 and a first sub-pixel 101 .

7 is a schematic top-view structure diagram of another array substrate provided by an embodiment of the present invention. Referring to FIG. 7 , a first data line 221 is electrically connected to a first fan-out line 31 or a second fan-out line 32 , and a first data line 221 is electrically connected to a first fan-out line 31 or a second fan-out line 32 . The two data lines 222 are electrically connected to a third fan-out trace 33 . The pixel 100 includes a plurality of sub-pixels 110 arranged in 2*4, and a row of sub-pixels 110 arranged in the first direction includes a first sub-pixel 101, a third sub-pixel 103, a second sub-pixel 102 and a third sub-pixel 103. Another row of sub-pixels 110 arranged in the direction includes a second sub-pixel 102 , a third sub-pixel 103 , a first sub-pixel 101 and a third sub-pixel 103 .

6 and 7 , the emission color of the first sub-pixel 101 is red, the emission color of the second sub-pixel 102 is blue, and the emission color of the third sub-pixel 103 is green.

Optionally, referring to FIG. 2 , FIG. 3 , FIG. 6 and FIG. 7 , the vertical projections of the first fan-out trace 31 and the third fan-out trace 33 on the substrate 10 do not overlap, and the second fan-out trace 32 and the third fan-out trace 32 do not overlap. The vertical projections of the fan-out traces 33 on the substrate 10 do not overlap. In the embodiment of the present invention, the vertical projections of the first fan-out traces 31 and the third fan-out traces 33 on the substrate 10 do not overlap, which prevents the first fan-out traces 31 and the third fan-out traces 33 from generating overlapping capacitances. The vertical projections of the second fan-out traces 32 and the third fan-out traces 33 on the substrate 10 do not overlap, which prevents the second fan-out traces 32 and the third fan-out traces 33 from generating overlapping capacitances.

8 is a schematic top view of a fan-out trace in an array substrate according to an embodiment of the present invention. Referring to FIG. 8 , the vertical projection of the third fan-out trace 33 and the first fan-out trace 31 on the substrate 10 overlaps. Since the second metal layer M2 is spaced between the third metal layer M3 and the first metal layer M1 in the direction perpendicular to the plane of the substrate 10 , the third fan-out trace 33 and the first fan-out trace 31 are spaced apart There is a second fanout trace 32 . In the direction perpendicular to the plane of the substrate 10, the distance between the third fan-out trace 33 and the first fan-out trace 31 is greater than the spacing between the second fan-out trace 32 and the first fan-out trace 31, and the third The distance between the fan-out trace 33 and the first fan-out trace 31 is relatively large, and the overlap capacitance when the third fan-out trace 33 and the first fan-out trace 31 overlap is small, so that the third fan-out trace 31 has a relatively small overlap. The load increase caused by line 33 and the first fan-out trace 31 is small. And since the vertical projection of the third fan-out trace 33 and the first fan-out trace 31 on the substrate 10 overlaps, the area occupied by the fan-out trace 30 in the step area A2 is reduced, the width of the step area A2 is reduced, and the bezels and increase the screen-to-body ratio.

In addition, the vertical projections of the first fan-out traces 31 , the second fan-out traces 32 and the third fan-out traces 33 on the substrate 10 may not overlap each other and are arranged closely adjacent to each other. That is, the vertical projections of the first fan-out trace 31 , the second fan-out trace 32 and the third fan-out trace 33 on the substrate 10 do not overlap each other, and at the same time, the vertical projections of the three fan-out traces have no gaps with each other. tightly packed. In this way, it can save the space occupied by the gap between the traces and the traces when they are set on the same layer, reduce the width of the lower step, and the orthographic projections of the traces on the sinking substrate can be completely non-overlapping. Overlapping capacitance is generated between the lines, and the space distance between the lines arranged on different layers will also increase correspondingly, which further reduces the signal interference between the fan-out lines.

FIG. 9 is a schematic top-view structural diagram of fan-out traces in another array substrate according to an embodiment of the present invention. Referring to FIG. 9 , the vertical projections of the third fan-out traces 33 and the second fan-out traces 32 on the substrate 10 overlap. In the embodiment of the present invention, the vertical projections of the third fan-out trace 33 and the first fan-out trace 31 and the second fan-out trace 32 on the substrate 10 all overlap. Therefore, the area occupied by the fan-out traces 30 in the step area A2 is further reduced, the width of the step area A2 is reduced, the frame is reduced, and the screen-occupancy ratio is increased. In other embodiments, the third fan-out trace 33 may not overlap with the vertical projection of the first fan-out trace 31 on the substrate 10 , but only intersect with the vertical projection of the second fan-out trace 32 on the substrate 10 . stack. Therefore, in some feasible embodiments, the third fan-out trace 33 may overlap the vertical projection of the first fan-out trace 31 and/or the second fan-out trace 32 on the substrate 10 to reduce the fan-out trace 30 occupies an area in the step area A2.

Optionally, referring to FIG. 9 , the overlapping area of the third fan-out wiring 33 and the second fan-out wiring 32 is smaller than the overlapping area of the third fan-out wiring 33 and the first fan-out wiring 31 . In the embodiment of the present invention, the third fan-out trace 33 overlaps the vertical projection of the first fan-out trace 31 on the substrate 10 , and the third fan-out trace 33 overlaps the vertical projection of the second fan-out trace 32 on the substrate 10 stack. In the direction perpendicular to the plane of the substrate 10, the distance between the third fan-out trace 33 and the first fan-out trace 31 is greater than the distance between the third fan-out trace 33 and the second fan-out trace 32, and the third fan-out trace 33 The overlapping area with the second fan-out trace 32 is smaller than the overlap area of the third fan-out trace 33 and the first fan-out trace 31 . It can be understood that the overlap capacitance is inversely proportional to the distance, and the overlap capacitance is proportional to the overlap area. In the embodiment of the present invention, the overlapping area of the third fan-out wiring 33 with the larger distance and the first fan-out wiring 31 is larger, and the overlapping area of the third fan-out wiring 33 and the second fan-out wiring 32 with the smaller distance The area is small, so that the overlapping capacitance of the third fan-out trace 33 and the first fan-out trace 31 is consistent with the overlapping capacitance of the third fan-out trace 33 and the second fan-out trace 32, so as to balance the The electrical influence of the third fan-out trace 33 on the first fan-out trace 31 and the second fan-out trace 32 makes the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 the same or similar degree of attenuation to ensure display uniformity.

FIG. 10 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention. Referring to FIG. 10 , the data lines 22 are located in the third metal layer M3 . In the embodiment of the present invention, the third fan-out wiring 33 and the data line 22 are both located in the third metal layer M3, and the third fan-out wiring 33 and the data line 22 can be formed of the same material and in the same process, so as to save the process. .

FIG. 11 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention, FIG. 12 is a top-view structural schematic diagram of another array substrate provided by an embodiment of the present invention, and FIG. 13 is another type of array substrate provided by an embodiment of the present invention. 11 , 12 , and 13 , and with reference to FIG. 1 , the array substrate further includes a plurality of scan lines 21 , and the plurality of scan lines 21 are located in the display area A1 , extending along the first direction and extending along the Arrangement in the second direction. The scan lines 21 are located in the first metal layer M1, the data lines 22 are located in the second metal layer M2, and the second metal layer M2 and the third metal layer M3 are made of the same material. In the embodiment of the present invention, the second fan-out trace 32 and the third fan-out trace 33 are made of the same material, and the second fan-out trace 32 and the third fan-out trace 33 have the same resistivity, thereby reducing the second fan-out trace. The difference between the voltage drops on the outgoing trace 32 and the third fan out trace 33 makes the data signals transmitted on the second fan out trace 32 and the third fan out trace 33 have the same or similar degree of attenuation to ensure a uniform display sex.

11 , 12 , and 13 , and with reference to FIG. 1 , the scan line 21 , the gate 52 of the thin film transistor 50 and the first plate 61 of the storage capacitor 60 are located in the first metal layer M1 , and the thin film transistor The source electrode 51 of 50 , the drain electrode 54 of the thin film transistor 50 , the data line 22 and the second fan-out line 32 are located in the second metal layer M2 .

Optionally, referring to FIG. 11 , FIG. 12 , and FIG. 13 , and with reference to FIG. 1 , the display area A1 includes a plurality of pixels 100 arranged in an array, the pixel 100 includes a plurality of sub-pixels 110 , and the plurality of sub-pixels 110 includes a first sub-pixel 101 , a second sub-pixel 102 and a third sub-pixel 103 . Along the second direction, the data lines 22 electrically connected to the plurality of first sub-pixels 101 and the plurality of second sub-pixels 102 are the first data lines 221, and the data lines 22 electrically connected to the plurality of third sub-pixels 103 are the first data lines 221. Two data lines 222 . A first data line 221 is electrically connected with a second fan-out line 32 or a third fan-out line 33 , and a second data line 222 is electrically connected with a first fan-out line 31 .

In the embodiment of the present invention, some of the first sub-pixels 101 are electrically connected to the second fan-out traces 32 , and another part of the first sub-pixels 101 are electrically connected to the third fan-out traces 33 . Similarly, some of the second sub-pixels 102 are electrically connected to each other. To the second fan-out trace 32, another part of the second sub-pixel 102 is electrically connected to the third fan-out trace 33, the second fan-out trace 32 located in the second metal layer M2 and the third fan-out trace located in the third metal layer M3 The wire 33 is made of the same material, and the second fan-out wire 32 and the third fan-out wire 33 have the same resistivity, thereby reducing the voltage drop difference between the second fan-out wire 32 and the third fan-out wire 33, Make the data signals transmitted on the second fan-out trace 32 and the third fan-out trace 33 have the same or similar degree of attenuation, so that the first sub-pixel 101 that receives the data signal transmitted by the second fan-out trace 32 and the first sub-pixel 101 that receives the third fan-out trace 32 The first sub-pixel 101 that transmits the data signal from the line 33 has the same or similar luminance, so that the second sub-pixel 102 that receives the data signal from the second fan-out line 32 and the second sub-pixel 102 that receives the third fan-out line 33 transmit the data signal The second sub-pixels 102 have the same or similar luminous brightness to ensure display uniformity.

FIG. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to FIG. 14 , the display panel 400 includes the array substrate 200 in the above-mentioned embodiment. The display panel 400 may be an organic light emitting display panel, a liquid crystal display panel, an electrophoretic display panel, or the like.

For example, referring to FIG. 14 , the display panel 400 further includes an opposite substrate 300 disposed opposite to the array substrate 200 , and the opposite substrate 300 may be, for example, a color filter substrate or a package cover. For example, the color filter substrate may include well-known structures such as color resist and black matrix, which will not be repeated here.

An embodiment of the present invention further provides a display device. FIG. 15 is a schematic structural diagram of a display device provided by an embodiment of the present invention. As shown in FIG. 15 , the display device provided by an embodiment of the present invention includes the above-mentioned display panel 400 . The display device may be the mobile phone shown in FIG. 15 , or may be a computer, a television, a smart wearable device, or the like, which is not particularly limited in this embodiment of the present invention.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention. The scope is determined by the scope of the appended claims.

Claims (19)

1. The array substrate is characterized by comprising a display area and a step area;

a substrate;

a plurality of data lines located in the display area; the data lines extend along a second direction and are arranged along a first direction;

the fan-out wires are positioned in the step areas and electrically connected with the data lines and used for providing data signals for the data lines; the plurality of fan-out wires comprise a first fan-out wire positioned on the first metal layer, a second fan-out wire positioned on the second metal layer and a third fan-out wire positioned on the third metal layer; in a direction perpendicular to the substrate, the second metal layer is located on one side, away from the substrate, of the first metal layer, the third metal layer is located on one side, away from the first metal layer, of the second metal layer, and vertical projections of the first fan-out routing and the second fan-out routing on the substrate are not overlapped;

the film layer where the data line is located is a first organic layer; the first fan-out routing and the second fan-out routing are positioned on two sides of the third fan-out routing;

the first fan-out routing line and the second fan-out routing line are closer in distance.

2. The array substrate of claim 1, further comprising a plurality of scan lines in the display area, extending along the first direction and arranged along the second direction;

the scanning line is located on the first metal layer, and the second metal layer is located between the first metal layer and the film layer where the data line is located.

3. The array substrate of claim 2, wherein the first metal layer and the second metal layer are made of the same material.

4. The array substrate of claim 3, wherein a line width of the first fan-out trace is equal to a line width of the second fan-out trace.

5. The array substrate of claim 3, wherein the display area comprises a plurality of pixels arranged in an array, the pixels comprising a plurality of sub-pixels, the plurality of sub-pixels comprising a first sub-pixel, a second sub-pixel and a third sub-pixel;

along the second direction, the data line electrically connected with the first sub-pixels and the second sub-pixels is a first data line, and the data line electrically connected with the third sub-pixels is a second data line;

one first data line is electrically connected with one first fan-out wiring or one second fan-out wiring, and one second data line is electrically connected with one third fan-out wiring.

6. The array substrate of claim 5, wherein the pixel comprises a plurality of the sub-pixels arranged in 2 x 3, one row of the sub-pixels arranged in the first direction comprises the first sub-pixel, the third sub-pixel and the second sub-pixel, and another row of the sub-pixels arranged in the first direction comprises the second sub-pixel, the third sub-pixel and the first sub-pixel.

7. The array substrate of claim 5, wherein the pixel comprises a plurality of the sub-pixels arranged in 2 x 4 rows, one row of the sub-pixels arranged in the first direction comprises the first sub-pixel, the third sub-pixel, the second sub-pixel and the third sub-pixel, and another row of the sub-pixels arranged in the first direction comprises the second sub-pixel, the third sub-pixel, the first sub-pixel and the third sub-pixel.

8. The array substrate of claim 1, wherein the data line is located in the third metal layer.

9. The array substrate of claim 1, wherein the third metal layer is located on a side of the film layer where the data line is located away from the substrate.

10. The array substrate of claim 9, further comprising a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first metal layer and the second metal layer, the second insulating layer is located between the third metal layer and the film layer where the data line is located, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.

11. The array substrate of claim 10, wherein the second insulating layer comprises a planarization layer and a pixel defining layer, the planarization layer being located between the pixel defining layer and the third metal layer.

12. The array substrate of claim 1, wherein the third fan-out trace overlaps a perpendicular projection of the first fan-out trace on the substrate.

13. The array substrate of claim 12, wherein the third fan-out trace overlaps a perpendicular projection of the second fan-out trace on the substrate.

14. The array substrate of claim 13, wherein an overlapping area of the third fan-out trace and the second fan-out trace is smaller than an overlapping area of the third fan-out trace and the first fan-out trace.

15. The array substrate of claim 1, wherein the first fan-out trace and the third fan-out trace do not overlap in vertical projection on the substrate, and the second fan-out trace and the third fan-out trace do not overlap in vertical projection on the substrate.

16. The array substrate of claim 1, further comprising a plurality of scan lines in the display area, extending along the first direction and arranged along the second direction;

the scanning lines are located on the first metal layer, the data lines are located on the second metal layer, and the second metal layer and the third metal layer are made of the same material.

17. The array substrate of claim 16, wherein the display area comprises a plurality of pixels arranged in an array, the pixels comprising a plurality of sub-pixels, the plurality of sub-pixels comprising a first sub-pixel, a second sub-pixel and a third sub-pixel;

along the second direction, the data line electrically connected with the plurality of first sub-pixels and the plurality of second sub-pixels is a first data line, and the data line electrically connected with the plurality of third sub-pixels is a second data line;

one first data line is electrically connected with one second fan-out wiring or one third fan-out wiring, and one second data line is electrically connected with one first fan-out wiring.

18. A display panel comprising the array substrate according to any one of claims 1 to 17.

19. A display device characterized by comprising the display panel according to claim 18.

Images