CN110930883B - Display panel and display device - Google Patents
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- CN110930883B CN110930883B CN201911276826.XA CN201911276826A CN110930883B CN 110930883 B CN110930883 B CN 110930883B CN 201911276826 A CN201911276826 A CN 201911276826A CN 110930883 B CN110930883 B CN 110930883B
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Abstract
The embodiment of the invention discloses a display panel and a display device, wherein the display panel comprises a substrate; the liquid crystal display device comprises a gate line, a data line, a power line and a first active layer, wherein the gate line, the data line, the power line and the first active layer are positioned on a substrate; the area enclosed by the projections of the two adjacent gate lines, the data line and the power line adjacent to the data line on the substrate is a first area; along the thickness direction of the substrate, a first active layer is arranged in at least one first area, the area of a light-transmitting area in at least one first area provided with the first active layer accounts for more than 3% of the area of a topological structure of a pixel circuit, and the total area of the light-transmitting areas in the topological structure of the pixel circuit accounts for 30% -40% of the total area of the topological structure of the pixel circuit. According to the technical scheme, the area of the light-transmitting area in the display panel can be increased, and the light transmittance of the display panel is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, more and more display devices are integrated with fingerprint identification modules.
In the existing display panel, in order to realize the function of identifying fingerprints under the screen, a mode of opening holes in a pixel area is usually adopted, the holes are usually small, so that the light transmittance of the screen body of the existing display panel is limited, and the difficulty is brought to the identification of the fingerprints under the screen.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for improving the light transmittance of a screen body and further realizing the identification of fingerprints under a screen.
In a first aspect, an embodiment of the present invention provides a display panel, including:
a substrate;
the liquid crystal display device comprises a gate line, a data line, a power line and a first active layer, wherein the gate line, the data line, the power line and the first active layer are positioned on a substrate;
the area enclosed by the projections of the two adjacent gate lines, the data line and the power line adjacent to the data line on the substrate is a first area; along the thickness direction of the substrate, a first active layer is arranged in at least one first area, and the area of a light-transmitting area in at least one first area provided with the first active layer accounts for more than 3% of the area of a topological structure of one pixel circuit;
in the display panel, the total area of the light-transmitting areas in the pixel circuit topological structure accounts for 30% -40% of the total area of the pixel circuit topological structure.
Optionally, the display panel further includes an initialization line, and the first active layer is connected to the initialization line through the contact hole.
Optionally, the display panel further includes a second active layer, the second active layer is a low-temperature polysilicon layer, and the first active layer is a metal oxide semiconductor layer;
the substrate is sequentially provided with a second active layer, a first metal layer, a second metal layer, a first active layer, a third metal layer and a fourth metal layer; the gate line is located on the first metal layer and the third metal layer.
Optionally, the gate lines include a first gate line and a second gate line arranged along a second direction, and both the first gate line and the second gate line are located on the third metal layer;
the first active layer includes at least a first active portion and a second active portion arranged in the first direction and overlapping the first gate line, a portion of the first active portion overlapping the first gate line forms a first initialization transistor, and a portion of the second active portion overlapping the first gate line forms a second initialization transistor;
the first active layer further includes a third active portion extending in the second direction, the third active portion overlapping the second gate line, and a portion of the third active portion overlapping the second gate line forms a compensation transistor;
wherein the third active portion is located between the adjacent first data line and the first power line.
Optionally, the pixel circuit includes a driving transistor and a light emission control transistor for connecting an anode of the light emitting device, and the second active layer constitutes active layers of the driving transistor and the light emission control transistor;
the second active layer includes a fourth active portion connecting the drain of the driving transistor and the source of the emission control transistor, the fourth active portion extending in the second direction;
in the first direction, the fourth active portion is located between the third active portion and the first data line; the first end of the third active portion is connected to the gate of the driving transistor through a first metal line, the second end of the third active portion is connected to the fourth active portion through a second metal line, and the second end of the third active portion is a common end of the first initialization transistor and the compensation transistor.
Optionally, the second metal line is located on the second metal layer, and the second metal line includes a first metal portion extending along the first direction and a second metal portion extending along the second direction, and the second metal portion and the fourth active portion are located on the same straight line.
Optionally, the pixel circuit includes a driving transistor and a light emission control transistor for connecting an anode of the light emitting device, and the second active layer constitutes active layers of the driving transistor and the light emission control transistor;
the second active layer includes a fourth active portion connecting the gate of the driving transistor and the gate of the emission control transistor, the fourth active portion extending in the second direction;
the fourth active portion overlaps the third active portion; the first end of the third active part is electrically connected with the grid electrode of the driving transistor through a third metal wire, and the second end of the third active part is electrically connected with the fourth active part through a through hole; wherein the first terminal of the third active portion is a common terminal of the first initialization transistor and the compensation transistor.
Optionally, the fourth active portion and the third active portion are located on the same straight line.
Optionally, the display panel further includes a third gate line and a fourth gate line, the third gate line and the fourth gate line are located on the first metal layer, the third gate line is located between the first gate line and the second gate line, and the fourth gate line is located on a side of the second gate line away from the first gate line;
the first active layer further comprises a fifth active portion between the first active portion and the second active portion, the first active portion, the second active portion and the fifth active portion all extend along the second direction, and the first active layer further comprises a sixth active portion connecting the second active portion and the fifth active portion;
the first data line and the first power line, and the first gate line and the third gate line which are adjacent to each other enclose a first region, and the sixth active region is located in the first region along the thickness direction of the substrate; the area of the light-transmitting area in the first area accounts for at least 5% of the topological structure area of one pixel circuit. Optionally, the first area is located in a fingerprint identification area of the display panel.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel provided in the first aspect.
The embodiment of the invention provides a display panel and a display device, wherein the display panel comprises a substrate; the liquid crystal display panel comprises a gate line, a data line, a power line and a first active layer, wherein the gate line, the data line, the power line and the first active layer are positioned on a substrate, and a region enclosed by projections of two adjacent gate lines, the data line and the power line adjacent to the data line on the substrate is a first region; the area of the light transmission area in at least one first area provided with the first active layer accounts for more than 3% of the area of the topological structure of one pixel circuit, so that the area of the light transmission area in a single first area in the pixel circuit can be ensured to be larger, namely, a light transmission hole with a larger size can exist in the topological structure of the pixel circuit. And set up the first active layer and be transparent active layer, except making to have great size opening in the pixel circuit topological structure, can also make still to have more light transmission region to account for less region in the display panel, can and then make the total area of light transmission region account for 30% -40% of pixel circuit topological structure total area in the pixel circuit topological structure, compare in traditional polycrystalline silicon active layer, can increase the area of light transmission region in the display panel, improve the light transmissivity of display panel, and then can realize fingerprint identification under the screen, and be favorable to improving fingerprint identification performance.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is an enlarged view of one of the pixel circuit topologies of FIG. 1; fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a display panel according to an embodiment of the present invention;
figure 6 is a schematic structural diagram of another display panel provided in an embodiment of the invention,
figure 7 is an enlarged view of a portion of figures 1 and 6 provided by an embodiment of the present invention,
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, in the conventional display panel, in order to implement the function of the finger print under the screen, a mode of opening a hole in a pixel region is usually adopted, and the hole is usually small, so that the light transmittance of the screen body of the conventional display panel is limited, and difficulty is brought to the implementation of the finger print under the screen. The inventor researches and finds that the above problems occur because the conventional display panel with an under-screen fingerprint identification function generally comprises a plurality of light emitting devices for displaying and a pixel circuit array layer for driving the light emitting devices to emit light, and the fingerprint identification sensor is generally arranged on one side of the pixel circuit array layer far away from the light emitting devices. The pixel circuit array layer generally comprises a polycrystalline silicon layer and a plurality of metal layers, for realizing higher pixel resolution, in the thickness direction of the display panel, the polycrystalline silicon layer and the metal layers are arranged closely, the size of an opening hole in a pixel area is limited, the area of a light transmission area of the pixel circuit array layer is smaller, the light transmittance of the whole pixel circuit array layer is smaller, the fingerprint identification sensor is arranged on one side of the pixel circuit array layer far away from a light emitting device, the light which can be irradiated to the fingerprint identification sensor through the pixel circuit array layer is limited, and the fingerprint identification sensor cannot work normally or the identification precision is limited.
In view of the above problems, an embodiment of the present invention provides a display panel, and fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present invention, and referring to fig. 1, the display panel includes a substrate (not shown in fig. 1); a gate line, a data line 120, a power line 130, and a first active layer 140 on the substrate, the first active layer 140 being a transparent active layer, the gate line extending in a first direction x, the data line 120 extending in a second direction y, the first direction x intersecting the second direction y; the area enclosed by the projection of the two adjacent gate lines, the data line 120 and the power line 130 adjacent to the data line 120 on the substrate is a first area; along the thickness direction of the substrate, a first active layer 140 is arranged in at least one first area, and the area of a light-transmitting area in the first area accounts for more than 3% of the area of a topological structure of one pixel circuit;
in the display panel, the total area of the light-transmitting areas in the pixel circuit topological structure accounts for 30% -40% of the total area of the pixel circuit topological structure.
In particular, the substrate may provide cushioning, protection, or support for the display device. The substrate may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of these materials. The substrate may be a hard substrate formed of a material such as glass.
The gate line may include a scan line and a light emission control signal line. Referring to fig. 1, fig. 1 exemplarily shows a case where the gate line includes a first scan line, a second scan line 112, and a light emission control signal line 113, and two first scan lines, i.e., a first scan line one 1111 and a first scan line two 1112, are shown in fig. 1. The sub-pixels in the display panel are usually arranged in an array, for example, m rows along the second direction y and n columns along the first direction x, then the first scan line one 1111 may be connected to a specific transistor in the pixel circuit of the sub-pixel in the ith row, the first scan line two 1112 may be connected to the same transistor in the pixel circuit of the sub-pixel in the (i +1) th row, exemplarily, the first scan line 1111 may be connected to the gate of the initialization transistor of the pixel circuit in the ith row, and then the second scan line 1112 may be connected to the gate of the initialization transistor in the pixel circuit in the (i +1) th row. The gate lines, the data lines 120, and the power lines 130 in the display panel are usually made of metal, and therefore, the gate lines, the data lines 120, and the power lines 130 are usually opaque, so that when light is emitted from the light emitting side of the display panel to the gate lines, the data lines 120, or the power lines 130, the light is reflected and cannot pass through the lines.
The display panel of the embodiment may include a first active layer 140 disposed on one side of the substrate, and a plurality of metal layers on one side of the first active layer 140 away from the first active layer 140, the gate line, the data line 120 and the power line 130 may be disposed in the plurality of metal layers on one side of the first active layer 140 away from the substrate, the fingerprint sensor is generally disposed on one side of the first active layer 140 away from each metal layer, specifically between the first active layer 140 and the substrate, and may also be disposed on one side of the substrate away from the first active layer 140, as described above, since the metal routing lines of the gate line, the data line 120 and the power line 130 are generally opaque, light cannot penetrate through the gate line, the data line 120 and the power line 130 to the fingerprint sensor. In the display panel of this embodiment, the first active layer 140 is a transparent active layer, and optionally, the material of the transparent active layer may be Indium Gallium Zinc Oxide (IGZO), so that light can pass through a region where the transparent active layer and the metal layer are not overlapped in the thickness direction of the display panel.
Referring to fig. 1, specifically, a region enclosed by projections of two adjacent gate lines, a data line 120 and a power line 130 adjacent to the data line 120 on the substrate is a first region; along the thickness direction of the substrate, the first active layer 140 is arranged in at least one first area, and the area of the light-transmitting area in at least one first area provided with the first active layer accounts for more than 3% of the area of the topological structure of one pixel circuit; in the display panel, the total area of the light-transmitting areas in the pixel circuit topological structure accounts for 30% -40% of the total area of the pixel circuit topological structure. The area of the topology 150 of one pixel circuit may refer to an area surrounded by two adjacent data lines and two gate lines connecting the same transistor in two adjacent rows of pixel circuits, wherein, to calculate the occupied areas of the data lines and the gate lines, the area surrounded by the center lines of the two adjacent data lines and the center line connecting the gate line of the same transistor in two adjacent rows of pixel circuits may be respectively used as the area of the topology 150 of one pixel circuit. The total area of the pixel circuit topology may be an area surrounded by outermost outlines of all pixel circuit topologies (including various components such as thin film transistors and capacitors, and various signal lines in any embodiment of the present invention) in the entire display panel, which are orthogonally projected on the substrate, for example, when the outermost sides of all pixel circuit topologies are two data lines farthest away in a first direction and two gate lines farthest away in a second direction, an area surrounded by orthogonally projected outer edges of the two data lines farthest away in the first direction and the two gate lines farthest away in the second direction on the substrate is taken as the total area of the pixel circuit topology.
Fig. 2 is an enlarged view of one pixel circuit topology of fig. 1, and referring to fig. 2, fig. 2 exemplarily shows four first regions, i.e., a first region one 151, a first region two 152, a first region three 153, and a first region four 154. The first active layer 140 is disposed in each of the first region one 151, the first region two 152, the first region three 153, and the first region four 154, and almost only the first active layer 140 exists in the first region one 151. . In the display panel of fig. 1, the first direction x and the second direction y are taken as an example to be perpendicular, and then one pixel circuit topology 150 is rectangular, and referring to fig. 1 and fig. 2, the width a1 of the pixel circuit topology 150 is 26 micrometers, and the length is 78 micrometers; the first region 151 can also be regarded as a rectangle, and the length c1 of the first region is 14 micrometers, and the width of the first region is 7.5 micrometers, because only a small part of the region corresponding to the power line 130 in the first region 151 is an opaque region, which is negligible here, because the first active layer 140 is a transparent active layer, the area of the transparent region in the first region 151 is not affected by the transparent active layer in the first region 151, and the ratio of the area of the transparent region in the first region 151 to the area of the pixel circuit topology 150 is (14 × 7.5)/(78 × 26) ═ 5.2%, which is greater than 3%, so that the area of the transparent region in a single first region in the pixel circuit can be ensured to be larger. Optionally, the area of the light-transmitting region in at least one of the first regions provided with the first active layer accounts for 3% to 5.2% of the area of the topological structure of one pixel circuit. Because the area of the light-transmitting region in at least one first region provided with the first active layer 140 accounts for more than 3% of the area of the topological structure of one pixel circuit, and the first active layer 140 is provided as a transparent active layer, more regions with smaller light-transmitting regions also exist in the display panel, and the total area of the light-transmitting regions in the pixel circuit topological structure accounts for 30% -40% of the total area of the pixel circuit topological structure. Compare in traditional polycrystalline silicon active layer, can increase the regional area of light transmission in the display panel, and then improve display panel's light transmissivity, and then make fingerprint identification under the screen realize more easily, be favorable to promoting fingerprint identification performance.
It should be noted that the total area of the light-transmitting regions in the pixel circuit topology structure accounts for 30% -40% of the total area of the pixel circuit topology structure and does not represent the light transmittance of the whole display panel, and the whole light transmittance of the display panel is also affected by other film layer structures (such as polarizers, etc.).
The display panel provided by the embodiment comprises a substrate; the liquid crystal display panel comprises a gate line, a data line, a power line and a first active layer, wherein the gate line, the data line, the power line and the first active layer are positioned on a substrate, and a region enclosed by projections of two adjacent gate lines, the data line and the power line adjacent to the data line on the substrate is a first region; along the thickness direction of the substrate, the first active layer is arranged in at least one first area, and the area of the light-transmitting area in at least one first area provided with the first active layer accounts for more than 3% of the area of the topological structure of one pixel circuit, so that the area of the light-transmitting area in a single first area in the pixel circuit can be ensured to be larger. Because of the light transmission area accounts for more than 3% of the area of the topological structure of the pixel circuit in at least one first area provided with the first active layer, and the first active layer is arranged to be a transparent active layer, more light transmission areas account for smaller areas in the display panel, and the total area of the light transmission areas in the pixel circuit topological structure accounts for 30% -40% of the total area of the pixel circuit topological structure.
With continued reference to fig. 1, optionally, the display panel further includes an initialization line, and the first active layer 140 is connected to the initialization line through the contact hole 161.
Specifically, the initialization line may be used to transmit an initialization signal, and the first active layer 140 and the initialization line are connected through the contact hole 161, so that there is an overlap of the first active layer 140 and the initialization line in a thickness direction of the display panel, and the contact hole 161 may be formed in a partial region where the first active layer 140 and the initialization line overlap. Fig. 2 exemplarily shows two initialization lines, which are denoted as an initialization line one 1601 and an initialization line two 1602, referring to fig. 2, in a first region one 151 formed by a first scan line one 1111 and a second scan line one 1121 adjacent to the initialization line one 1601, a power line 130 and a data line 120, metal wirings of the gate line, the data line 120 and the power line 130 are hardly disposed, and therefore, the initialization line is disposed to be connected to the first active layer 140 through the contact hole 161, so that the first active layer 140 is formed at a position close to the initialization line, and a light transmission region in the formed first region can be relatively large, thereby facilitating to improve the overall light transmittance of the display panel.
Fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 3 and fig. 4, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor C1, and an organic light emitting device D1, where each row of pixel circuits may correspond to two scan lines, which are hereinafter referred to as a first scan line and a second scan line, respectively. For example, the pixel circuit is located in the ith row, the first Scan line one 1111 corresponds to the pixel circuit in the ith row, the gate of the fourth transistor T4 is connected to the first Scan signal input terminal Scan1(i) of the pixel circuit in the ith row, the first Scan signal input terminal Scan1(i) may be connected to the first Scan line one 1111 corresponding to the pixel circuit in the ith row, the first pole of the fourth transistor T4 is connected to the initialization voltage input terminal Vref of the pixel circuit, and the initialization voltage input terminal Vref may be connected to the initialization line corresponding to the pixel circuit in the ith row. The gates of the second transistor T2 and the third transistor T3 are connected to a second Scan signal input terminal Scan2(i), the second Scan signal input terminal Scan2(i) is connectable to a second Scan line of the row, the first pole of the second transistor T2 is connected to a data voltage input terminal Vdata, and the data voltage input terminal Vdata is connected to the data line 120; the gate of the fifth transistor T5 is the same as the Scan line connected to the first Scan signal input terminal Scan1(i +1) of the pixel circuit in the (i +1) th row, that is, the first Scan line corresponding to the pixel circuit in the (i +1) th row is connected, and the first pole of the fifth transistor T5 is connected to the initialization line corresponding to the pixel circuit in the present row. The gates of the sixth transistor T6 and the seventh transistor T7 are connected to the light-emitting control signal input terminal of the pixel circuit, the light-emitting control signal input terminal may be connected to the light-emitting control signal line 113 corresponding to the pixel circuit of the row, the first pole of the sixth transistor T6 is connected to the first power supply voltage input terminal Vdd, and the cathode of the organic light-emitting device D1 is connected to the second power supply voltage input terminal Vss.
The difference between the pixel circuits in fig. 3 and fig. 4 is only that the connection relationship of the fourth transistor T4 is different, in fig. 3, the fourth transistor T4 is electrically connected to the gate of the first transistor T1 through the third transistor T3, and in fig. 4, the fourth transistor T4 is directly electrically connected to the gate T1 of the first transistor. The display panel structure shown in fig. 1 includes a pixel circuit structure shown in fig. 3.
It should be noted that fig. 1 shows two second scan lines, which are denoted as a first scan line 1121 and a second scan line 1122, and the first scan line 1121 and the second scan line 1122 can transmit the same scan signal but can be located in different metal layers.
Fig. 5 is a cross-sectional view of a display panel according to an embodiment of the present invention, the cross-sectional view may correspond to a schematic structural view of the display panel shown in fig. 1, and referring to fig. 1 and fig. 5, optionally, the display panel further includes a second active layer 210, the second active layer 210 is a low temperature polysilicon layer, and the first active layer 140 is a metal oxide semiconductor layer;
a second active layer 210, a first metal layer 220, a second metal layer 230, a first active layer 140, a third metal layer 240 and a fourth metal layer 250 are sequentially disposed on the substrate 200; the gate line is located in the first metal layer 220 and the third metal layer 240.
Referring to fig. 2 and 5, the first active layer 140 serves as an active layer of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in fig. 3 and 4, gates of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be located at the third metal layer 240, and sources and drains of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be located at the fourth metal layer 250; the second active layer 210 serves as an active layer of the first, second, sixth and seventh transistors T1, T2, T6 and T7 of fig. 3 and 4, gates of the first, second, sixth and seventh transistors T1, T2, T6 and T7 may be located at the first metal layer 220, and sources and drains of the first, second, sixth and seventh transistors T1, T2, T6 and T7 may be located at the second metal layer 230. The gate lines of the display panel may be disposed on the first metal layer 220 or the third metal layer 240 according to the transistors connected thereto. For example, the pixel circuit is located in the ith row, and the gate of the fourth transistor T4 is connected to the first scan line corresponding to the pixel circuit in this row, so that the first scan line and the gate of the fourth transistor T4 are located in the same layer, that is, in the third metal layer 240, and when the first scan line is connected to the gate of the fourth transistor T4, no via hole needs to be opened, so that the connection between the first scan line and the gate of the fourth transistor T4 is more convenient. For the same reason, the second scan line may be electrically connected to the gate of the second transistor T2, and the second scan line may be disposed on the first metal layer 220 at the same level as the gate of the second transistor T2. The light emission control line is located at the first metal layer 220 at the same layer as the gates of the sixth and seventh transistors T6 and T7. Optionally, the initialization line is disposed on the second metal layer 230, and the data line 120 and the power line 130 are disposed on the fourth metal layer 250.
In the display panel of this embodiment, the display panel includes the second active layer 210, the first metal layer 220, the second metal layer 230, the first active layer 140, the third metal layer 240, and the fourth metal layer 250, which are sequentially disposed on the substrate 200, such that the second active layer 210, the first metal layer 220, and the second metal layer 230 form part of element signal lines in the display panel, and the first active layer 140, the third metal layer 240, and the fourth metal layer 250 form another part of elements and signal lines in the display panel, which is equivalent to improving a one-layer array structure (all transistors correspond to one active layer) in the prior art into a two-layer array structure, so that a layout space for arranging the elements and the signal lines is more sufficient, and a larger light-transmitting region is more easily formed, thereby facilitating improvement of transmittance of the display panel.
Referring to fig. 1, 3 and 5, the gate lines may alternatively include a first gate line 1111 (i.e., a first scan line one in the above embodiment) and a second gate line 1122 (i.e., a second scan line two in the above embodiment) arranged in a second direction, and both the first gate line 1111 and the second gate line 1122 are located at a third metal layer;
the first active layer 140 includes at least a first active portion 141 and a second active portion 142 arranged in the first direction x and overlapping the first gate line 1111, a portion of the first active portion 141 overlapping the first gate line 1111 forming a first initialization transistor T4, and a portion of the second active portion 142 overlapping the first gate line 1122 forming a second initialization transistor T5;
the first active layer 140 further includes a third active portion 143, the third active portion T3 extends along the second direction y, the third active portion 143 overlaps the second gate line 1122, and a portion where the third active portion 140 overlaps the second gate line 1122 forms a compensation transistor T3;
wherein the third active portion 143 is located between the adjacent first data line 121 and the first power line 131.
Referring to fig. 5, in particular, since the gate line extends along a first direction x, the first, second, and third active portions 141, 142, and 143 extend along a second direction y intersecting the first direction x, which ensures that the first, second, and third active portions 141, 142, and 143 may form an overlapping region with the gate line to form a transistor. A position where the first active portion 141 overlaps the first gate line 1111 forms a first initialization transistor T4, and a position where the second active portion 142 overlaps the first gate line 1122 forms a second initialization transistor T5, i.e., the first active layer 140 serves as an active layer of the first and second initialization transistors T4 and T5. The compensation transistor T3 is formed at a position where the third active portion 143 overlaps the second gate line 1122, i.e., the first active layer 140 serves as an active layer of the compensation transistor T3. As can be seen from fig. 1, the arrangement density of the metal traces in the regions where the first initialization transistor T4, the second initialization transistor T5 and the compensation transistor T3 are located is reduced, so that a large opening is easily formed, the first active layer 140 is a transparent active layer, and the first active layer 140 is used as the active layer of the initialization transistor and the compensation transistor, so that a light-transmitting region with a large area is easily formed, thereby facilitating to improve the overall light transmittance of the display panel. In addition, the material of the first active layer 140 may be IGZO, which may reduce leakage currents of the initialization transistor and the compensation transistor, so that the gate potential of the first transistor T1 as the driving transistor may be well maintained, thereby improving the display effect.
Referring to fig. 1, 2 and 5, alternatively, the pixel circuit includes a driving transistor T1 and a light emission controlling transistor T7 for connecting the anode of the light emitting device, and the second active layer constitutes the active layers of the driving transistor T1 and the light emission controlling transistor T7;
the second active layer 210 includes a fourth active portion 211 connecting the drain of the driving transistor T1 and the source of the light emission controlling transistor, the fourth active portion 211 extending in the second direction y;
in the first direction x, the fourth active portion 211 is located between the third active portion 143 and the first data line 121; the first terminal of the third active portion 143 is connected to the gate of the driving transistor T1 through the first metal line 170, the second terminal of the third active portion 143 is connected to the fourth active portion 211 through the second metal line 180, and the second terminal of the third active portion 143 is a common terminal of the first initialization transistor T4 and the compensation transistor T3.
Specifically, the third active portion 143 is located between the first data line 121 and the first power line 131, and the fourth active portion 211 is located between the third active portion 143 and the first data line 121, and the third active portion 143 is used as both a part of the compensation transistor T3 and a signal line connecting the gate of the first initialization transistor T4 and the gate of the driving transistor T1, that is, the transparent first active layer is used as an active layer and a signal line of a partial transistor in the display panel, compared with an opaque active layer such as low temperature polysilicon, a light-transmitting area between the first data line 121 and the first power line 131 can be enlarged, thereby being beneficial to improving transmittance of the display panel.
With continued reference to fig. 3 and 4, optionally, the second metal line 180 is located at the second metal layer, and the second metal line 180 includes a first metal portion 181 extending along the first direction x and a second metal portion 182 extending along the second direction y, and the second metal portion 182 and the fourth active portion 211 are located on the same straight line.
Specifically, since the second metal line 180 overlaps the gate line 1122, the gate line may have a first metal layer and a third metal layer, and thus the second metal line 180 is located in the second metal layer, which may prevent a signal short circuit. Moreover, the second metal layer 180 is located between the first active layer 140 and the second active layer 210, and when the first active layer 140 and the second active layer 210 are connected by punching, the punching depth is shallow, which is further beneficial to the realization of the punching process. And, set up second metal wire 180 and include first metal portion 181 that extends along first direction x and second metal portion 182 that extends along second direction y, second metal portion 182 and fourth active portion 211 are located same straight line, can make second metal portion 182 keep away from first data line 121 one side and form the light transmission area, this light transmission area can form continuous light transmission area with second active portion 143, and then be favorable to forming great trompil size, and then make things convenient for fingerprint sensor's setting, for example, can set up fingerprint sensor in the corresponding position department that has great trompil size, and then improve fingerprint identification precision.
Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, where the display panel structure shown in fig. 6 includes the pixel circuit shown in fig. 4, and referring to fig. 4 and 6, optionally, the pixel circuit includes a driving transistor T1 and a light emission controlling transistor T7 for connecting an anode of a light emitting device, and the second active layer 210 constitutes active layers of the driving transistor T1 and the light emission controlling transistor T7;
the second active layer 210 includes a fourth active portion 212 connecting the gate electrode of the driving transistor T1 and the gate electrode of the light emission controlling transistor T7, the fourth active portion 212 extending in the second direction y;
the fourth active portion 212 overlaps with the third active portion 143; a first end of the third active portion 143 is electrically connected to the gate of the driving transistor T1 through the third metal line 190, and a second end of the third active portion 143 is electrically connected to the fourth active portion 212 through a via; wherein the first terminal of the third active portion 143 is a common terminal of the first initialization transistor T4 and the compensation transistor T3.
Referring to fig. 4 and 6, in particular, in the pixel circuit shown in fig. 4, the common terminal of the compensation transistor T3 and the first initialization transistor T1 is connected to the gate of the driving transistor T1. In the display panel, a larger opening region, such as the first region five 155 in fig. 6, may also be formed, and the first region five 155 may have the same area as the first region one 151 in fig. 1, and may have the same light-transmitting area.
Optionally, the third metal line 190 is located on the fourth metal layer. The third metal line 190 is disposed on the fourth metal layer, and specifically may be disposed between the adjacent power line 130 and the data line 120, so that the same layer of metal may not overlap, and thus, a short circuit problem may not occur during signal transmission, and reliability of signal transmission is ensured.
It should be noted that, when the second end of the third active portion 143 is electrically connected to the fourth active portion 212 through a via, the second end may be a via directly connecting the second active portion 143 and the fourth active portion 212, the third active portion 143 may be connected to a metal layer through the first via, and then the metal layer is connected to the fourth active portion 212 through the second via, or the third active portion may be connected through more vias and more metal film layers, which is not specifically limited herein.
With continued reference to fig. 6, optionally, the fourth active portion 212 is co-linear with the third active portion 143.
Specifically, the fourth active portion 212 and the third active portion 143 are located on the same straight line, so that a region excluding the active layer and the metal layer is formed between the straight line where the fourth active portion 212 and the third active portion 143 are located and the third metal line 190, which is further beneficial to further improving the transmittance of the display panel.
Fig. 7 is a partial enlarged view of fig. 1 and 6 according to an embodiment of the present invention, wherein the enlarged portion may be a region near a first region one 151 in fig. 1 and a first region five 155 in fig. 6 (the first region one 151 in fig. 1 and the first region five 155 in fig. 6 are regions having the same structure), and referring to fig. 1, 6 and 7, the display panel further includes a third gate line 1121 (i.e., a second scan line one in the above embodiment) and a fourth gate line 113, the third gate line 1121 and the fourth gate line 113 are located at the first metal layer, the third gate line 1121 is located between the first gate line 1111 and the second gate line 1122, and the fourth gate line 113 is located at a side of the second gate line 1122 away from the first gate line 1111;
the first active layer 140 further includes a fifth active portion 145 between the first active portion 141 and the second active portion 142, the first active portion 141, the second active portion 142, and the fifth active portion 145 all extend in the second direction y, and the first active layer further includes a sixth active portion 146 connecting the second active portion 142 and the fifth active portion 145;
the adjacent first data line 121 and first power line 131 and first gate line 1111 and third gate line 1121 enclose a first region in which the sixth active portion 146 is located along the thickness direction of the substrate; the area of the light-transmitting region in the first region occupies at least 5% of the area of the topological structure of one pixel circuit.
With reference to fig. 2, the pixel circuit topology 150 has a width a1 microns of 26 microns and a width of 78 microns; the first region 151 can also be regarded as a rectangle, the length c1 of the first region is 14 micrometers, the width of the first region is 7.5 micrometers, and since only a small part of the first region 151 corresponding to the power line 130 is an opaque region, which is negligible here, since the first active layer 140 is a transparent active layer, the area of the transparent region in the first region 151 is not affected by the transparent active layer in the first region 151, and the ratio of the area of the transparent region in the first region 151 to the area of one pixel circuit topology 150 is (14 × 7.5)/(78 × 26) — 5.2%, which can ensure that the area of the transparent region in a single first region in the pixel circuit is large, thereby improving the light transmittance of the display panel.
On the basis of the above technical solution, optionally, the first area is located in a fingerprint identification area of the display panel. Specifically, the fingerprint identification area may refer to an area in which the fingerprint identification sensor is disposed in the thickness direction of the display panel. The first region is located the fingerprint identification region, can be so that the light that the fingerprint identification sensor received is comparatively sufficient, and then improves the fingerprint identification performance.
Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 8, a display device 10 according to an embodiment of the present invention includes the display panel 100 according to any embodiment of the present invention. The display device may be a mobile phone as shown in fig. 8, or may be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising:
a substrate;
a gate line, a data line, a power line, and a first active layer on the substrate, the first active layer being a transparent active layer, the gate line extending in a first direction, the data line extending in a second direction, the first direction crossing the second direction;
the area enclosed by the projections of the two adjacent gate lines, the data line and the power line adjacent to the data line on the substrate is a first area; along the thickness direction of the substrate, the first active layer is arranged in at least one first area, and the area of a light-transmitting area in at least one first area provided with the first active layer accounts for more than 3% of the area of a topological structure of a pixel circuit; the topological structure area of one pixel circuit is a region surrounded by two adjacent data lines and two gate lines which are connected with the same transistor in two adjacent rows of pixel circuits;
in the display panel, the total area of the light-transmitting areas in the pixel circuit topological structure accounts for 30% -40% of the total area of the pixel circuit topological structure; the total area of the pixel circuit topological structures is the area surrounded by the outermost outline of the orthogonal projection of all the pixel circuit topological structures in the display panel on the substrate.
2. The display panel according to claim 1,
the first active layer is connected to the initialization line through a contact hole.
3. The display panel according to claim 1, further comprising a second active layer, wherein the second active layer is a low-temperature polysilicon layer, and the first active layer is a metal oxide semiconductor layer;
the substrate is sequentially provided with the second active layer, the first metal layer, the second metal layer, the first active layer, the third metal layer and the fourth metal layer; wherein the gate line is located at the first metal layer and the third metal layer.
4. The display panel of claim 3, wherein the gate lines include first and second gate lines arranged in a second direction, the first and second gate lines being located at a third metal layer;
the first active layer includes at least a first active portion and a second active portion arranged in the first direction and overlapping the first gate line, a portion of the first active portion overlapping the first gate line forming a first initialization transistor, and a portion of the second active portion overlapping the first gate line forming a second initialization transistor;
the first active layer further includes a third active portion extending in the second direction, the third active portion overlapping the second gate line, and a portion where the third active portion overlaps the second gate line forms a compensation transistor;
wherein the third active portion is positioned between the adjacent first data line and the first power line.
5. The display panel according to claim 4, wherein the pixel circuit comprises a driving transistor and a light emission control transistor for connecting an anode of a light emitting device, and the second active layer constitutes an active layer of the driving transistor and the light emission control transistor;
the second active layer includes a fourth active portion connecting the drain of the driving transistor and the source of the emission control transistor, the fourth active portion extending in the second direction;
the fourth active portion is located between the third active portion and the first data line along the first direction; a first end of the third active portion is connected to the gate of the driving transistor through a first metal line, a second end of the third active portion is connected to the fourth active portion through a second metal line, and the second end of the third active portion is a common end of the first initialization transistor and the compensation transistor.
6. The display panel according to claim 5, wherein the second metal line is located in the second metal layer, and the second metal line includes a first metal portion extending in a first direction and a second metal portion extending in a second direction, and the second metal portion and the fourth active portion are located on a same straight line.
7. The display panel according to claim 4, wherein the pixel circuit comprises a driving transistor and a light emission control transistor for connecting an anode of a light emitting device, and the second active layer constitutes an active layer of the driving transistor and the light emission control transistor;
the second active layer includes a fourth active portion connecting the driving transistor gate and the light emission control transistor gate, the fourth active portion extending in the second direction;
the fourth active portion overlaps the third active portion; the first end of the third active part is electrically connected with the grid electrode of the driving transistor through a third metal wire, and the second end of the third active part is electrically connected with the fourth active part through a through hole; wherein the first terminal of the third active portion is a common terminal of the first initialization transistor and the compensation transistor.
8. The display panel according to claim 7, wherein the fourth active portion and the third active portion are located on a same line.
9. The display panel according to claim 4, further comprising a third gate line and a fourth gate line, the third gate line and the fourth gate line being located on the first metal layer, the third gate line being located between the first gate line and the second gate line, the fourth gate line being located on a side of the second gate line away from the first gate line;
the first active layer further includes a fifth active portion between the first active portion and the second active portion, the first active portion, the second active portion, and the fifth active portion all extending along the second direction, the first active layer further includes a sixth active portion connecting the second active portion and the fifth active portion;
the first data line and the first power line, and the first gate line and the third gate line which are adjacent to each other enclose a first region, and the sixth active region is located in the first region along the thickness direction of the substrate; the area of the light-transmitting area in the first area accounts for at least 5% of the topological structure area of one pixel circuit.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112909066B (en) * | 2021-02-05 | 2024-02-02 | 武汉华星光电半导体显示技术有限公司 | Display panel, preparation method of display panel and display device |
| DE112021004417T5 (en) | 2021-04-29 | 2023-06-07 | Boe Technology Group Co., Ltd. | DISPLAY PANEL AND DISPLAY DEVICE |
| CN115497411A (en) * | 2022-09-22 | 2022-12-20 | 昆山国显光电有限公司 | Pixel circuit, driving method thereof and display panel |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102193127A (en) * | 2010-03-10 | 2011-09-21 | 旭硝子株式会社 | Front plate for display, display device, and method and apparatus for manufacturing front plate for display |
| WO2013031766A1 (en) * | 2011-08-29 | 2013-03-07 | 大日本印刷株式会社 | Anti-glare film, polarized light plate, and image display device |
| CN108400149A (en) * | 2017-02-07 | 2018-08-14 | 三星显示有限公司 | Display device |
| CN108615019A (en) * | 2018-04-28 | 2018-10-02 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN108733260A (en) * | 2018-04-27 | 2018-11-02 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN109801943A (en) * | 2019-01-09 | 2019-05-24 | 昆山国显光电有限公司 | Display panel and display device |
| CN110188744A (en) * | 2019-05-28 | 2019-08-30 | 昆山国显光电有限公司 | Display panel and display device |
| CN110233166A (en) * | 2019-05-21 | 2019-09-13 | 武汉华星光电技术有限公司 | Display panel and display device |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7342112B2 (en) * | 2003-07-01 | 2008-03-11 | Ppg Industries Ohio, Inc. | Photochromic compounds |
| CN101339317B (en) * | 2007-07-04 | 2010-06-02 | 胜华科技股份有限公司 | Multi-domain liquid crystal display |
| KR102145191B1 (en) * | 2014-01-24 | 2020-08-19 | 엘지전자 주식회사 | Mobile terminal |
| WO2017038927A1 (en) * | 2015-09-03 | 2017-03-09 | 富士フイルム株式会社 | Organic electroluminescent display device |
| US9934418B2 (en) * | 2015-12-03 | 2018-04-03 | Synaptics Incorporated | Display integrated optical fingerprint sensor with angle limiting reflector |
| CN108122487B (en) * | 2016-11-30 | 2020-07-17 | 财团法人工业技术研究院 | Display panel and sensing display panel |
| CN106850101B (en) * | 2017-02-14 | 2019-09-13 | Oppo广东移动通信有限公司 | Display state control method and device |
| CN108885376A (en) * | 2017-04-25 | 2018-11-23 | 华为技术有限公司 | LCD display screen, electronic equipment and method for manufacturing LCD display screen |
| CN107025451B (en) * | 2017-04-27 | 2019-11-08 | 上海天马微电子有限公司 | A display panel and a display device |
| CN107272242B (en) * | 2017-07-28 | 2020-09-29 | 维沃移动通信有限公司 | Display screen manufacturing method and display screen |
| US11065960B2 (en) * | 2017-09-13 | 2021-07-20 | Corning Incorporated | Curved vehicle displays |
| CN108365122A (en) * | 2017-09-30 | 2018-08-03 | 云谷（固安）科技有限公司 | Display screen and electronic equipment |
| CN108336117A (en) * | 2017-09-30 | 2018-07-27 | 云谷（固安）科技有限公司 | Display screen and electronic equipment |
| CN108389878B (en) * | 2017-09-30 | 2022-01-25 | 昆山国显光电有限公司 | Display screen and display device |
| CN108257514A (en) * | 2017-09-30 | 2018-07-06 | 昆山国显光电有限公司 | Display screen, display panel drive method and its display device |
| CN108269840B (en) * | 2017-09-30 | 2021-08-13 | 昆山国显光电有限公司 | Display screen and display device |
| CN108389879B (en) * | 2017-09-30 | 2021-06-15 | 云谷（固安）科技有限公司 | Display screen and electronic equipment |
| CN108376691B (en) * | 2018-01-05 | 2021-01-08 | 惠科股份有限公司 | Display panels and display devices |
| CN108288681B (en) * | 2018-01-11 | 2021-01-22 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN108520224B (en) * | 2018-04-02 | 2020-10-09 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108898955A (en) * | 2018-07-31 | 2018-11-27 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109300963B (en) * | 2018-10-18 | 2024-04-05 | 福建华佳彩有限公司 | AMOLED display structure based on-screen fingerprint identification and preparation method thereof |
| CN109657657A (en) * | 2019-02-19 | 2019-04-19 | 武汉芯盈科技有限公司 | A kind of mobile phone small area high-precision fingerprint identification method and system based on image procossing |
| CN109950290B (en) * | 2019-04-03 | 2023-04-07 | 维沃移动通信有限公司 | AMOLED display screen, display equipment and mobile terminal |
| CN110098238A (en) * | 2019-05-15 | 2019-08-06 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| CN110232892A (en) * | 2019-05-16 | 2019-09-13 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN110492018B (en) * | 2019-08-09 | 2024-06-18 | 武汉华星光电半导体显示技术有限公司 | Display device |
| CN119730629A (en) * | 2019-08-09 | 2025-03-28 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
-
2019
- 2019-12-12 CN CN201911276826.XA patent/CN110930883B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102193127A (en) * | 2010-03-10 | 2011-09-21 | 旭硝子株式会社 | Front plate for display, display device, and method and apparatus for manufacturing front plate for display |
| WO2013031766A1 (en) * | 2011-08-29 | 2013-03-07 | 大日本印刷株式会社 | Anti-glare film, polarized light plate, and image display device |
| CN108400149A (en) * | 2017-02-07 | 2018-08-14 | 三星显示有限公司 | Display device |
| CN108733260A (en) * | 2018-04-27 | 2018-11-02 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN108615019A (en) * | 2018-04-28 | 2018-10-02 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN109801943A (en) * | 2019-01-09 | 2019-05-24 | 昆山国显光电有限公司 | Display panel and display device |
| CN110233166A (en) * | 2019-05-21 | 2019-09-13 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN110188744A (en) * | 2019-05-28 | 2019-08-30 | 昆山国显光电有限公司 | Display panel and display device |
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| Publication number | Publication date |
|---|---|
| CN110930883A (en) | 2020-03-27 |
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