CN110911478B - A two-dimensional thin film field effect transistor with sub-1nm gate length - Google Patents
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Abstract
本发明提出的一种具有亚1nm栅长的二维薄膜场效应晶体管，包括依次层叠的衬底、衬底绝缘层、单层或少层石墨烯和垂直电场屏蔽结构，及第一绝缘层、二维薄膜和三个电极；厚度在亚1nm的单层或少层石墨烯作为栅极；垂直电场屏蔽结构由第二绝缘层和沉积电场阻挡层组成，或由金属层和包覆于其外的氧化层组成；垂直电场屏蔽结构用于隔绝栅极垂直方向电场以利用栅极厚度定义栅长；第一绝缘层覆盖在衬底绝缘层的顶部以及单层或少层石墨烯和垂直电场屏蔽结构同侧，并覆盖垂直电场屏蔽结构的上表面，用于产生栅极水平方向的电场；二维薄膜作为导电沟道覆盖在第一绝缘层上。本发明利用石墨烯厚度来定义栅长，可控制场效应晶体管的栅长在亚1nm范围内。
A two-dimensional thin film field effect transistor with a gate length of sub-1nm proposed by the present invention includes a substrate, a substrate insulating layer, a single-layer or few-layer graphene and a vertical electric field shielding structure stacked in sequence, and a first insulating layer, Two-dimensional thin film and three electrodes; single-layer or few-layer graphene with a thickness of sub-1 nm as gate; vertical electric field shielding structure consisting of a second insulating layer and a deposited electric field blocking layer, or a metal layer and a coating on it The composition of the oxide layer; the vertical electric field shielding structure is used to isolate the electric field in the vertical direction of the gate to define the gate length by the gate thickness; the first insulating layer covers the top of the substrate insulating layer and the single-layer or few-layer graphene and vertical electric field shielding The structure is on the same side and covers the upper surface of the vertical electric field shielding structure for generating the electric field in the horizontal direction of the gate; the two-dimensional thin film serves as a conductive channel and covers the first insulating layer. The present invention uses the thickness of graphene to define the gate length, and can control the gate length of the field effect transistor within the range of sub-1 nm.
Description
Technical Field
The invention relates to the field of field effect transistor devices, in particular to a two-dimensional thin film field effect transistor with a sub-1 nm gate length.
Background
Moore's law development has driven the continued progress of microelectronics and the feature sizes of transistors have continued to shrink. While the feature size of transistors is reduced to sub-10 nm nodes, the continuous scaling of planar bulk silicon devices has been a serious challenge, and various new structures have been developed, i.e., devices with single gate to double gate, multi-gate and surrounding gate structures.
In a conventional planar field effect transistor, doping of a conductive channel of a silicon substrate is performed by doping or the like to form a metal-oxide-doped semiconductor structure, and the conductivity of the doped semiconductor is changed by applying a metal terminal voltage. The planar field effect transistor has the characteristic of being compatible with the traditional CMOS process, but the control capability of the metal gate on the conductive channel of the silicon substrate is weakened continuously along with the continuous reduction of the length of the conductive channel, and the short channel effect is shown. At present, there are three main types of transistors that improve or solve the short channel effect: a fin field effect transistor, a fully depleted SOI (Silicon-On-Insulator, Silicon On Insulator) field effect transistor, a wrap-around gate nanowire field effect transistor.
The fin field effect transistor changes the channel of the traditional planar field effect transistor from a planar type to a three-dimensional type, so that a grid can be switched on and off from a top control device and can also be switched on and off from two side control devices similar to a fish fin. Compared with the traditional planar field effect transistor, the structure has stronger grid control capability, can obviously improve the short channel effect, can greatly reduce the channel length of the field effect transistor, and has good process compatibility, but with the continuous development of microelectronic technology, if the field effect transistor with the length of less than 10nm is used, the problems of overhigh equipment cost and the like can occur.
The fully depleted SOI field effect transistor utilizes the oxide layer to isolate silicon, so that when the transistor works in an MOS structure, a silicon film is fully depleted, a floating neutral region does not exist, the Kink effect (warping effect) caused by a floating substrate is basically eliminated, and the control capability of a grid on a channel is greatly improved due to the fact that the silicon film on the oxide layer is very thin (generally, the silicon film is 200 nm-80 um), and the short channel effect can also be well improved. However, the SOI device has a large leakage current and a parasitic lateral bipolar transistor effect, and the SOI device having a thin silicon film is also subject to cost.
The wrap-around nanowire field effect transistor addresses short channel effects in a manner similar to the fin field effect transistor described above, with the device gate surrounding the entire conductive channel. Depending on the application, the surrounding gate nanowire field effect transistor can be divided into 2 or 4 equivalent gates. Such transistors present a number of obstacles in terms of complex gate fabrication, nanowires and contacts; besides the silicon material, other materials such as indium gallium arsenic, germanium nanowires and the like are also needed, and the compatibility of the materials in the traditional CMOS process is reduced, so that the cost is greatly increased.
For the three technical solutions, in the process of developing the precision of the lithography machine, the field effect transistor made of bulk material or two-dimensional material is optimized to improve the control force of the gate on the conductive channel, so as to further reduce the effective channel length. How to further reduce the effective channel length without depending on the precision of the lithography machine becomes the focus of the current research.
In addition, the two-dimensional material is a natural and good ultrathin body due to the thickness of the atomic layer of the two-dimensional material, and can effectively inhibit the short channel effect. In the recent research process, the two-dimensional material has the characteristics superior to the traditional silicon-based material in various aspects, and has obvious advantages in becoming a candidate material of a mainstream material in the next generation CMOS process. In recent years, a very wide range of basic research is conducted on transistors made of two-dimensional materials, however, how to prepare a transistor with a very narrow effective gate length through the thickness of an atomic layer of the two-dimensional material is still a problem to be solved.
For field effect transistors with two-dimensional material as channel, the gate length can be reduced to 1nm (Desai S B, madhvathy S R, small a B, et al2transistors with1-nanometer gate lengths[J]Science,2016,354(6308): 99-102). While a technique for gate lengths less than 1nm has not been proposed.
In summary, there is no clear solution in the semiconductor industry to further realize transistors with gate length below 1 nm.
Disclosure of Invention
In view of the above problems in the prior art, the present invention provides a two-dimensional thin film transistor having a sub-1 nm gate length; according to the invention, the thickness of a single-layer or few-layer graphene atomic layer level and good conductivity of the single-layer or few-layer graphene atomic layer level are used as side grid electrodes, and an electric field in the vertical direction is shielded by metal deposited with an electric field barrier layer, so that a sub-1 nm grid length two-dimensional thin film field effect transistor based on single-layer or few-layer graphene is realized, the grid length of the traditional silicon-based field effect transistor can be further reduced, and the silicon-based field effect transistor can be widely applied to the field of.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a two-dimensional thin film field effect transistor with a sub-1 nm gate length, which is characterized by comprising a substrate, a substrate insulating layer, single-layer or few-layer graphene, a vertical electric field shielding structure, a first insulating layer, a two-dimensional thin film and three electrodes, wherein the substrate, the substrate insulating layer, the single-layer or few-layer graphene and the vertical electric field shielding structure are sequentially stacked;
the single-layer or few-layer graphene is used as a grid, and the thickness of the graphene is sub-1 nm;
the vertical electric field shielding structure consists of a second insulating layer and a deposited electric field barrier layer stacked on the second insulating layer; or the oxide layer is formed by the autoxidation mode of the metal layer; the vertical electric field shielding structure is used for isolating an electric field in the vertical direction of the single-layer or few-layer graphene so as to define the gate length by using the thickness of the gate;
the first insulating layer covers the top of the substrate insulating layer and the same side of the single-layer or few-layer graphene and the vertical electric field shielding structure in an etching mode, one end of the first insulating layer extends to the other side of the vertical electric field shielding structure to cover the upper surface of the vertical electric field shielding structure, and a step-shaped first insulating layer is formed and used for generating an electric field of the single-layer or few-layer graphene in the horizontal direction;
the two-dimensional film covers the first insulating layer in a step shape to serve as a conducting channel, and the upper surface of the lower step of the two-dimensional film is lower than the lower surface of the single-layer or few-layer graphene;
the first electrode and the second electrode are respectively arranged on the upper step surface and the lower step surface of the two-dimensional film and used for leading out an electrical signal of the two-dimensional film; and the third electrode is simultaneously connected with the substrate insulating layer and the single-layer or few-layer graphene and is used for transmitting a voltage signal required by the grid electrode.
The invention has the characteristics and beneficial effects that:
the invention provides a brand-new solution for further reducing the gate length of a field effect transistor and capable of being prepared in a large scale, and the principle is that the atomic layer thickness of graphene and good conductivity of the graphene are used as lateral gates, a dielectric layer is transferred or deposited to be used as an insulating layer, and an electric field in the vertical direction is shielded by depositing an electric field barrier layer, so that the graphene-based lateral gate two-dimensional thin film field effect transistor is realized. Graphene is used as a two-dimensional material, and due to the ultrathin thickness of the graphene, the limitation of breaking through the size reduction of the existing silicon-based transistor is achieved, the further development of Moore's law is maintained, and the graphene can be applied to a new chip process for further reducing the characteristic size. The preparation process of the device is compatible with the traditional silicon-based process, particularly, the vertical electric field shielding structure can be formed by adopting a metal autoxidation mode, so that the process complexity and the preparation cost are further reduced, and the device has wide application prospects and spaces in smaller-size and larger-scale analog circuits and digital logic circuits.
Drawings
Fig. 1 is a cross-sectional view of a two-dimensional thin film transistor structure having a sub-1 nm gate length proposed in embodiment 1 of the present invention;
fig. 2 is a cross-sectional view of a two-dimensional thin film transistor structure having a sub-1 nm gate length according to example 2 of the present invention;
FIG. 3 is a flow chart of a method for fabricating a two-dimensional thin film transistor with a sub-1 nm gate length according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The two-dimensional thin film field effect transistor with the sub-1 nm gate length provided by the embodiment 1 of the invention has a structure shown in fig. 1, and comprises a substrate 101, a substrate insulating layer 102, a single-layer graphene 103 and a vertical electric field shielding structure which are sequentially stacked, and further comprises an insulating layer 106, a two-dimensional thin film 107 and three electrodes (108, 109 and 110); the thickness of the single-layer graphene 103 is 0.34nm, and the single-layer graphene serves as a grid electrode of the field effect transistor; the vertical electric field shielding structure consists of an insulating layer 104 and a deposited electric field barrier layer 105 laminated on the insulating layer, and is used for isolating an electric field in the vertical direction of the single-layer graphene 103 so as to define the gate length by using the thickness of the gate; the insulating layer 106 covers the top of the substrate insulating layer 102 and the same side of the single-layer graphene 103, the insulating layer 104 and the deposited electric field barrier layer 105 in an etching mode, one end of the insulating layer 106 extends to the other side of the deposited electric field barrier layer 105 to cover the upper surface of the deposited electric field barrier layer 105, a step-shaped insulating layer 106 is formed and used for generating an electric field of the single-layer graphene 103 in the horizontal direction, the core part of the lateral gate structure is formed by the single-layer graphene 103 and the insulating layer 106, the electric field shielding layer structure can shield the electric field from the vertical direction of the single-layer graphene 103, the gate length of the field effect transistor is further reduced, and the lateral gate structure is manufactured in a mode of sequentially transferring, patterning, depositing and etching; the two-dimensional film 107 covers the insulating layer 106 in a step shape to serve as a conductive channel, the change of carrier concentration can be completed under the regulation and control of an electric field, and the upper surface of the lower step of the two-dimensional film 107 is lower than the lower surface of the single-layer graphene 103 to ensure the formation of the channel; the electrode 109 and the electrode 108 are respectively arranged on the upper surfaces of the upper step and the lower step of the two-dimensional film 107 and are used for deriving the electrical signal of the two-dimensional film 107; the electrode 110 is connected to both the substrate insulating layer 102 and the single layer graphene 103 for transmitting a voltage signal required for the gate.
The specific implementation and functions of each component device in this embodiment are described as follows:
the substrate 101 is made of a conductive or insulating material, and in this embodiment, heavily doped P-type Si is selected to provide physical support for the entire transistor and is connected to the substrate insulating layer 102.
The lower surface of the substrate insulating layer 102 is connected with the substrate 101, the upper surface of the substrate insulating layer is respectively connected with the lower surfaces of the single-layer graphene 103 and the insulating layer 106, and the embodiment selects 300nm SiO grown by thermal oxidation2As a substrate insulating layer 102, the single-layer graphene 103 can be used for electrically isolating electrical signalsAnd (3) properly etching to realize the gate regulation effect of the single-layer graphene 103 and the two-dimensional film 107.
The single-layer graphene 103 is used as a grid electrode, the lower surface of the single-layer graphene is connected with the substrate insulating layer 102, the upper surface of the single-layer graphene is connected with the insulating layer 104 of the electric field shielding layer structure, one etched side surface of the single-layer graphene 103 is connected with the insulating layer 106, the thickness of the selected single-layer graphene is 0.34nm, in addition, few layers of graphene can be adopted, and the total thickness can be controlled within 1 nm.
The lower surface of the insulating layer 104 is in contact with the single-layer graphene 103, the upper surface of the insulating layer 104 is connected with the deposited electric field barrier layer 105, the etched side surface of the insulating layer 104 is connected with the insulating layer 106, the insulating layer is used for isolating the single-layer graphene 103 from the deposited electric field barrier layer 105, and the insulating layer 104 is made of an oxide insulator, a two-dimensional insulator or a flexible insulator, and is preferably less than 10nm thick. For this example, a metallic autooxidized alumina material was used.
The deposited electric field barrier layer 105 has a lower surface connected to the insulating layer 104 and an upper surface and an etched side surface connected to the insulating layer 106, and is used to shield an electric field from the single-layer graphene 103 in a vertical direction, and the etching is completed by using a self-alignment technique to realize a relatively steep gate control region. The material from which the electric field blocking layer 105 is made includes metals and other conductive non-metals such as highly doped p-type and n-type silicon, germanium semiconductors, flexible electrode materials, etc. For this example, 15nm of metallic Al.
The lower surfaces of the upper step and the lower step of the insulating layer 106 are respectively contacted with the upper surfaces of the deposition electric field barrier layer 105 and the substrate insulating layer 102, the upper surface of the insulating layer 106 is connected with the two-dimensional film 107, and the side surface of the insulating layer 106 is simultaneously contacted with the same side of the substrate insulating layer 102, the single-layer graphene 103, the insulating layer 104 and the deposition electric field barrier layer 105, so that a dielectric layer of a grid electrode is realized, and a field effect transistor structure is realized. The material of which the insulating layer 106 is made includes a metal oxide, a two-dimensional insulator, and a flexible insulator. For this example, a 10nm thick hafnium oxide material using atomic layer deposition.
The bottom of the two-dimensional film 107 is connected with the insulating layer 106, the tops of the upper step and the lower step of the two-dimensional film 107 are respectively connected with the first electrode 109 and the second electrode 108, and a field effect transistor channel is formed in the two-dimensional film. The two-dimensional film 107 may be made of a two-dimensional film having semiconductor characteristics, an oxide semiconductor, or the like, and has a thickness ranging from 0.33nm to 50nm, and for the present embodiment, is a single layer of molybdenum disulfide having a high carrier mobility.
The bottom of the first electrode 109 and the bottom of the second electrode 108 are respectively connected to the bottom surfaces of the upper step and the lower step of the two-dimensional film 107, so as to transmit the electrical signal of the two-dimensional film field effect transistor. The materials of the first electrode 109 and the second electrode 108 include metals and other conductive non-metals, such as highly doped p-type and n-type silicon, germanium semiconductors, flexible electrode materials, etc., and the materials of the first electrode and the second electrode may be the same or different, and for the present embodiment, are metal Pt of 30 nm.
The bottom of the third electrode 110 is connected to the single-layer graphene 103 and the substrate insulating layer 102 at the same time, and is used for transmitting a voltage signal required by the gate. The material of which the third electrode 110 is made includes metals and other conductive non-metals, highly doped p-type and n-type silicon, germanium semiconductors, flexible electrode materials, and the like. For this example, 30nm of metallic Pt.
Example 2
Referring to fig. 2, the difference between this embodiment and embodiment 1 is that the vertical electric field shielding structure is composed of a metal layer and an oxide layer coated outside the metal layer, and the oxide layer is formed by auto-oxidation of the metal layer. In this embodiment, the metal layer is 25nm metal aluminum, and may also be copper, magnesium, zinc or lead with dense autoxidation characteristics, and the thickness of the oxide layer is 5-10 nm. The vertical electric field shielding structure is formed in an autoxidation mode, so that the process complexity can be further reduced. The rest of this embodiment is the same as embodiment 1, and will not be described herein.
Referring to fig. 3, it is a flow chart of the preparation of the two-dimensional thin film transistor with sub-1 nm gate length according to the present invention, the method includes:
s101: preparing graphene 103 on a substrate 101 and a substrate insulating layer 102 by growing or transferring, and combining patterning and etching, wherein the patterning mode is as follows: mask exposure or electron beam exposure, and the etching method is plasma dry etching or chemical reaction etching.
S102: transferring the two-dimensional insulating film by adopting an atomic layer deposition method or a wet method; or a vertical electric field shielding structure is prepared on the graphene 103 by adopting a metal autoxidation mode.
S103: the electric field barrier layer 105 is deposited on the insulating layer 104 by patterning processes such as general lithography (mask exposure) or electron beam exposure. For the case of forming the vertical electric field shielding structure by metal autoxidation, the step is absent.
S104: the insulating layer 106 is prepared on the electric field barrier layer 105 or the oxide layer 112 by atomic layer deposition or wet transfer two-dimensional insulating film or metal autoxidation. If the method is an atomic layer deposition or wet transfer method, the insulating layer 106 needs to be prepared by subsequent patterning and etching.
S105: the two-dimensional film 107 with the conducting channel is prepared by adopting a wet transfer or growth mode and then by a patterning and etching method, wherein the patterning mode is as follows: mask exposure or electron beam exposure, and the etching method is plasma dry etching or chemical reaction etching.
S106: the first electrode 109 and the second electrode 108 are prepared on the two-dimensional film 107 by using patterning processes such as general lithography or electron beam exposure. This step may be performed separately to prepare the first electrode 109 and the second electrode 108 of different materials.
S107: and preparing a third electrode 110 on the substrate insulating layer 102 and the graphene 103 by using patterning processes such as common photoetching or electron beam exposure. This step may be performed at any step after step S102.
Claims (6)
1. The two-dimensional thin film field effect transistor with the sub-1 nm gate length is characterized by comprising a substrate (101), a substrate insulating layer (102), a single-layer or few-layer graphene (103) and a vertical electric field shielding structure which are sequentially stacked, and further comprising a first insulating layer (106), a two-dimensional thin film (107) and three electrodes (108, 109 and 110);
the single-layer or few-layer graphene (103) is used as a grid electrode and has the thickness of sub-1 nm;
the vertical electric field shielding structure consists of a second insulating layer (104) and a deposited electric field barrier layer (105) laminated on the second insulating layer; or the oxide layer is formed by the autoxidation mode of the metal layer; the vertical electric field shielding structure is used for isolating an electric field in the vertical direction of the single-layer or few-layer graphene (103) so as to define the gate length by using the thickness of the gate;
the first insulating layer (106) covers the top of the substrate insulating layer (102) in an etching mode, and the single-layer or few-layer graphene (103) and the vertical electric field shielding structure are on the same side, one end of the first insulating layer (106) extends to the other side of the vertical electric field shielding structure to cover the upper surface of the vertical electric field shielding structure, and a step-shaped first insulating layer (106) is formed and used for generating an electric field of the single-layer or few-layer graphene (103) in the horizontal direction;
the two-dimensional film (107) covers the first insulating layer (106) in a step shape to serve as a conducting channel, and the upper surface of the lower step of the two-dimensional film (107) is lower than the lower surface of the single-layer or few-layer graphene (103);
the first electrode (109) and the second electrode (108) are respectively arranged on the upper step surface and the lower step surface of the two-dimensional film (107) and are used for deriving the electric signal of the two-dimensional film (107); the third electrode (110) is simultaneously connected with the substrate insulating layer (102) and the single-layer or few-layer graphene (103) and is used for transmitting a voltage signal required by the grid.
2. The two-dimensional thin film transistor of claim 1, wherein in the vertical electric field shielding structure, the second insulating layer (104) is made of a two-dimensional insulating film or a flexible insulating film by atomic layer deposition or wet transfer; the deposited electric field barrier layer (105) is made of a metal or a conductive non-metal by a patterning process.
3. The two-dimensional thin film transistor of claim 1, wherein the metal layer of the vertical electric field shielding structure is a metal with a dense autoxidation property.
4. The two-dimensional thin film transistor according to claim 1, wherein the material of the first insulating layer (106) comprises a metal oxide, a two-dimensional insulating film, and a flexible insulating film; the metal oxide is formed by means of metal autoxidation.
5. The two-dimensional thin film transistor according to claim 1, wherein the two-dimensional thin film (107) is formed by wet transfer or growth, and then patterned and etched, and the two-dimensional thin film (107) is selected from two-dimensional thin films having semiconductor characteristics or oxide semiconductors.
6. A two-dimensional thin film transistor according to claim 1, wherein each electrode is made of metal or conductive non-metal.
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| Ultrathin Piezotronic Transistors with 2 nm Channel Lengths;Longfei Wang,et. al.;《ACS Nano》;20180427;第12卷;全文 * |
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| CN110911478A (en) | 2020-03-24 |
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