CN110908491B - Power consumption control method, control part and electronic system thereof - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to a power consumption control method, a control component and an electronic system thereof. The provided power consumption control method comprises the following steps: and controlling the closing, opening or working efficiency of the processing unit according to the state indication of the state register in the processing unit.
Description
Technical Field
The present application relates to power consumption control of circuits, and in particular to power consumption control of error correction units of memory controllers.
Background
The storage controller provides high performance and low latency data access services for the host. FIG. 1 illustrates a block diagram of a prior art memory controller. The Memory controller operates a plurality of NVM (Non-Volatile Memory) chips in parallel through a plurality of channels. Typically, NVM storage media are unreliable, so the memory controller needs to ensure data correctness with an error correction unit.
The memory controller controls the process of writing data to and reading data from the NVM chip. To improve the throughput of the error correction unit, the memory correction unit typically integrates multiple encoders and multiple decoders. In the example of FIG. 1, the error correction unit of the memory controller includes a plurality of error correction encoders (120, 122, and 124) and a plurality of error correction decoders (130, 132, and 134). In general, all encoders and decoders are turned on in order to guarantee peak read-write performance. LDPC (low density parity check, low Density Parity Check Code) codes and BCH codes are error correction codes commonly used in memory controllers.
The memory controller writes data to the NVM chip via a write path on which a plurality of error correction encoders may operate in parallel, e.g., each error correction encoder performs error correction encoding on the data written to one of the memory cells of the NVM chip, and the memory controller also writes the encoded data to the NVM chip. On the read path, a plurality of error correction decoders may operate in parallel, e.g., each error correction decoder performs error check decoding on read data from one of the memory cells of the NVM chip, so that the memory controller obtains the decoded correct data.
Disclosure of Invention
The encoder and decoder of the low-delay, high-bandwidth error correction unit consume more power. It is necessary to control the power consumption of the error correction unit. Particularly, under the condition of low read-write strength, the individual coder (decoder) works under idle or low pressure for a long time, but the clock and the power supply still exist at the moment, so that the power consumption of the memory controller is too high under the condition of low read-write bandwidth.
According to a first aspect of the present application, there is provided a first power consumption control method according to the first aspect of the present application, wherein the turning-off, turning-on or operating efficiency of the processing unit is controlled in accordance with a status indication of a status register in the processing unit.
According to a first power consumption control method of a first aspect of the present application, there is provided a second power consumption control method according to the first aspect of the present application, wherein according to a status register in each processing unit, the corresponding processing unit is turned on or turned off, or the operating frequency of the processing unit is adjusted.
According to a second power consumption control method of the first aspect of the present application, a third power consumption control method according to the first aspect of the present application is provided, wherein if the status register of the processing unit with the lowest priority is smaller than the first threshold value, the processing unit with the lowest priority is turned off.
According to a first or second power consumption control method of a first aspect of the present application, there is provided a fourth power consumption control method according to the first aspect of the present application, wherein the first processing unit is turned off or the frequency of the first processing unit is reduced in response to the state register of the first processing unit being smaller than a first threshold value, and the second processing unit having a lower priority than the first processing unit being already in an off state.
According to a first to third power consumption control methods of the first aspect of the present application, a fifth power consumption control method according to the first aspect of the present application is provided, wherein if the status register of the first processing unit is greater than a second threshold value, a second processing unit with a lower priority than the first processing unit is turned on, or the frequency of the second processing unit is increased.
According to a fourth or fifth power consumption control method of the first aspect of the present application, there is provided the sixth power consumption control method according to the first aspect of the present application, wherein when data to be processed is present, the data to be processed is preferentially scheduled to a first processing unit with a high priority, and if the first processing unit is currently unable to receive new data to be processed, the data to be processed is scheduled to a second processing unit with a lower priority than the first processing unit.
According to a first to sixth power consumption control method of the first aspect of the present application, there is provided a seventh power consumption control method according to the first aspect of the present application, wherein the status register indicates a ratio of times of an operating state to an idle state of the processing unit.
According to a first power consumption control method of a first aspect of the present application, there is provided an eighth power consumption control method according to the first aspect of the present application, wherein the status register indicates the power consumption of the processing unit.
According to a second aspect of the present application, there is provided a first error correction unit according to the second aspect of the present application, wherein the error correction unit comprises one or more processing units and a power consumption management element; the processing unit comprises a state register which is used for indicating the working state of the processing unit to which the processing unit belongs; the power consumption management element is used for controlling the closing, opening or working frequency of the processing unit according to the state indication.
According to a first error correction unit of a second aspect of the present application, a second error correction unit according to the second aspect of the present application is provided, wherein the power consumption management element is specifically configured to turn on or off the corresponding processing unit or adjust the operating frequency of the processing unit according to a status register in each processing unit.
According to a second error correction unit of the second aspect of the present application, a third error correction unit according to the second aspect of the present application is provided, wherein the power consumption management unit is specifically configured to shut down the lowest priority processing unit when the status register of the lowest priority processing unit is smaller than the first threshold.
According to a first error correction unit of a second aspect of the present application, there is provided a fourth error correction unit according to the second aspect of the present application, wherein the power consumption management unit is specifically configured to switch off or reduce the frequency of the first processing unit when the second processing unit having a lower priority than the first processing unit is already in the off state in response to the status register of the first processing unit being smaller than the first threshold.
According to a first error correction unit of a second aspect of the present application, there is provided a fifth error correction unit according to the second aspect of the present application, wherein the power consumption management unit is specifically configured to turn on a second processing unit having a lower priority than the first processing unit or to increase the frequency of the second processing unit when the status register of the first processing unit is greater than a second threshold.
According to a third aspect of the present application, there is provided the first control section according to the third aspect of the present application, wherein the first control section includes an error correction unit and a CPU; the error correction unit includes one or more processing units for processing data read from the NVM chip; and the CPU is used for controlling the closing, opening or working efficiency of the processing unit.
According to a first control component of a third aspect of the present application, there is provided a second control component of the third aspect of the present application, wherein the error correction unit comprises one or more processing units for processing data read from the NVM chip.
According to a second control unit of a third aspect of the present application, there is provided a third control unit according to the third aspect of the present application, wherein the error correction unit comprises a status register for indicating the operating status of each processing unit.
According to a first to third control means of a third aspect of the present application, there is provided a fourth control means according to the third aspect of the present application, wherein a status register is provided for indicating the busy/idle ratio, the power consumption and/or the power consumption level of each processing unit.
According to a fourth control unit of the third aspect of the present application, there is provided a fifth control unit according to the third aspect of the present application, wherein the CPU comprises a switching or clock frequency of each processing unit for controlling the power consumption of each processing unit by adjusting the switching or clock frequency of the processing unit.
According to a fifth control means of the third aspect of the present application, there is provided the sixth control means according to the third aspect of the present application, wherein the CPU includes power consumption management software for controlling the power consumption of the respective processing units.
According to a fourth control unit of the third aspect of the present application, there is provided the seventh control unit of the third aspect of the present application, wherein the CPU sets the operation state of each processing unit in response to a large number of read commands acquired or in response to receiving an adjustment of the operation state or the power consumption level by the host.
According to a fourth aspect of the present application, there is provided the first electronic system according to the fourth aspect of the present application, wherein the control unit further comprises an NVM chip; the control unit performs error correction processing on read data from the NVM chip.
Drawings
The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:
FIG. 1 illustrates a block diagram of a prior art memory controller;
FIG. 2 illustrates a schematic diagram of power consumption control of an error correction unit according to an embodiment of the present application;
FIG. 3 illustrates a schematic diagram of power consumption control of an error correction unit according to another embodiment of the present application;
FIG. 4 is a flow chart of controlling the reduction of decoder power consumption according to an embodiment of the present application;
fig. 5 is a flow chart of controlling the turning on of a decoder to improve performance according to an embodiment of the present application.
Fig. 6 is a schematic diagram of power consumption control of a control unit according to yet another embodiment of the present application.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the present application.
Fig. 2 shows a schematic diagram of power consumption control of an error correction unit according to an embodiment of the present application.
Although the principles, systems, and methods of power consumption control are described in the embodiments of the present application in terms of error correction units, it should be understood that the power consumption control methods provided herein may be applied to other electronic systems having multiple, functionally similar processing units, each processing unit processing tasks independently.
Referring to fig. 2, the error correction unit includes a plurality of processing units, which are encoders or decoders. The following embodiments are described by taking decoders (210, 212, and 214) as examples. Each decoder performs error correction decoding on the data read out from the NVM chip, for example, according to a decoding algorithm of the LDPC code. The scheduling unit 220 selects one of the free decoders, the selected decoder decoding the currently read data. It should be noted that the same power consumption control method as that applied to the decoder in this embodiment may be applied to the encoder, and will not be described here again.
By way of example, the scheduling unit 220 adopts a priority scheduling method. Decoder 210 has the highest priority (highest priority indicated by a "1" in the connection of scheduling unit 220 to decoder 210), decoder 212 has the next highest priority (middle priority indicated by a "2" in the connection of scheduling unit 220 to decoder 212), and decoder 214 has the lowest priority (lowest priority indicated by a "3" in the connection of scheduling unit 220 to decoder 214).
When data is to be decoded, the scheduling unit 220 preferentially sends the data to the decoder 210 for decoding. If the decoder 210 is currently unable to receive new data to be decoded because of the decoding task being processed, the scheduling unit 220 transmits the data to the decoder 212. In this scheduling mode, the probability that decoder 210 is invoked is highest, the probability that decoder 212 is scheduled is next lower, and the probability that decoder 214 is scheduled is lowest.
According to an embodiment of the present application, each decoder includes a status register for, for example, recording or indicating the ratio of times the decoder is in an active state to an idle state (referred to as the "busy/idle ratio"). For example, the time when the decoder is in an active state versus the time when it is in an idle state is counted periodically (e.g., every 100 ms), and the ratio of the two times is taken as the busy/idle ratio and recorded in the status register. The decoder 210, the decoder 212, and the decoder 214 each include a status register and record their busy/idle ratio. In addition to the busy/idle ratio, the status register also indicates, for example, the power consumption of the decoder, which also indicates the workload of the decoder.
The error correction unit further includes a power consumption management unit 240. The power consumption management unit 240 turns on or off one or more decoders according to the status register of each decoder. For example, if the busy/idle ratio of the decoder 214 with the lowest priority is less than 10%, the power consumption management unit 240 turns off the decoder 214 to reduce the power consumption of the error correction unit. Since the priority of the decoder 214 is the lowest, the decoding task it handles is the least, so in the case of a low busy/idle ratio of the decoder 214, the decoding capability of the entire memory controller after turning off the decoder 214 is less affected. And the decoder 214 with the lowest priority is turned off preferentially, with minimal impact on the schedule unit 220. Alternatively or further, on the basis of the turned-off decoder 214, the power consumption management unit 240 further turns off the decoder 212 if the busy/idle ratio of the next highest priority decoder 212 is also smaller than a specified threshold. Further, on the basis that the decoder 212 has been turned off, if the busy/idle ratio of the decoder 210 with the highest priority is also smaller than the specified threshold, the power consumption management unit 240 further turns off the decoder 210.
Alternatively, the power consumption management unit 240 controls the power consumption by reducing the operating frequency of the selected decoder.
In still alternative embodiments, each decoder includes a power consumption management component without implementing power consumption control by means of the power consumption management unit 240. In one example, the power consumption management component of each decoder decides whether to turn off its decoder based on the busy/idle ratio or power consumption indicated by its decoder's status register.
With continued reference to fig. 2, according to yet another embodiment of the present application, the power consumption management unit 240 also controls the turning on of the turned-off decoder to enhance the decoding capability of the error correction unit.
For example, decoder 210 is in operation, while decoder 212 and decoder 214 have been turned off. The power consumption management unit 240 identifies the operation state of the decoder 210 according to the state register of the decoder 210. If the decoder 210 is in an excessively busy state for a long period of time, the power consumption management unit 240 turns on the decoder 212 to share the operation of the decoder 210. For example, the power consumption management unit 240 acquires the busy/idle ratio indicated by the status register of the decoder 210, and turns on the decoding unit 212 if the busy/idle ratio is greater than a specified threshold or greater than a specified threshold for a long period of time. Optionally, the threshold for turning on the decoder is greater than the threshold for turning off the decoder.
Alternatively, or further, after turning on the decoder 212, the power consumption management unit further turns on the decoder 214 to further share the decoding task according to the state register of the decoder 212 identifying that the decoder 212 is also in an excessively busy state.
Alternatively, the power consumption management unit 240 controls the power consumption by increasing the operating frequency of the selected decoder.
Fig. 3 shows a schematic diagram of power consumption control of an error correction unit according to another embodiment of the present application.
According to the embodiment shown in fig. 3, each decoder includes a power consumption management part without implementing power consumption control by means of the power consumption management unit 240. The power management component of each decoder is also coupled to a lower priority decoder than itself. For example, the power consumption management component of the decoder 312 is coupled to the lower priority decoder 314 to obtain the operating state of the decoder 314. The power consumption management component of the decoder determines to set the decoder itself to an off (or low power consumption) state when, for example, the busy/idle ratio indicated by the status register of the decoder itself is less than a threshold and the coupled lower priority decoder than itself is already in the off (or low power consumption) state.
Alternatively or further, the power consumption management component of each decoder is coupled to a higher priority decoder than itself. For example, the power consumption management component of the decoder 312 is coupled to the higher priority decoder 310 to obtain the operational state of the decoder 310. The power consumption management part of the decoder determines to turn on the decoder of itself when the decoder is in a turned-off or low power consumption state and the coupled decoder having a higher priority than the decoder of itself is already in an excessively busy state.
Alternatively, or in addition, by monitoring the busy/idle ratio of the decoders, it is also decided whether to switch the decoder or change the frequency of the decoder by monitoring the power consumption of each decoder.
Fig. 4 is a flow chart of controlling the reduction of decoder power consumption according to an embodiment of the present application.
As shown in fig. 4, a status indication of a status register in the decoder is obtained (410); a determination is made as to whether the status indication is less than a first threshold (420), and if so, the decoder is placed in a low power consumption state (430).
Fig. 5 is a flow chart of controlling the turning on of a decoder to improve performance according to an embodiment of the present application.
As shown in fig. 5, a status indication of a status register in the decoder is obtained (510); a determination is made as to whether the state indication is greater than a second threshold (520), and if so, the decoder is placed in a high performance state (530).
Fig. 6 is a schematic diagram of power consumption control of a control unit according to yet another embodiment of the present application.
The control section includes a CPU 60 and an error correction unit 61. The control means is, for example, a control means of a memory controller. The error correction unit 61 includes a plurality of decoders (610, 612, and 614), each of which performs error correction decoding on data read out from the NVM chip, respectively. The error correction unit further comprises a status register indicating the operating status of the decoders of the error correction unit. For example, the status register indicates the busy/idle ratio, power consumption, and/or power consumption level of each decoder. Optionally, the error correction unit 61 further comprises one or more encoders (not shown).
The CPU 60 is coupled to the error correction unit 61 and acquires the operation states of the respective decoders by accessing the state registers. And the CPU 60 also sets the switching or clock frequency of each decoder to implement power consumption control. The power consumption control is implemented by, for example, software running in the CPU 60.
Alternatively or in addition to setting the operating state of each decoder according to, for example, a workload expectation for a future period of time, in accordance with the power consumption control strategy employed in the embodiment described in connection with fig. 2. For example, the control unit sets the operating state of each decoder in response to a large number of read commands being acquired, or in response to receiving an adjustment of the host to an operating state or power consumption registration, without entirely relying on the operating state indication given by the state register.
The power consumption control method according to an embodiment of the present invention may be implemented by software, hardware, firmware, FPGA (field programmable gate array ) and/or ASIC (application specific integrated circuit, application Specific Integrated Circuit), etc. The power consumption control method according to the embodiment of the invention can be applied to storage equipment integrated with a storage controller, including but not limited to a solid state disk, a USB flash disk and an SD card, and can also be applied to portable electronic equipment such as a mobile phone and a tablet personal computer comprising an integrated circuit chip and other various electronic equipment.
Although the examples referred to in the present application are described for illustrative purposes only and not as limitations on the present application, variations, additions and/or deletions to the embodiments may be made without departing from the scope of the application.
Many modifications and other embodiments of the application set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (10)
1. A power consumption control method, characterized by comprising: controlling the closing, opening or working frequency of the processing unit according to the scheduled priority of the processing unit according to the state indication of a state register in the processing unit, wherein the processing unit is an encoder or a decoder; wherein the priority is used to indicate the order in which the processing units are scheduled; and
preferentially closing the processing units with low priority or controlling the working frequency of the processing units; and preferentially turning on the processing unit with high priority or controlling the working frequency thereof.
2. The power consumption control method according to claim 1, wherein the lowest priority processing unit is turned off if the status register of the lowest priority processing unit is smaller than the first threshold.
3. The power consumption control method of claim 2, wherein the first processing unit is turned off or the frequency of the first processing unit is reduced in response to the status register of the first processing unit being less than a first threshold value and a second processing unit having a lower priority than the first processing unit having been in an off state.
4. A power consumption control method according to any one of claims 1-3, characterized in that if the status register of the first processing unit is larger than the second threshold value, the second processing unit having a lower priority than the first processing unit is turned on or the frequency of the second processing unit is increased.
5. The power consumption control method according to claim 4, wherein when data to be processed is present, the data to be processed is preferentially scheduled to a first processing unit having a higher priority, and if the first processing unit is currently unable to receive new data to be processed, the data to be processed is scheduled to a second processing unit having a lower priority than the first processing unit.
6. An error correction unit, characterized in that the error correction unit comprises one or more processing units and a power consumption management element;
wherein the processing unit is an encoder or a decoder; the processing unit comprises a state register which is used for indicating the working state of the processing unit to which the processing unit belongs;
the power consumption management element is used for controlling the closing, opening or working frequency of the processing unit according to the state indication and the scheduled priority of the processing unit; wherein the priority is used to indicate the order in which the processing units are scheduled; and
preferentially closing the processing units with low priority or controlling the working frequency of the processing units; or the processing unit with higher priority is preferentially started or the working frequency of the processing unit is controlled.
7. A control unit, characterized by comprising: an error correction unit and a CPU;
the error correction unit comprises one or more processing units, which are encoders or decoders, for processing the data read from the NVM chip;
the CPU is used for controlling the closing, opening or working efficiency of the processing unit according to the scheduled priority of the processing unit; wherein the priority is used to indicate the order in which the processing units are scheduled; and
preferentially closing the processing units with low priority or controlling the working frequency of the processing units; and preferentially turning on the processing unit with high priority or controlling the working frequency thereof.
8. The control unit of claim 7, characterized by a status register for indicating the busy/idle ratio, power consumption and/or power consumption level of the respective processing unit.
9. The control unit of claim 7, wherein the CPU sets the operating state of each processing unit in response to a number of read commands being acquired or in response to receiving an adjustment of the operating state or power consumption level by the host.
10. An electronic system comprising the control component of any of claims 7-9, further comprising: an NVM chip; the control unit performs error correction processing on read data from the NVM chip.
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