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CN110896036A - A packaging structure and packaging method - Google Patents

A packaging structure and packaging method Download PDF

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Publication number
CN110896036A
CN110896036A CN201910662160.5A CN201910662160A CN110896036A CN 110896036 A CN110896036 A CN 110896036A CN 201910662160 A CN201910662160 A CN 201910662160A CN 110896036 A CN110896036 A CN 110896036A
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CN
China
Prior art keywords
packaging
layer
plating seed
seed layer
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910662160.5A
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Chinese (zh)
Inventor
尹佳山
周祖源
吴政达
林正忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SJ Semiconductor Jiangyin Corp filed Critical SJ Semiconductor Jiangyin Corp
Priority to CN201910662160.5A priority Critical patent/CN110896036A/en
Publication of CN110896036A publication Critical patent/CN110896036A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemically Coating (AREA)

Abstract

The invention provides a packaging structure and a packaging method, comprising the following steps: providing a supporting substrate, and forming a packaging layer on the upper surface of the supporting substrate; forming a chemical plating seed layer on the upper surface of the packaging layer by adopting chemical plating; forming bonding pads on the upper surface of the electroless plating seed layer, wherein the electroless plating seed layer is exposed between the bonding pads; removing the exposed part of the electroless plating seed layer; and connecting a metal wire above the bonding pad by adopting a routing process. The packaging structure and the packaging method can improve the firmness of the bonding pad and the bonding force between the bonding pad and the packaging layer, thereby preventing the bonding pad from falling off in the subsequent process.

Description

Packaging structure and packaging method
Technical Field
The invention belongs to the field of semiconductor packaging, and particularly relates to a packaging structure and a packaging method.
Background
Wafer Level Chip Scale Packaging (WLCSP), which is a Wafer Level Chip Packaging method, is different from the conventional Chip Packaging method (cutting and then Packaging), and the volume of the original Chip is increased by at least 20% after Packaging). Wafer level chip package often needs encapsulated layer and pad, and in traditional technology, the cohesion between pad and the encapsulated layer is not strong, leads to the pad to appear the obscission, has seriously influenced the yields of product.
Based on the above, the present invention provides a package structure and a package method to solve the problem of pad detachment in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a package structure and a packaging method for solving the problem of pad detachment in the prior art.
To achieve the above and other related objects, the present invention provides a packaging method, comprising the steps of:
providing a supporting substrate, and forming a packaging layer on the upper surface of the supporting substrate;
forming a chemical plating seed layer on the upper surface of the packaging layer by adopting chemical plating;
forming bonding pads on the upper surface of the electroless plating seed layer, wherein the electroless plating seed layer is exposed between the bonding pads;
removing the exposed part of the electroless plating seed layer;
and connecting a metal wire above the bonding pad by adopting a routing process.
Optionally, the method of forming the pad includes: forming a patterned mask layer on the upper surface of the chemical plating seed layer, wherein the mask layer is provided with a first window, and the chemical plating seed layer is exposed through the first window; forming a metal layer in the first window; and removing the mask layer to form the bonding pad.
Optionally, the mask layer includes a photoresist, and the method of forming the patterned photoresist includes a photolithography process.
Optionally, the method of forming the metal layer comprises electroplating.
Optionally, the material of the bonding pad includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the pad has a thickness of between 3 μm and 15 μm.
Optionally, the material of the electroless plating seed layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the electroless plating seed layer has a thickness of between 180nm and 220 nm.
Optionally, the material of the encapsulation layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.
Optionally, the method for forming the encapsulation layer includes one of plastic molding, compression molding, transfer molding, liquid encapsulation, vacuum lamination, and spin coating.
Optionally, the material of the supporting base includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, and the thickness of the supporting base is between 800 μm and 1200 μm.
Optionally, the method of removing the exposed portion of the electroless plating seed layer comprises a chemical etching process.
Optionally, the metal wire includes one of a gold wire and a copper wire.
The present invention also provides a package structure, comprising:
a support substrate;
the packaging layer is formed on the supporting substrate;
the patterned electroless plating seed layer is formed on the surface of the packaging layer;
the bonding pad is formed on the surface of the electroless plating seed layer;
and the metal wire is connected to the bonding pad.
Optionally, the pad has a thickness of between 3 μm and 15 μm.
Optionally, the electroless plating seed layer has a thickness of between 180nm and 220 nm.
Optionally, the thickness of the support substrate is between 800 μm and 1200 μm.
As described above, the present invention provides a package structure and a package method, and the present invention has the following effects:
the packaging structure and the packaging method of the invention adopt chemical plating to form the chemical plating seed layer on the upper surface of the packaging layer, thereby improving the firmness of the bonding pad and the binding force between the bonding pad and the packaging layer, and preventing the bonding pad from falling off in the subsequent working procedures.
Forming a patterned mask layer on the upper surface of the chemical plating seed layer, wherein the mask layer is provided with a first window, the chemical plating seed layer is exposed from the first window, a metal layer is formed in the first window, the mask layer is removed to form a welding disc, the chemical plating seed layer of the exposed part is removed by adopting a chemical etching process, dry etching is not used in the whole forming process of the welding disc, only wet etching is adopted, the production efficiency is improved, and the production cost is reduced.
The chemical plating seed layer is arranged between the bonding pad and the packaging layer, so that the firmness of the bonding pad is improved, and the binding force between the bonding pad and the packaging layer is improved, so that the bonding pad is prevented from falling off in the subsequent working procedures. And the chemical plating seed layer is directly contacted with the packaging layer without carrying other substances, so that the binding force between the chemical plating seed layer and the packaging layer is improved.
Drawings
Fig. 1 shows a schematic structural diagram of step 1) of the packaging method of the present invention.
Fig. 2 shows a schematic structural diagram of step 2) of the packaging method of the present invention.
Fig. 3 shows a schematic structural diagram of step 3) of the packaging method of the present invention.
Fig. 4 shows a schematic structural diagram of step 4) of the packaging method of the present invention.
Fig. 5 shows a schematic structural diagram of step 5) of the packaging method of the present invention.
Fig. 6 shows a schematic structural diagram of step 6) of the packaging method of the present invention.
Fig. 7 shows a schematic structural diagram of step 7) of the packaging method of the present invention.
FIG. 8 is a flow chart of the packaging method of the present invention.
Description of the element reference numerals
101 supporting substrate
102 encapsulation layer
103 electroless plating seed layer
104 mask layer
105 first window
106 bonding pad
107 metal line
S01-S07
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1 to 8, the present embodiment provides a packaging method, including the steps of:
as shown in fig. 1, step 1) S01 is performed to provide a supporting substrate 101, and an encapsulation layer 102 is formed on an upper surface of the supporting substrate 101.
The material of the supporting base 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, and the thickness of the supporting base 101 is between 800 μm and 1200 μm, for example, the thickness of the supporting base 101 may be 900 μm, 1000 μm, and 1100 μm. The material of the package layer 102 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the method for forming the package layer 102 includes one of plastic package process, compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating. The encapsulation layer 102 is formed by processes such as material scattering, heating and melting, mold clamping and cooling.
In this embodiment, the material of the encapsulation layer 102 is selected from epoxy resin, which is a generic name of a polymer having two or more epoxy groups in a molecule. It is a polycondensation product of epichlorohydrin and bisphenol A or a polyol. Due to the chemical activity of epoxy group, it can be opened by many compounds containing active hydrogen, cured and cross-linked to form a network structure, so it is a kind of thermosetting resin.
As shown in fig. 2, step 2) S02 is performed, and an electroless plating seed layer 103 is formed on the upper surface of the encapsulation layer 102 by electroless plating.
The electroless plating seed layer 103 may be made of copper, aluminum, nickel, gold, silver, or titanium, or a combination of two or more thereof. The thickness of the electroless plating seed layer 103 is between 180nm and 220nm, for example, the thickness of the electroless plating seed layer 103 may be 180nm, 200nm, 220 nm.
In this embodiment, the material of the electroless plating seed layer 103 includes copper, the electroless plating temperature is between 25 ℃ and 30 ℃, when the temperature is too low, the copper plating rate is reduced, and when the temperature is too high, side reactions increase, so that the plating solution is unstable. The time of the chemical plating is 30-40 minutes. The content of formaldehyde (37%) in the plating solution is between 6ml/L and 8ml/L, and when the content of formaldehyde is in the range, the change of the content of formaldehyde has little influence on the deposition rate of copper.
Electroless plating, also known as electroless plating or autocatalytic plating, is a plating method in which metal ions in a plating solution are reduced to metal by means of a suitable reducing agent in the absence of an applied current and deposited onto the surface of a part. The electroless plating seed layer 103 is formed on the upper surface of the packaging layer 102 by electroless plating, so that the firmness of the bonding pad 106 is improved, the bonding force between the bonding pad 106 and the packaging layer 102 is improved, and the bonding pad 106 is prevented from falling off in the subsequent process.
As shown in fig. 3, step 3) S03 is performed to form a patterned mask layer 104 on the upper surface of the electroless plating seed layer 103, where the mask layer 104 has a first window 105, and the electroless plating seed layer 103 is exposed through the first window 105.
Illustratively, the mask layer 104 includes a photoresist, and the method of forming the patterned photoresist includes a photolithography process.
In this embodiment, the photolithography process is performed by cleaning and drying the surface of the silicon wafer, priming, spin-coating the photoresist, soft-baking, alignment exposure, post-baking, developing, and hard-baking, thereby forming a patterned photoresist. The photosensitive material used in photolithography is called a photoresist, and is mainly classified into a positive photoresist and a negative photoresist. The unexposed portions of the positive photoresist are developed and the exposed portions of the negative photoresist are developed and retained, wherein the removed portions of the positive photoresist or negative photoresist form the first windows 105. The photoresist needs to be sensitive to not only a given light but also to maintain stable properties during a subsequent metal etching process or the like. Different photoresists typically have different photosensitive properties, some are sensitive to all ultraviolet spectra, some are sensitive only to specific spectra, and some are sensitive to X-rays or to electron beams.
As shown in fig. 4, step 4) S04 is performed to form a metal layer in the first window 105.
The metal layer is formed by one of electroplating and electroless plating, and the material of the pad 106 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium. The thickness of the pad 106 is between 3 μm and 15 μm, for example, the thickness of the pad 106 may be 6.6 μm and 9.6 μm. The metal layer may or may not fill the first window 105.
The electroplating is a process of plating a thin layer of other metals or alloys on the surface of some metals by using the principle of electrolysis, and is a process of attaching a layer of metal film on the surface of a metal or other material workpiece by using the action of electrolysis.
As shown in fig. 5, step 5) S05 is performed to remove the mask layer 104 to form pads 106, and the electroless plating seed layer 103 is exposed between the pads 106.
As shown in fig. 6, step 6) S06 is performed to remove the exposed portion of the electroless plating seed layer 103.
Illustratively, the method of removing the exposed portions of the electroless plating seed layer 103 includes a chemical etching process.
The chemical etching process is to soak the silicon wafer in a certain chemical reagent or a reagent solution, so that the part of the surface of the film which is not masked by the resist is removed by chemical reaction with the reagent.
Forming a patterned mask layer 104 on the upper surface of the electroless plating seed layer 103, wherein the mask layer 104 is provided with a first window 105, the first window 105 exposes the electroless plating seed layer 103, a metal layer is formed in the first window 105, the mask layer 104 is removed to form a bonding pad 106, a chemical etching process is adopted to remove the exposed part of the electroless plating seed layer 103, dry etching is not used in the whole forming process of the bonding pad 106, only wet etching is adopted, the production efficiency is improved, and the production cost is reduced.
As shown in fig. 7, step 7) S07 is performed, and a metal wire 107 is connected above the pad 106 by a wire bonding process.
By way of example, the metal line 107 includes one of a gold line and a copper line.
As shown in fig. 7, the present embodiment further provides a package structure, including: a support substrate 101; an encapsulation layer 102 formed on the support substrate 101; a patterned electroless plating seed layer 103 formed on the surface of the encapsulation layer 102; a bonding pad 106 formed on the surface of the electroless plating seed layer 103; and a metal line 107 connected to the pad 106. The thickness of the pad 106 is, for example, between 3 μm and 15 μm, and the thickness of the pad 106 may be, for example, 6.6 μm and 9.6 μm. By way of example, the electroless plating seed layer 103 has a thickness of 180nm to 220nm, for example, the electroless plating seed layer 103 may have a thickness of 180nm, 200nm, 220 nm. As an example, the thickness of the supporting substrate 101 is between 800 μm and 1200 μm, for example, the thickness of the supporting substrate 101 may be 900 μm, 1000 μm, 1100 μm.
In summary, the present invention provides a package structure and a package method, which have the following effects:
the packaging structure and the packaging method of the invention adopt chemical plating to form the chemical plating seed layer 103 on the upper surface of the packaging layer 102, which can improve the firmness of the bonding pad 106 and the bonding force between the bonding pad 106 and the packaging layer 102, thereby preventing the bonding pad 106 from falling off in the subsequent process. Forming a patterned mask layer 104 on the upper surface of the electroless plating seed layer 103, wherein the mask layer 104 is provided with a first window 105, the first window 105 exposes the electroless plating seed layer 103, a metal layer is formed in the first window 105, the mask layer 104 is removed to form a bonding pad 106, the exposed part of the electroless plating seed layer 103 is removed by adopting a chemical etching process, dry etching is not used in the whole forming process of the bonding pad 106, only wet etching is adopted, the production efficiency is improved, and the production cost is reduced. The electroless plating seed layer 103 is arranged between the bonding pad 106 and the packaging layer 102, so that the firmness of the bonding pad 106 is improved, the bonding force between the bonding pad 106 and the packaging layer 102 is improved, and the bonding pad 106 is prevented from falling off in the subsequent process. In addition, other substances are not entrained in the direct contact between the electroless plating seed layer 103 and the packaging layer 102, and the bonding force between the electroless plating seed layer 103 and the packaging layer 102 is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be accomplished by those skilled in the art without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims (17)

1. A method of packaging, comprising the steps of:
providing a supporting substrate, and forming a packaging layer on the upper surface of the supporting substrate;
forming a chemical plating seed layer on the upper surface of the packaging layer by adopting chemical plating;
forming bonding pads on the upper surface of the electroless plating seed layer, wherein the electroless plating seed layer is exposed between the bonding pads;
removing the exposed part of the electroless plating seed layer;
and connecting a metal wire above the bonding pad by adopting a routing process.
2. The method of packaging of claim 1, wherein: the method for forming the bonding pad comprises the following steps: forming a patterned mask layer on the upper surface of the chemical plating seed layer, wherein the mask layer is provided with a first window, and the chemical plating seed layer is exposed through the first window; forming a metal layer in the first window; and removing the mask layer to form the bonding pad.
3. The method of packaging of claim 2, wherein: the mask layer comprises photoresist, and the method for forming the patterned photoresist comprises a photoetching process.
4. The method of packaging of claim 2, wherein: the method of forming the metal layer includes electroplating.
5. The method of packaging of claim 1, wherein: the bonding pad is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
6. The method of packaging of claim 1, wherein: the thickness of the bonding pad is between 3 and 15 mu m.
7. The method of packaging of claim 1, wherein: the chemical plating seed layer is made of one or more of copper, aluminum, nickel, gold, silver and titanium.
8. The method of packaging of claim 1, wherein: the thickness of the electroless plating seed layer is between 180nm and 220 nm.
9. The method of packaging of claim 1, wherein: the packaging layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass.
10. The method of packaging of claim 1, wherein: the method for forming the packaging layer comprises one of plastic packaging technology, compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating.
11. The method of packaging of claim 1, wherein: the material of the supporting base comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate, and the thickness of the supporting base is between 800 and 1200 mu m.
12. The method of packaging of claim 1, wherein: the method for removing the exposed part of the chemical plating seed layer comprises a chemical etching process.
13. The method of packaging of claim 1, wherein: the metal wire comprises one of a gold wire and a copper wire.
14. A package structure, comprising:
a support substrate;
the packaging layer is formed on the supporting substrate;
the patterned electroless plating seed layer is formed on the surface of the packaging layer;
the bonding pad is formed on the surface of the electroless plating seed layer;
and the metal wire is connected to the bonding pad.
15. The package structure of claim 14, wherein: the thickness of the bonding pad is between 3 and 15 mu m.
16. The package structure of claim 14, wherein: the thickness of the electroless plating seed layer is between 180nm and 220 nm.
17. The package structure of claim 14, wherein: the thickness of the supporting substrate is between 800 and 1200 mu m.
CN201910662160.5A 2019-07-22 2019-07-22 A packaging structure and packaging method Pending CN110896036A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114203666A (en) * 2020-09-18 2022-03-18 盛合晶微半导体(江阴)有限公司 Manufacturing method and packaging structure of a metal wiring layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413769A (en) * 2013-08-27 2013-11-27 南通富士通微电子股份有限公司 Wafer level chip size packaging method
CN103745938A (en) * 2014-02-08 2014-04-23 华进半导体封装先导技术研发中心有限公司 Manufacture method of fan-out wafer level package
CN107705971A (en) * 2017-08-30 2018-02-16 歌尔股份有限公司 A kind of manufacture method of coil, coil, electronic equipment
CN210182334U (en) * 2019-07-22 2020-03-24 中芯长电半导体（江阴）有限公司 Packaging structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413769A (en) * 2013-08-27 2013-11-27 南通富士通微电子股份有限公司 Wafer level chip size packaging method
CN103745938A (en) * 2014-02-08 2014-04-23 华进半导体封装先导技术研发中心有限公司 Manufacture method of fan-out wafer level package
CN107705971A (en) * 2017-08-30 2018-02-16 歌尔股份有限公司 A kind of manufacture method of coil, coil, electronic equipment
CN210182334U (en) * 2019-07-22 2020-03-24 中芯长电半导体（江阴）有限公司 Packaging structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114203666A (en) * 2020-09-18 2022-03-18 盛合晶微半导体(江阴)有限公司 Manufacturing method and packaging structure of a metal wiring layer
CN114203666B (en) * 2020-09-18 2025-03-14 盛合晶微半导体(江阴)有限公司 A method for manufacturing a metal wiring layer and a packaging structure

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