CN110890346B - Integrated circuit memory and method for forming the same - Google Patents
Integrated circuit memory and method for forming the same Download PDFInfo
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- CN110890346B CN110890346B CN201811051297.9A CN201811051297A CN110890346B CN 110890346 B CN110890346 B CN 110890346B CN 201811051297 A CN201811051297 A CN 201811051297A CN 110890346 B CN110890346 B CN 110890346B
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 39
- 238000009413 insulation Methods 0.000 claims description 32
- 239000011810 insulating material Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 229940104869 fluorosilicate Drugs 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 239000012774 insulation material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
本发明提供了一种集成电路存储器及其形成方法，通过在对应同一有源区的两条字线之间的沟槽隔离结构中形成绝缘结构，且所述绝缘结构的材料的介电常数小于所述沟槽隔离结构的材料的介电常数，从而减小了对应同一有源区的两条所述字线之间的寄生电容，提高了集成电路存储器的性能和稳定性。
The present invention provides an integrated circuit memory and a method for forming the same. By forming an insulating structure in a trench isolation structure between two word lines corresponding to the same active area, and the dielectric constant of the material of the insulating structure is smaller than the dielectric constant of the material of the trench isolation structure, the parasitic capacitance between the two word lines corresponding to the same active area is reduced, thereby improving the performance and stability of the integrated circuit memory.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to an integrated circuit memory and a method for forming the same.
Background
In order to reduce the area of the integrated circuit memory for maximum integration, a trench type transistor structure is generally adopted, and two transistors sharing a drain can be manufactured in one active region to further reduce the area and the production cost. However, in this way, the distance between the two transistors is very close, and a large parasitic capacitance is generated between the word lines, which affects the performance and stability of the device.
Disclosure of Invention
An object of the present invention is to provide an integrated circuit memory and a method of forming the same, which can improve the performance and stability of a device by reducing the dielectric constant of a dielectric between two word lines corresponding to the same active region to reduce parasitic capacitance between the two word lines.
In order to achieve the above object, the present invention provides an integrated circuit memory, comprising:
a substrate, a plurality of trench isolation structures formed in the substrate, the trench isolation structures defining a plurality of active regions,
A plurality of word lines arranged in parallel, formed in the substrate, and intersecting the corresponding active regions and extending into the trench isolation structure, each of the active regions intersecting two of the word lines;
and the insulating structures are formed in the trench isolation structures and are positioned between the two word lines corresponding to the same active region, and the dielectric constant of the material of the insulating structures is smaller than that of the material of the trench isolation structures.
Optionally, the plurality of active regions are arranged in an array, and the plurality of active regions in the same column intersect with the same two word lines, so that two adjacent active regions and the two word lines in the same column surround an insulation region in the trench isolation structure, and the insulation structure is formed in the insulation region of the trench isolation structure.
Optionally, the insulating structure includes a layer of insulating material formed in an insulating trench, the insulating material layer having a material with a dielectric constant less than 4.
Optionally, the insulation structure further includes a stress buffer layer, the stress buffer layer covers the side wall and the bottom wall of the insulation trench, and the insulation material layer is formed on the stress buffer layer and fills the insulation trench.
Optionally, the material of the insulating material layer includes one or more of free silicon oxide material, silicon oxycarbide, fluorosilicone glass, carbon doped glass and organic polymer.
Optionally, in the extending direction of the word line, two adjacent insulating structures are separated by one active region.
Optionally, the active area is used for forming two memory cells of the integrated circuit memory, each active area is formed with a drain area and two source areas, the two source areas are respectively located at two sides of the drain area, each memory cell is provided with an access transistor, and the two access transistors share the drain area.
The invention also provides a forming method of the integrated circuit memory, which comprises the following steps:
providing a substrate, wherein a plurality of groove isolation structures are formed in the substrate, and define a plurality of active areas extending along a first direction;
forming a plurality of insulation trenches in the trench isolation structure, wherein the plurality of insulation trenches are arranged along a second direction, and virtual connecting lines corresponding to the plurality of insulation trenches arranged on the same straight line intersect with the active region;
Filling a layer of insulating material in the insulating trench to form an insulating structure, the insulating material layer having a material with a dielectric constant less than that of the trench isolation structure, and
And forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines are intersected with corresponding active areas and extend into the trench isolation structure, each active area is intersected with two word lines, and two word lines corresponding to the same active area are respectively located on two sides of the insulation structure in the trench isolation structure.
Optionally, the step of forming a plurality of the insulating structures includes:
Forming a first mask layer extending along a second direction on the substrate, wherein a first opening corresponding to an insulation region and part of the active region is formed in the first mask layer, and the insulation region is used for forming the insulation structure;
etching the insulating region under the first opening to form a plurality of insulating trenches arranged along the second direction in the trench isolation structure, and
And filling an insulating material layer in the insulating trench to form the insulating structure.
Optionally, the step of filling the insulating material layer in the insulating trench to form the insulating structure includes:
forming stress buffer layer on the side wall and bottom wall of the insulation trench, and
And forming the insulating material layer on the stress buffer layer, wherein the insulating material layer fills the insulating groove, and the stress buffer layer and the insulating material layer jointly form the insulating structure.
Optionally, the step of forming the first mask layer includes:
forming a second mask layer extending along a second direction on the substrate, wherein the second mask layer covers the word line region;
Forming a third mask layer on the substrate, wherein the third mask layer is adjacent to the second mask layer and forms the first mask layer with the second mask layer;
and after forming the insulating structure, forming the word line in the substrate comprises:
Filling a fourth mask layer in the first opening, and removing the second mask layer to form a second opening corresponding to the word line region;
Etching a word line region below the second opening to form a word line trench in the substrate;
Word lines are formed in the word line trenches.
Optionally, the material of the fourth mask layer is the same as the material of the third mask layer.
In the integrated circuit memory and the forming method thereof, the insulating structure is formed in the trench isolation structure between the two word lines corresponding to the active region, and the dielectric constant of the material of the insulating structure is smaller than that of the material of the trench isolation structure, so that parasitic capacitance between the two word lines corresponding to the same active region is reduced, and the performance and stability of the integrated circuit memory are improved.
Drawings
FIG. 1 is a top view of an integrated circuit memory according to an embodiment of the present invention;
FIG. 2 is a partial cross-sectional view of the integrated circuit memory device of FIG. 1 taken along the height direction thereof in accordance with an embodiment of the present invention;
FIG. 3 is a flow chart of a method for forming an integrated circuit memory according to an embodiment of the present invention;
Fig. 4-12 are partial cross-sectional views of semiconductor structures formed using the method for forming an integrated circuit memory according to embodiments of the present invention;
wherein, the reference numerals are as follows:
1-substrate, 11-trench isolation structure, 12-active region, 121-drain region, 122-source region;
2-word line, 21-word line trench;
3-insulating structure, 31-insulating trench, 32-insulating material layer;
41-a second mask layer, 42-a fifth mask layer;
43-third mask layer 44-fourth mask layer;
51-first opening, 52-second opening;
a-a first direction, b-a second direction.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 and 2 are schematic structural diagrams of an integrated circuit memory provided in this embodiment, as shown in fig. 1 and 2, the integrated circuit memory includes a substrate 1, a plurality of trench isolation structures 11 are formed in the substrate 1, the trench isolation structures 11 define a plurality of active regions 12, a plurality of word lines 2 arranged in parallel are formed in the substrate 1, the word lines 2 intersect the corresponding active regions 12 and extend into the trench isolation structures 11, each active region 12 intersects two word lines 2, and a plurality of insulation structures 3 are formed in the trench isolation structures 11, and the dielectric constant of the material of the insulation structures 3 is smaller than that of the material of the trench isolation structures 11.
For ease of description, two of the word lines 2 corresponding to the same active region 12 are defined herein as two adjacent word lines 2, none of the word lines 2 not corresponding to the same active region 12 being adjacent, e.g., having three pairs of adjacent word lines 2 in fig. 1.
Specifically, referring to fig. 1, a plurality of trench isolation structures 11 are formed in the substrate 1, the trench isolation structures 11 separate adjacent active regions 12, so that the active regions form an array distribution of a plurality of rows and a plurality of columns, the trench isolation structures 11 generally include a silicon oxide layer formed in the isolation trench, the periphery of the active regions 12 is surrounded by the trench isolation structures 11, each active region 12 includes two source regions 121 and a drain region 122, the drain region 122 is located between the two source regions 121, a plurality of word lines 2 arranged in parallel are located in the substrate 1, and each active region 12 is crossed by two adjacent word lines 2, wherein two adjacent word lines 2 respectively pass through a portion between the source regions 121 and the drain regions 122 in the active regions 12, so as to separate each source region 121 and each drain region 122, and two access transistors are formed in each active region, and the two access transistors share the drain region 122.
Further, referring to fig. 2, 8 and 9, the insulating structures 3 are located in the trench isolation structures 11 at both sides of each of the active regions 12 and located between two adjacent word lines 2. Specifically, the plurality of active regions 12 are arranged in an array, and the plurality of active regions 12 in the same column intersect the same two word lines 2, so that two adjacent active regions 12 and two word lines 2 in the same column surround an insulating region in the trench isolation structure 11, and the insulating structure 3 is formed in the insulating region of the trench isolation structure 11.
The insulating structure 3 includes an insulating material layer 32 formed in an insulating trench 31, where the material of the insulating material layer 32 is a low-K material with a dielectric constant less than 4, such as one or more of free silicon oxide material, silicon oxycarbide, fluorosilicone glass, carbon doped glass, and organic polymer. It can be appreciated that, since the material of the insulating structure 3 is a low-K material and is located between two adjacent word lines 2, parasitic capacitance between two adjacent word lines 2 can be effectively reduced, thereby improving the performance of the device.
Further, as shown in fig. 2, the insulating structure 3 may be further sunk in the substrate 1 than the word line 2, and in the extending direction (i.e., the second direction b) of the word line 2, two adjacent insulating structures 3 are separated by one active region 12 (i.e., all the insulating structures 3 between two word lines 2 corresponding to the same active region 12 except the drain region 122), so that the area of the insulating structure 3 is larger, and parasitic capacitance between two adjacent word lines 2 can be further reduced.
Optionally, the insulating structure 3 may further include a stress buffer layer (not shown) covering the sidewall and the bottom wall of the insulating trench 31, and the insulating material layer 32 is formed on the stress buffer layer and fills the insulating trench 31 to buffer and match stress between film layers.
As shown in fig. 3, the present embodiment provides a method for forming an integrated circuit memory, including:
S1, forming a plurality of insulation trenches in the trench isolation structure, wherein the insulation trenches are arranged along a second direction, and virtual connecting lines corresponding to the insulation trenches arranged on the same line intersect with the active region;
S2, filling an insulating material layer in the insulating groove to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than that of the material of the groove isolation structure;
And S3, forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines are intersected with corresponding active areas and extend into the trench isolation structure, each active area is intersected with two word lines, and two word lines corresponding to the same active area are respectively located on two sides of the insulation structure in the trench isolation structure.
Specifically, referring to fig. 1, a plurality of trench isolation structures 11 are formed in the substrate 1, the trench isolation structures 11 define a plurality of active regions 12 extending along a first direction a, that is, the periphery of each active region 12 is surrounded by the trench isolation structures 11, so that the plurality of active regions 12 are isolated from each other, a drain region 122 and two source regions 121 are formed in each active region 12, the two source regions 121 are respectively located at two sides of the drain region 122, the active regions are used for forming two memory cells of the integrated circuit memory, each memory cell has one access transistor therein, and the two access transistors share the drain electrode 122.
Next, as shown in fig. 4 to 8, a first mask layer extending in the second direction b is formed on the substrate 1, and the insulation trench 31 is formed using the first mask layer as a mask. Specifically, the step of forming the first mask layer includes, firstly, forming a second mask layer 41 on the substrate 1 as shown in fig. 4, where the second mask layer 41 covers a portion of the substrate 1 corresponding to a word line region, where the word line region is used to form a word line, it may be understood that the second mask layer 41 is strip-shaped and extends along the second direction b, then, as shown in fig. 5, forming a fifth mask layer 42 extending along the second direction b on the substrate 1, where the fifth mask layer 42 covers the substrate 1 between two adjacent word line regions, then, as shown in fig. 6, forming a third mask layer 43 extending along the second direction b on the substrate 1, where the third mask layer 43 abuts the second mask layer 41 and covers the remaining substrate 1, and finally, as shown in fig. 7, etching to remove the fifth mask layer 41 and the third mask layer 43, forming a first mask layer, as shown in fig. 5, and then, forming a fifth mask layer 42, and exposing the first mask layer 51, and forming an insulating layer 122, where the opening is formed in the fifth mask layer 51, and the insulating layer is opened, and the opening is formed.
Next, as shown in fig. 8, the insulating region is etched with the first mask layer as a mask, so as to form an insulating trench 31 in the trench isolation structure 11, where the insulating trench 31 may or may not extend through the entire trench isolation structure 11, and the present invention is not limited thereto. As shown in fig. 9, the insulating trench 31 is filled with a low-K material to form an insulating material layer 32, and the insulating structure 3 is finally formed.
It will be appreciated that, as shown in fig. 1 and 8, since the first opening 51 also corresponds to the drain region 122, when etching the insulating region to form the insulating trench 31, an etchant having a high selectivity to the material of the drain region 122 and the material of the trench isolation structure 11 needs to be selected, so that etching the trench isolation structure 11 generates the insulating trench 31 but has little influence on the drain region 122, so that the insulating trench 31 is formed to be arranged on both sides of the drain region 122.
In a preferred embodiment, before the isolation material layer 32 is formed, a stress buffer layer may be formed on the side wall and the bottom wall of the insulation trench 31, and then the insulation material layer 32 is formed on the stress buffer layer, the insulation material layer 32 fills the insulation trench 31, the stress buffer layer and the insulation material layer 32 together form the insulation structure 3, and the stress buffer layer may have functions of stress matching and buffering, so that stability between the film layers is better.
Further, as shown in fig. 10, in order to form the word line, the first opening 51 may be filled with a fourth mask layer 44 extending in the second direction b. The second mask layer 41 is then directly removed, and a second opening 52 is formed, where the second opening 52 corresponds to the word line region.
Finally, as shown in fig. 11-12, the third mask layer 43 and the fourth mask layer 44 are used as masks to etch the word line region to form a word line trench 21, and then a word line 2 is formed in the word line trench 21, where the word line 2 includes a gate dielectric layer and a gate conductive layer, and the word line trench 21 is formed in the substrate 1 and passes through a portion between the drain region 122 and the source region 121, the gate dielectric layer covers the sidewall and the bottom wall of the word line trench 21, and the gate conductive layer is formed on the gate dielectric layer and fills the word line trench 21. Finally, the third mask layer 43 and the fourth mask layer 44 are removed to form the semiconductor structure shown in fig. 2.
Further, the materials of the third mask layer 43 and the fourth mask layer 44 may be the same, so as to achieve the effect of removing the second mask layer 41 and retaining the third mask layer 43 and the fourth mask layer 44.
It can be understood that in this embodiment, since the first mask layer is formed by the second mask layer 41 and the third mask layer 43, when the word line 2 is formed after the insulating structure 3 is formed, the word line 2 can be formed after the second mask layer 41 is directly stripped, and a new mask layer is not required to be formed, so that the process is simplified, and it is also possible to understand that when the insulating structure 3 is formed in this embodiment, a new photomask is not required to be redesigned in the original process, and the performance of the device can be greatly improved on the basis of simpler process.
In summary, in the integrated circuit memory and the forming method thereof provided in the embodiments of the present invention, an insulating structure is formed in a trench isolation structure between two word lines corresponding to the active region, and a dielectric constant of a material of the insulating structure is smaller than that of a material of the trench isolation structure, so that parasitic capacitance between two word lines corresponding to the same active region is reduced, and performance and stability of the integrated circuit memory are improved.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (12)
1. An integrated circuit memory, the integrated circuit memory comprising:
a substrate, a plurality of trench isolation structures formed in the substrate, the trench isolation structures defining a plurality of active regions,
A plurality of word lines arranged in parallel, formed in the substrate, and intersecting the corresponding active regions and extending into the trench isolation structure, each of the active regions intersecting two of the word lines;
and the insulating structures are formed in the trench isolation structures and are positioned between the two word lines corresponding to the same active region, and the dielectric constant of the material of the insulating structures is smaller than that of the material of the trench isolation structures.
2. The integrated circuit memory of claim 1, wherein a plurality of said active regions are arranged in an array and wherein a plurality of said active regions in a same column intersect two same word lines such that adjacent two of said active regions and said two word lines in a same column surround an insulating region in said trench isolation structure, said insulating structure being formed in said insulating region of said trench isolation structure.
3. The integrated circuit memory of claim 2, wherein the insulating structure comprises a layer of insulating material formed in an insulating trench, the insulating material layer having a material dielectric constant less than 4.
4. The integrated circuit memory of claim 3 wherein the insulating structure further comprises a stress buffer layer covering sidewalls and a bottom wall of the insulating trench, the layer of insulating material being formed on the stress buffer layer and filling the insulating trench.
5. The integrated circuit memory of claim 3 wherein the material of the layer of insulating material comprises one or more of free silicon oxide material, silicon oxycarbide, fluorosilicate glass, carbon doped glass, and organic polymers.
6. The integrated circuit memory of claim 1, wherein adjacent two of said insulating structures are separated by one of said active regions in the direction of extension of said word line.
7. The integrated circuit memory of claim 5 wherein said active region is used to form two memory cells of said integrated circuit memory, each of said active regions having a drain region and two source regions formed therein, said two source regions being located on opposite sides of said drain region, respectively, each of said memory cells having an access transistor therein, said drain region being shared by said two access transistors.
8. A method of forming an integrated circuit memory, comprising:
providing a substrate, wherein a plurality of groove isolation structures are formed in the substrate, and define a plurality of active areas extending along a first direction;
forming a plurality of insulation trenches in the trench isolation structure, wherein the plurality of insulation trenches are arranged along a second direction, and virtual connecting lines corresponding to the plurality of insulation trenches arranged on the same straight line intersect with the active region;
Filling a layer of insulating material in the insulating trench to form an insulating structure, the insulating material layer having a material with a dielectric constant less than that of the trench isolation structure, and
And forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines are intersected with corresponding active areas and extend into the trench isolation structure, each active area is intersected with two word lines, and two word lines corresponding to the same active area are respectively located on two sides of the insulation structure in the trench isolation structure.
9. The method of forming an integrated circuit memory of claim 8, wherein the step of forming a plurality of said insulating structures comprises:
Forming a first mask layer extending along a second direction on the substrate, wherein a first opening corresponding to an insulation region and part of the active region is formed in the first mask layer, and the insulation region is used for forming the insulation structure;
etching the insulating region under the first opening to form a plurality of insulating trenches arranged along the second direction in the trench isolation structure, and
And filling an insulating material layer in the insulating trench to form the insulating structure.
10. The method of forming an integrated circuit memory of claim 9, wherein filling the insulating material layer in the insulating trench to form the insulating structure comprises:
forming stress buffer layer on the side wall and bottom wall of the insulation trench, and
And forming the insulating material layer on the stress buffer layer, wherein the insulating material layer fills the insulating groove, and the stress buffer layer and the insulating material layer jointly form the insulating structure.
11. The method of forming an integrated circuit memory of claim 9, wherein the step of forming the first mask layer comprises:
forming a second mask layer extending along a second direction on the substrate, wherein the second mask layer covers the word line region;
Forming a third mask layer on the substrate, wherein the third mask layer is adjacent to the second mask layer and forms the first mask layer with the second mask layer;
and after forming the insulating structure, forming the word line in the substrate comprises:
Filling a fourth mask layer in the first opening, and removing the second mask layer to form a second opening corresponding to the word line region;
Etching a word line region below the second opening to form a word line trench in the substrate;
Word lines are formed in the word line trenches.
12. The method of claim 11, wherein the material of the fourth mask layer is the same as the material of the third mask layer.
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