CN110881009B - Method, device, communication equipment and storage medium for receiving test message - Google Patents
Method, device, communication equipment and storage medium for receiving test message Download PDFInfo
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- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L43/00—Arrangements for monitoring or testing data switching networks
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- H—ELECTRICITY
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- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The application discloses a method and a device for receiving a test message, communication equipment and a storage medium. The method is applied to the device to be tested, the device to be tested comprises a multi-core processor, a plurality of network interfaces and a hardware logic interface, the multi-core processor comprises a main core and a forwarding core, and virtual cache queues which correspond to the network interfaces in the network interfaces one to one are preset in the device to be tested, and the method comprises the following steps: the forwarding core acquires a test message from the hardware logic interface; the forwarding core identifies a source interface of the test message and enqueues the test message to a virtual cache queue corresponding to the source interface, wherein the source interface is an interface in a plurality of network interfaces; and the main core receives the test message from the virtual cache queue corresponding to the source interface. By establishing the virtual cache queues corresponding to the plurality of network interfaces one to one in advance, the main core receives the test message from the virtual cache queues, so that the problem of false alarm of the test can be avoided.
Description
Technical Field
The present application belongs to the field of communication technologies, and in particular, to a method and an apparatus for receiving a test packet, a communication device, and a storage medium.
Background
Communication equipment such as a router and a switch needs to be tested by using a tool test program before leaving a factory so as to detect whether equipment from a production line has hardware faults or not, and delivery can be performed only if the tool test is passed. An important test item in the tool test is to test a network interface receiving and sending packet, the test principle is to configure the network interface into a special loopback mode through driving, and the interface can normally work through a loopback line. In this mode, the message sent from the device will return to the device through the loopback loop, and the loopback process of the message passes through a complete hardware path. If any place on the hardware has a problem, the loopback of the message fails, so that the reliability of the hardware can be checked through loopback test.
It can be seen from the above test flow that after a tool test program sends a message to a certain interface, the tool test program needs to receive the message back to the interface, and this action is easily implemented in a device using a pcie (peripheral Component Interconnect express) network chip. Because such devices have hardware support, each interface is independent of itself, and software can receive messages directly onto the interface. In the device using the cavum chip, the hardware design of the device prevents software from directly receiving messages to the network interface, the cavum chip is provided with a hardware acceleration component, the component only presents a logic interface for receiving the messages to the software, the messages from any network interface are gathered to the logic interface, and the messages are uniformly delivered to the software from the logic interface. The software can only identify which network interface the message really comes from by analyzing the content additionally inserted by the hardware acceleration component in the message after the message is taken.
Since the tool test is a multi-thread test, a plurality of interfaces can be tested simultaneously, which causes uncertainty in the source of the message when the hardware platform receives the test message. For example: if during testing of the two interfaces a and B, the logic of the A, B interface test thread sends a message to the test interface, then receives the message and detects the message, but the message can only be received on the common logic interface in the cavum report. In addition, because the system can perform process scheduling, for example, when the test thread of the interface a sends a message and is scheduled by the system, the system schedules the test thread of the interface B to run and sends a test message to the interface B, but the scheduling of the system is uncertain, and it may cause the test thread of the interface B to continue running, so the test thread of the interface B receives the message from the logic interface, and it receives the test message sent by the test thread of the interface a. At this point, the question is about how to process the message? If the test message is considered to be the test message of the user, the content of the self-detection message can be wrongly reported, if the test message is lost, the thread A can be lost, the error reporting is not caused by hardware, the error reporting under the condition is actually a wrong report, and only the problem of hardware can be more complicated to solve.
Disclosure of Invention
In view of the above, an object of the present application is to provide a method, an apparatus, a communication device and a storage medium for receiving a test packet, so as to effectively improve the above problem.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for receiving a test packet, which is applied to a device to be tested, where the device to be tested includes a multi-core processor, multiple network interfaces, and a hardware logic interface, where the multi-core processor includes a main core and a forwarding core, and a virtual cache queue corresponding to each network interface in the multiple network interfaces in a one-to-one manner is preset in the device to be tested, and the method includes: the forwarding core acquires a test message from the hardware logic interface; the forwarding core identifies a source interface of the test message and enqueues the test message into a virtual cache queue corresponding to the source interface, wherein the source interface is an interface in the plurality of network interfaces; and the main core receives the test message from the virtual cache queue corresponding to the source interface. In the embodiment of the application, the limitation of hardware is broken through a mode of establishing a virtual cache queue corresponding to each network interface in a plurality of network interfaces in advance, so that during testing, a forwarding core acquires a test message from a hardware logic interface, identifies a source interface of the test message, and enqueues the test message into the virtual cache queue corresponding to the source interface, so that a main core does not receive the test message directly from the hardware logic interface but receives the test message from the virtual cache queue corresponding to the source interface, the purpose of receiving the message by a specified interface is indirectly achieved, and the problem of false testing caused by the fact that tooling test software cannot directly receive the message of the specified network interface due to special attributes of hardware is solved.
With reference to an optional implementation manner of the first aspect, before the forwarding core obtains the test packet from the hardware logic interface, the method further includes: the main core sends a test message to at least one network interface in the plurality of network interfaces, and the test message returns to the at least one network interface after looping back according to a preset looping route, so that the at least one network interface sends the looped test message to the hardware logic interface. In the embodiment of the application, during tool testing, a main core sends a test message to at least one network interface in a plurality of network interfaces, a forwarding core different from the main core obtains the test message from a hardware logic interface, identifies a source interface of the test message, and enqueues the test message into a virtual cache queue corresponding to the source interface, and because different cores are synchronous during operation, the forwarding core can timely store a looped test message sent to the hardware logic interface by at least one network interface into the virtual cache queue, so that when the main core receives the test message, the test message must be received by the corresponding test interface. Therefore, the requirement of receiving the message at the specified interface on the hardware platform such as the cavum and the like is realized in a software mode.
With reference to still another optional implementation manner of the first aspect, after the master core receives the test packet from the virtual cache queue corresponding to the source interface, the method further includes: and the main core determines whether the content of the test message is complete or wrong. In the embodiment of the application, after the main core receives the test message from the virtual cache queue corresponding to the source interface, whether the content of the test message is complete or wrong is determined through analysis, so that the reliability of hardware is checked.
With reference to still another optional implementation manner of the first aspect, the acquiring, by the forwarding core, the test packet from the hardware logic interface includes: the forwarding core periodically polls the hardware logic interface to determine whether the test message exists in the hardware logic interface; and when the test message exists in the hardware logic interface, the forwarding core acquires the test message from the hardware logic interface. In the embodiment of the application, whether the test message exists in the hardware logic interface is determined by forwarding the core periodic polling hardware logic interface, so that the message is stored in the corresponding virtual cache queue in time, and the test message is prevented from being accumulated in the hardware logic interface, so that the main core cannot receive the message from the virtual cache queue to influence the test progress.
In a second aspect, an embodiment of the present application further provides a communication device, including: the communication equipment comprises a multi-core processor, a plurality of network interfaces and hardware logic interfaces, wherein the processor comprises a main core and a forwarding core, and virtual cache queues which are in one-to-one correspondence with each of the plurality of network interfaces are preset in the communication equipment; the forwarding core is used for acquiring a test message from the hardware logic interface; the forwarding core is further configured to identify a source interface of the test packet, and enqueue the test packet in a virtual cache queue corresponding to the source interface, where the source interface is an interface of the plurality of network interfaces; and the main core is used for receiving the test message from the virtual cache queue corresponding to the source interface.
With reference to the second aspect, in an optional implementation manner, the primary core is further configured to send a test packet to at least one of the multiple network interfaces, where the test packet loops back to the at least one network interface according to a preset loop-back route, so that the at least one network interface sends the looped test packet to the hardware logic interface.
With reference to the second aspect, in yet another optional implementation manner, the primary core is further configured to determine whether the content of the test packet is complete or wrong.
In combination with yet another optional implementation manner of the second aspect, the forwarding core is further configured to periodically poll the hardware logic interface to determine whether the test packet exists in the hardware logic interface; and when the test message exists in the hardware logic interface, the forwarding core is further configured to obtain the test message from the hardware logic interface.
In a third aspect, an embodiment of the present application further provides a device for receiving a test packet, where the device is applied to a multi-core processor in a device to be tested, the device to be tested further includes a plurality of network interfaces and a hardware logic interface, and a virtual cache queue corresponding to each network interface in the plurality of network interfaces one to one is preset in the device to be tested; the device comprises: the device comprises an acquisition module, an identification module and a receiving module; the acquisition module is used for acquiring the test message from the hardware logic interface; the identification module is used for identifying a source interface of the test message and enqueuing the test message into a virtual cache queue corresponding to the source interface, wherein the source interface is an interface in the plurality of network interfaces; and the receiving module is used for receiving the test message from the virtual cache queue corresponding to the source interface.
With reference to an optional implementation manner of the third aspect, the apparatus further includes a sending module, configured to send a test packet to at least one of the multiple network interfaces, where the test packet loops back to the at least one network interface according to a preset loop-back route, so that the at least one network interface sends the looped test packet to the hardware logic interface.
With reference to still another optional implementation manner of the third aspect, the apparatus further includes a determining module, configured to determine whether content of the test packet is complete or wrong.
With reference to still another optional implementation manner of the third aspect, the obtaining module is further configured to periodically poll the hardware logic interface to determine whether the test packet exists in the hardware logic interface; and the test message acquisition module is also used for acquiring the test message from the hardware logic interface when the test message exists in the hardware logic interface.
In a fourth aspect, this application further provides a storage medium having a computer program stored thereon, where the computer program is executed by a processor to perform the method of the first aspect and/or the method provided in connection with any one of the optional implementations of the first aspect.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
Fig. 1 shows an architecture diagram of a communication device provided in an embodiment of the present application.
Fig. 2 shows a flowchart of a method for receiving a test packet according to an embodiment of the present application.
Fig. 3 shows a flowchart of step S101 in fig. 2 according to an embodiment of the present application.
Fig. 4 shows a module schematic diagram of an apparatus for receiving a test packet according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.
First embodiment
As shown in fig. 1, fig. 1 is a schematic diagram illustrating an architecture of a communication device according to an embodiment of the present invention. The communication device includes: a multi-core processor, a plurality of network interfaces, and a hardware logic interface. The processor includes a primary core and a forwarding core. The communication device may be a router, a switch, a gateway, or other communication devices. The communication device can also be regarded as a device to be tested when performing self-test, so that the device to be tested in the application is the communication device.
Because the communication equipment needs to be tested by using a tool test program before leaving the factory so as to detect whether the equipment coming from a production line has hardware faults or not, the equipment can be delivered only if the tool test is passed. An important test item in the tool test is to test a network interface receiving and sending packet, the test principle is to configure the network interface into a special loopback mode through driving, and the interface can normally work through a loopback line. In this mode, the message sent from the device will return to the device through the loopback loop, and the loopback process of the message passes through a complete hardware path. If any place on the hardware has a problem, the loopback of the message fails, so that the reliability of the hardware can be checked through loopback test.
It can be seen from the above test flow that after a tool test program sends a message to a certain interface, the message needs to be received back by the interface, the action is in a device using a cavum chip, the hardware design of the device makes software unable to directly receive the message from a network interface, the cavum chip has a hardware acceleration component, the component only presents a logic interface for receiving the message to the software, the message from any network interface is collected to the logic interface, and the message is uniformly delivered to the software from the logic interface. The software can only identify which network interface the message really comes from by analyzing the content additionally inserted by the hardware acceleration component in the message after the message is taken.
Since the tool test is a multi-thread test, a plurality of interfaces can be tested simultaneously, which causes uncertainty in the source of the message when the hardware platform receives the test message. For example: if during testing of the two interfaces a and B, the logic of the A, B interface test thread sends a message to the test interface, then receives the message and detects the message, but the message can only be received on the common logic interface in the cavum report. In addition, because the system can perform process scheduling, for example, when the test thread of the interface a sends a message and is scheduled by the system, the system schedules the test thread of the interface B to run and sends a test message to the interface B, but the scheduling of the system is uncertain, and it may cause the test thread of the interface B to continue running, so the test thread of the interface B receives the message from the logic interface, and it receives the test message sent by the test thread of the interface a. At this point, the question is about how to process the message? If the test message is considered to be the test message of the user, the content of the self-detection message can be wrongly reported, if the test message is lost, the thread A can be lost, the error reporting is not caused by hardware, the error reporting under the condition is actually a wrong report, and only the problem of hardware can be more complicated to solve.
In order to solve the above problem, in the embodiment of the present application, the limitation of hardware is broken through a manner of establishing a virtual cache queue corresponding to each network interface in a plurality of network interfaces in advance, so that during testing, a forwarding core acquires a test packet from a hardware logic interface, identifies a source interface of the test packet, and enqueues the test packet in the virtual cache queue corresponding to the source interface, so that a main core does not receive the test packet directly from the hardware logic interface, but receives the test packet from the virtual cache queue corresponding to the source interface, thereby indirectly achieving a purpose of receiving the packet by a specified interface, and solving a problem that tool test software cannot directly receive the packet of the specified network interface due to special attributes of hardware.
In order to facilitate understanding of the above process, or taking the above test example as an example, the a interface test thread is scheduled to go after sending the test message, and at this time, the system runs the B interface test thread and also sends a test message to the B interface. Because the forwarding core is another core different from the main core, its receiving action is performed synchronously when the main core runs, it will respectively receive and transmit A, B test messages that are sent out by two threads and looped back by a circuit, find out that the test messages respectively originate from A, B two network interfaces through message analysis, and then enqueue the test messages respectively into virtual cache queues corresponding to A, B two network interfaces. And then, no matter whether the A testing thread is operated first or the B testing thread is operated first, the main core only receives the testing message from the virtual cache queue corresponding to the testing interface. At this time, the received test message is sent by the forwarding core, and it must be the test message received by the corresponding test interface. Therefore, the requirement of receiving the message to the specified interface on hardware platforms such as a cavum and the like is realized in a software mode. The tooling test requirement is supported in a mode that software makes up for hardware limitation, and the difference of different hardware platforms is shielded from the bottom layer, so that the tooling test program does not need to be modified. The software platform is promoted, and the project investment cost is saved.
The tool test program runs on the main core, and the sending and receiving of the test message on the old equipment are completed on the main core. The test program of the main core sends the message out from the network interface, and then the message is directly received back to the corresponding network interface for analysis. The method is not communicated on a hardware platform using the cavum, so that the receiving and sending model is modified, the tool test program runs on the main core, and the sending message is also directly sent by the main core, but the main core does not directly appoint the network interface to receive but receives the message in the virtual cache queue corresponding to the appointed network interface when receiving the message.
It should be noted that the source interface is an interface in a plurality of network interfaces. In addition, when the tool test program is used to test the network interface transceiving packet of the communication device, the main core is further configured to send a test packet to at least one of the plurality of network interfaces, and the test packet is looped back to the at least one network interface according to a preset loopback route, so that the at least one network interface is configured to send the looped test packet to the hardware logic interface. That is to say, after the main core sends the test packet to at least one of the plurality of network interfaces, the test packet loops back according to a preset loop-back route and is finally gathered into the hardware logic interface, so that the forwarding core obtains the test packet from the hardware logic interface.
After receiving the test message from the virtual cache queue corresponding to the source interface, the main core is further configured to determine whether the content of the test message is complete or wrong, that is, determine whether the content of the test message is complete or wrong through analysis, so as to check the reliability of the hardware.
When the forwarding core acquires the test message from the hardware logic interface, periodically polling the hardware logic interface to determine whether the test message exists in the hardware logic interface; when the test message exists in the hardware logic interface, the forwarding core acquires the test message from the hardware logic interface so as to store the message to the corresponding virtual cache queue in time, and the test message is prevented from being accumulated in the hardware logic interface, so that the main core cannot receive the message from the virtual cache queue to influence the test progress.
The multi-core processor may be an integrated circuit chip having signal processing capability. The multi-core Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Second embodiment
Referring to fig. 2, steps included in a method for receiving a test packet applied to the communication device according to an embodiment of the present invention will be described with reference to fig. 2.
Step S101: and the forwarding core acquires the test message from the hardware logic interface.
When the communication equipment is tested, the transmitting and receiving model is modified, and the forwarding core acquires the test message from the hardware logic interface, so that the main core does not receive the message at the specified network interface any more but receives the message at the virtual cache queue corresponding to the specified network interface when receiving the message.
Alternatively, the process may be described in conjunction with the steps shown in fig. 3:
step S201: and the forwarding core periodically polls the hardware logic interface to determine whether the test message exists in the hardware logic interface.
Step S202: and when the test message exists in the hardware logic interface, the forwarding core acquires the test message from the hardware logic interface.
When a test message exists in the hardware logic interface, the forwarding core can acquire the message from the hardware logic interface in time so as to store the message to the corresponding virtual cache queue in time, and the test message is prevented from being accumulated in the hardware logic interface, so that the main core cannot receive the message from the virtual cache queue to influence the test progress.
Before the forwarding core obtains the test packet from the hardware logic interface, the method further includes: the main core sends a test message to at least one network interface in the plurality of network interfaces, and the test message returns to the at least one network interface after looping back according to a preset looping route, so that the at least one network interface sends the looped test message to the hardware logic interface. That is to say, after the main core sends the test packet to at least one of the plurality of network interfaces, the test packet loops back according to a preset loop-back route and is finally gathered into the hardware logic interface, so that the forwarding core obtains the test packet from the hardware logic interface.
Step S102: and the forwarding core identifies a source interface of the test message and enqueues the test message to a virtual cache queue corresponding to the source interface.
After the forwarding core obtains the test message from the hardware logic interface, the source interface of the test message is identified, that is, the interface from which the test message comes from among the plurality of network interfaces is identified, and after the source interface is identified, the test message is enqueued in the virtual cache queue corresponding to the source interface, so that the main core receives the test message from the virtual cache queue corresponding to the source interface. Wherein the source interface is an interface of the plurality of network interfaces.
Step S103: and the main core receives the test message from the virtual cache queue corresponding to the source interface.
In the embodiment of the application, the main core does not receive the test message directly from the hardware logic interface, but receives the test message from the virtual cache queue corresponding to the source interface, so that the purpose of receiving the message by the specified interface is indirectly achieved, and the problem that the tool test software cannot directly receive the message of the specified network interface due to the special attribute of the hardware is solved.
Optionally, after the primary core receives the test packet from the virtual cache queue corresponding to the source interface, the method further includes: and the main core determines whether the content of the test message is complete or wrong. After the main core receives the test message from the virtual cache queue corresponding to the source interface, whether the content of the test message is complete or wrong is determined through analysis, so that the reliability of the hardware is checked.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
Third embodiment
Referring to fig. 4, an embodiment of the present application further provides an apparatus 100 for receiving a test packet applied to the above-mentioned communication device, where the apparatus 100 includes: an acquisition module 110, an identification module 120, and a receiving module 130.
The obtaining module 110 is configured to obtain the test packet from the hardware logic interface. The obtaining module 110 is further configured to periodically poll the hardware logic interface to determine whether the test packet exists in the hardware logic interface; and the test message acquisition module is also used for acquiring the test message from the hardware logic interface when the test message exists in the hardware logic interface.
An identifying module 120, configured to identify a source interface of the test packet, and enqueue the test packet in a virtual cache queue corresponding to the source interface, where the source interface is an interface of the multiple network interfaces.
A receiving module 130, configured to receive the test packet from the virtual buffer queue corresponding to the source interface.
Wherein, the apparatus 100 further comprises: a sending module, configured to send a test packet to at least one of the multiple network interfaces, where the test packet loops back to the at least one network interface according to a preset loop-back route, so that the at least one network interface sends the looped test packet to the hardware logic interface.
Optionally, the apparatus 100 may further include: and the determining module is used for determining whether the content of the test message is complete or wrong.
The implementation principle and the generated technical effect of the apparatus 100 for receiving a test packet provided in the embodiment of the present invention are the same as those of the foregoing method embodiment, and for brief description, no mention is made in the apparatus embodiment, and reference may be made to the corresponding contents in the foregoing method embodiment.
Fourth embodiment
The present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the method described in the first embodiment. For specific implementation, reference may be made to the method embodiment, which is not described herein again.
Specifically, the storage medium can be a general-purpose storage medium, such as a mobile disk, a hard disk, and the like, when a program code on the storage medium is executed, the method for receiving a test packet shown in the above embodiment can be executed, the method breaks the limitation of hardware by establishing a virtual cache queue corresponding to each network interface in a plurality of network interfaces in advance, so that during testing, a forwarding core obtains the test packet from a hardware logic interface, identifies a source interface of the test packet, and enqueues the test packet into the virtual cache queue corresponding to the source interface, so that a main core does not directly receive the test packet from the hardware logic interface but receives the test packet from the virtual cache queue corresponding to the source interface, thereby indirectly achieving the purpose of receiving the packet by a specified interface, and solving the problem of special attributes of hardware, the problem that the tool test software cannot directly receive the message of the specified network interface is caused. .
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for receiving a test message is applied to a device to be tested, the device to be tested comprises a multi-core processor, a plurality of network interfaces and a hardware logic interface, the multi-core processor comprises a main core and a forwarding core, a virtual cache queue corresponding to each network interface in the plurality of network interfaces in a one-to-one mode is preset in the device to be tested, each network interface is connected with the hardware logic interface, the hardware logic interface is connected with the forwarding core, and the forwarding core is connected with the main core through each virtual cache queue, the method comprises the following steps:
the forwarding core acquires a test message from the hardware logic interface;
the forwarding core identifies a source interface of the test message and enqueues the test message into a virtual cache queue corresponding to the source interface, wherein the source interface is an interface in the plurality of network interfaces;
and the main core receives the test message from the virtual cache queue corresponding to the source interface.
2. The method of claim 1, wherein prior to the forwarding core obtaining the test packet from the hardware logical interface, the method further comprises:
the main core sends a test message to at least one network interface in the plurality of network interfaces, and the test message returns to the at least one network interface after looping back according to a preset looping route, so that the at least one network interface sends the looped test message to the hardware logic interface.
3. The method of claim 1, wherein after the primary core receives the test packet from the virtual cache queue corresponding to the source interface, the method further comprises:
and the main core determines whether the content of the test message is complete or wrong.
4. The method according to any of claims 1-3, wherein the forwarding core obtaining the test packet from the hardware logic interface comprises:
the forwarding core periodically polls the hardware logic interface to determine whether the test message exists in the hardware logic interface;
and when the test message exists in the hardware logic interface, the forwarding core acquires the test message from the hardware logic interface.
5. A communication device, comprising: the communication equipment is internally provided with virtual cache queues in one-to-one correspondence with each network interface in the network interfaces in advance, each network interface is connected with the hardware logic interface, the hardware logic interface is connected with the forwarding core, and the forwarding core is connected with the main core through each virtual cache queue;
the forwarding core is used for acquiring a test message from the hardware logic interface;
the forwarding core is further configured to identify a source interface of the test packet, and enqueue the test packet in a virtual cache queue corresponding to the source interface, where the source interface is an interface of the plurality of network interfaces;
and the main core is used for receiving the test message from the virtual cache queue corresponding to the source interface.
6. The communication device of claim 5, wherein:
the main core is further configured to send a test packet to at least one of the plurality of network interfaces, where the test packet returns to the at least one network interface after looping back according to a preset loopback route;
and the at least one network interface is used for sending the looped test message to the hardware logic interface.
7. The communication device of claim 5, wherein:
the main core is further configured to determine whether the content of the test packet is complete or wrong.
8. The communication device according to any of claims 5-7, wherein:
the forwarding core is further configured to periodically poll the hardware logic interface to determine whether the test packet exists in the hardware logic interface;
and when the test message exists in the hardware logic interface, the forwarding core is further configured to obtain the test message from the hardware logic interface.
9. A device for receiving a test message is characterized in that the device is applied to a multi-core processor in a device to be tested, the device to be tested further comprises a plurality of network interfaces and a hardware logic interface, a virtual cache queue corresponding to each network interface in the plurality of network interfaces in a one-to-one mode is preset in the device to be tested, each network interface is connected with the hardware logic interface, the hardware logic interface is connected with a forwarding core, and the forwarding core is connected with a main core through each virtual cache queue; the device comprises:
the acquisition module is used for acquiring the test message from the hardware logic interface;
the identification module is used for identifying a source interface of the test message and enqueuing the test message into a virtual cache queue corresponding to the source interface, wherein the source interface is an interface in the plurality of network interfaces;
and the receiving module is used for receiving the test message from the virtual cache queue corresponding to the source interface.
10. A storage medium having stored thereon a computer program which, when executed by a processor, performs the method according to any one of claims 1-4.
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| CN112202636B (en) * | 2020-09-29 | 2022-06-17 | 中国银行股份有限公司 | Communication test method and system |
| CN113518074B (en) * | 2021-05-11 | 2023-04-18 | 北京物芯科技有限责任公司 | Data message forwarding method, device, equipment and storage medium |
| CN113852610B (en) * | 2021-09-06 | 2024-03-05 | 招银云创信息技术有限公司 | Message processing method, device, computer equipment and storage medium |
| CN114205274B (en) * | 2021-11-02 | 2024-06-11 | 北京百度网讯科技有限公司 | Network equipment testing method and device |
| CN114363274A (en) * | 2021-12-24 | 2022-04-15 | 裕太微电子股份有限公司 | Packet receiving and transmitting system and method |
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