CN110868209B - A High Phase Accuracy Voltage-Controlled Delay Line Structure and Its Realization Method for Multi-Phase Delay Phase-Locked Loop - Google Patents

Abstract

The invention discloses a high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop and an implementation method thereof, wherein the high-phase precision voltage-controlled delay line structure comprises an n-level phase output circuit; the single-ended-differential circuit of the phase output circuit of the first stage is used for accessing the reference clock REF, and the single-ended-differential circuits of the phase output circuits of other stages are connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage; the input of the delay unit of each stage of phase output circuit is connected with the output of the single-end-differential circuit of the stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected with the input of the differential-single-end circuit of the stage of phase output circuit. The invention can reduce the matching error from the circuit level and save the chip area and the power consumption.

Description

A High Phase Accuracy Voltage-Controlled Delay Line Structure and Its Implementation Method for Multi-Phase Delay Phase-Locked Loop

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop and a realization method thereof.

Background technique

With the advancement of IC design technology and the reduction of process size, the scale of the system on chip is getting larger and larger, and the operating frequency is getting higher and higher, and the on-chip clock has become the mainstream choice.

Delay Locked Loop (DLL) is an important module of Time-to-Digital Converter (TDC). To digitize time intervals recorded in a TDC, multiple high-phase-accurate clocks are usually required. Compared with digital DLLs, analog DLLs are commonly used in TDCs due to their higher accuracy and lower jitter at lower power consumption. However, for the traditional multi-phase DLL, the voltage-controlled delay line (Voltage-Controlled DelayLine, VCDL) uses the delay unit to output the multi-phase clock in a cascaded manner. The traditional structure is shown in Figure 1. Any two-stage phase output circuit of its There is a mismatch between them; in particular, the first and last stages are completely different from the other intermediate stages, making the phase error between any two output phases relatively large.

In summary, there is an urgent need for a high-phase precision voltage-controlled delay line structure for multi-phase delay phase-locked loops.

Contents of the invention

The object of the present invention is to provide a high-phase-accuracy voltage-controlled delay line structure for multi-phase delay phase-locked loops and its implementation method, so as to solve one or more of the above-mentioned existing technical problems. Aiming at the phase error caused by inter-stage mismatch, the present invention proposes a high-phase-accuracy VCDL structure with better matching performance, which matches the same modules for the phase output circuits of all levels and adopts an end-to-end inter-stage connection mode to achieve Outputting multi-phase clocks, on the one hand, can reduce matching errors from the circuit level, and on the other hand, can save chip area and power consumption because of the simplicity of the circuit structure.

To achieve the above object, the present invention adopts the following technical solutions:

A high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop of the present invention, including an n-stage phase output circuit;

Each stage phase output circuit includes:

Single-ended-differential circuit for outputting differential signals;

a delay unit, configured to delay the differential signal output by the single-ended-differential circuit;

Differential-single-ended circuit, for converting the differential output signal of the delay unit into a single-ended signal, as the output clock signal of the phase output circuits at all levels;

Among them, the single-ended-differential circuit of the phase output circuit of the first stage is used to access the reference clock REF, and the single-ended-differential circuit of the phase output circuit of other stages is connected to the differential-single-ended circuit of the phase output circuit of the previous stage output;

The input of the delay unit of each stage of phase output circuit is connected to the output of the single-ended-differential circuit of this stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected to the output of the differential-single-ended circuit of this stage of phase output circuit enter.

A further improvement of the present invention is that the period of the input signal of the voltage-controlled delay line structure is T, and after the delay processing by the delay unit, n channels of clock signals with a delay of T/n at each stage are obtained.

A further improvement of the present invention is that the delay unit of each stage of the phase output circuit adopts a differential pair circuit structure.

A further improvement of the present invention is that the output of the differential-single-ended circuit of the last stage is connected with a single-ended-differential conversion circuit, which is used to ensure the structural consistency of each stage of the circuit.

A method for realizing a high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop of the present invention is based on the existing voltage-controlled delay line structure, including an n-stage phase output circuit, and also includes:

In the existing voltage-controlled delay line structure, the connection between the differential delay circuits of the phase output circuits of each stage is disconnected;

From the second stage phase output circuit to the nth stage phase output circuit, a single-end-differential circuit is added to each stage phase output circuit; wherein, the output of the single-end-differential circuit of each stage phase output circuit is the same as the current stage phase output circuit The input of the differential delay circuit is connected, and the input of the single-ended-differential circuit of the phase output circuit of each stage is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage.

A further improvement of the present invention is that the existing voltage-controlled delay line structure includes: a single-ended-differential circuit and a multi-stage phase output circuit;

In the multi-level phase output circuit, the phase output circuits at all levels are composed of a differential delay circuit and a differential-single-ended circuit; wherein, the output of the differential delay circuit is used as the input of the differential-single-ended circuit, and the output of the differential single-ended circuit is used as Output clock signals of phase output circuits at all levels;

The single-ended-differential circuit is used to output differential signals; the single-ended-differential circuit is used to access the reference clock REF;

The output of the single-ended-differential circuit is connected to the input of the differential delay circuit in the first stage phase output circuit; in the second stage to the nth stage phase output circuit, the input of the differential delay circuit in the phase output circuit is connected to the previous stage phase output The differential delay circuit in the circuit.

Compared with the prior art, the present invention has the following beneficial effects:

Aiming at the phase error caused by inter-stage mismatch, the invention proposes a VCDL structure with better matching performance and high phase precision. The voltage-controlled delay line structure of the present invention can output multi-phase clocks by matching the same modules for the phase output circuits of all levels, and adopting an end-to-end inter-level connection mode to output multi-phase clocks. On the one hand, it can reduce the matching error from the circuit level, on the other hand Also because the circuit structure is simple, chip area and power consumption can be saved.

In the VCDL structure of the present invention, each stage of phase output circuit includes three parts: a single-end-differential circuit (module I), a delay unit (module II) and a differential-single-end circuit (module III). In the circuit module I, the input of the single-ended-differential circuit is connected to the reference clock REF of the system or the output of the previous stage, and after conversion by the internal circuit, the differential signals INa and INb are output. In the circuit module II, the delay unit adopts a differential pair circuit structure, and its differential input is connected to the outputs INa and INb of the single-end-differential circuit, and outputs differential signals OUTa and OUTb. This structure realizes the delay function while, Can reduce the influence of noise on the circuit. In the circuit module III, the input of the differential-single-ended circuit is connected to the outputs OUTb and OUTa of the delay unit, and the single-ended clock signal OUTn is output; considering the load effect, an STD is added to the last-stage differential-single-ended circuit , so that the matching of the n phase output circuits is better. The circuit structure provided by the invention is simple and easy to implement, and can better meet the needs of the development of low-power miniaturized integrated circuits.

The method of the invention can realize the high-phase-accuracy voltage-controlled delay line structure used in the multi-phase delay phase-locked loop of the invention. The circuit structure realized by the invention is simple, and can better meet the needs of the development of miniaturized integrated circuits with low power consumption.

The VCDL structure of the present invention does not need to add any calibration circuit, but through the optimization of its own circuit structure, it ensures the consistency of the circuit structure of each level. The average current of the circuit is about 540μA, which has the characteristics of low power consumption.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art; obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is the schematic structural diagram of the existing VCDL structure realization circuit;

Fig. 2 is a schematic diagram of a high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop according to an embodiment of the present invention;

Fig. 3 is the traditional VCDL structure and the VCDL structure output phase simulation result schematic diagram of the embodiment of the present invention; (a) among Fig. 3 is the traditional existing VCDL structure output phase simulation result schematic diagram, (b) among Fig. 3 is the present invention A schematic diagram of the output phase simulation result of the VCDL structure of the embodiment.

Detailed ways

In order to make the purpose, technical effects and technical solutions of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments It is a part of the embodiment of the present invention. Based on the disclosed embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall all fall within the protection scope of the present invention.

Please refer to Fig. 2, a high phase precision voltage-controlled delay line structure for multi-phase delay phase-locked loop according to the embodiment of the present invention. The voltage-controlled delay line structure of the present invention is a simple multi-phase DLL implemented by a circuit High phase precision VCDL structure; all transistors in the circuit adopt the same manufacturing process. In the present invention, each stage of phase output circuit includes three parts: a single-end-differential circuit (module I), a delay unit (module II) and a differential-single-end circuit (module III).

Specifically, the high phase precision voltage-controlled delay line (Voltage-Controlled-Delay Line, VCDL) structure of the present invention includes n (greater than or equal to 2) stage phase output circuits; each stage phase output circuit includes: single-ended-differential circuit STD (Single-to-Differential), for outputting a differential signal; a delay unit, for delaying the differential signal output by the single-ended-differential circuit; differential-single-ended circuit DTS (Differential-to-Single), It is used to convert the differential output signal of the delay unit into a single-ended signal as the output clock signal of the phase output circuit of each stage; wherein, the single-ended-differential circuit of the phase output circuit of the first stage is used to access the reference clock REF, the single-end-differential circuit of the phase output circuit of other stages is connected to the output of the differential-single-ended circuit of the phase output circuit of the previous stage; the input of the delay unit of each stage of phase output circuit is connected to the single-end of the phase output circuit The terminal-the output of the differential circuit, the output of the delay unit of each stage of the phase output circuit is connected to the input of the differential-single-ended circuit of the phase output circuit of this stage.

The input of the single-ended-differential circuit shown in module I is connected to the reference clock REF of the system or the output of the previous stage. After conversion by the internal circuit, the output differential signals INa and INb are used to provide a pair of differential signals to the delay unit.

The delay unit shown in module II adopts a differential pair circuit structure, and its differential input is connected to the outputs INa and INb of the single-ended-differential circuit, and outputs differential signals OUTa and OUTb. This structure can reduce the delay while realizing the delay effect. The impact of noise on the circuit; assuming that the input signal period is T, and VCDL has n-stage phase output circuits, after processing by the delay unit, n-channel clock signals with each stage delay of T/n are obtained.

The input of the differential-single-ended circuit shown in module III is connected to the output OUTb and OUTa of the delay unit, and the output clock signal OUTn is used to output the delayed differential signal in the form of a single-ended clock signal; considering the load effect , an STD is added to the last differential-single-ended circuit to make the n phase output circuits better matched.

Explanation in the embodiments of the present invention:

DLL: Delay Locked Loop, delay-locked loop; TDC: Time-to-Digital Converter, time-to-digital converter; VCDL: Voltage-Controlled Delay Line, voltage-controlled delay line.

Table 1 Comparison of Phase Accuracy between the Traditional VCDL Structure and the VCDL Structure of the Embodiment of the Invention*

*This data is based on the simulation results under the condition of T=10ns, n=4

In the embodiment of the present invention, the single-ended-differential circuit, the delay unit and the differential-single-ended circuit included in each stage of the phase output circuit have multiple implementations, and the present invention does not limit the specific implementation of a single module circuit.

In order to verify the effect of the VCDL structure of the embodiment of the present invention, under the condition that the power supply voltage is 1.8V, the period is 10ns, and n=4, the DLLs including the traditional VCDL structure and the VCDL structure of this embodiment are simulated and compared respectively, wherein STD The circuit adopts literature (Seung-Jun Bae, Hyung-Joon Chi, Hyung-Rae Kim and Hong-June Park,"A3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digitalcalibration of equalization skew and offset coefficients," The structure shown in ISSCC.2005, pp.520-521.) is realized by the inverter circuit; the delay circuit adopts the literature (J.Wu, Y.Zhang, R.Zhao, K.Zhang, L.Zheng and W.Sun, "Low-jitter DLL applied for two-segment TDC," IET Circuits, Devices & Systems, vol.12, no.1, pp.17-24, Jan.2018.) The differential circuit structure shown in; DTS The circuit adopts literature (Joonsuk Lee, and Beomsup Kim, A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control, IEEE Journal of Solid-State Circuits, vol.35, no.8, pp.1137-1145.Aug .2000.) as shown in the structure.

Please refer to Figure 3, the phase accuracy simulation results are shown in Figure 3, and the data are organized in Table 1. The expected phase difference between every two adjacent output signals is π/2, which is 2.5ns. In fact, the simulation results show that the maximum phase error rate of the traditional VCDL structure is -6.8%, that is, the delay is 2.33ns, and the error is 0.17ns, while the maximum phase error rate of the embodiment of the present invention is only 0.8%, that is, the delay is 2.52ns, and the error is 0.02ns. The phase accuracy of the VCDL structure of the embodiment of the present invention is greatly improved compared with the traditional VCDL structure.

In addition, in order to improve the phase accuracy, some calibration schemes are currently available. H.-H.Chang, J.-Y.Chang and C.-Y.Kuo et al. proposed digital self-calibration technology in a paper entitled "A 0.7-2-GHz self-calibrated multiphase delay-locked loop", Adjust the output of each stage of VCDL with a digital calibration circuit to complete the improvement of the phase accuracy. Including the digital calibration circuit, the average current of each stage of the VCDL circuit is 5mA. S.Hwang, K.Kim and J.Kim proposed analog calibration technology in a paper entitled "A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor", adding analog to each level of VCDL output Calibration circuit, including the analog calibration circuit, the average current of each stage of VCDL circuit is 930μA; the VCDL structure of the embodiment of the present invention does not need to add any calibration circuit, but through the optimization of its own circuit structure, it ensures that each stage The consistency of the circuit structure, in the case of achieving a phase accuracy equivalent to the above-mentioned results, the average current of each stage of the circuit is 540μA, which has the characteristics of low power consumption.

To sum up, the embodiment of the present invention provides a high-phase-accuracy VCDL structure applied to multi-phase DLLs. The implementation circuit is simple. Except for the first stage, the phase output circuit of each stage only needs to be added on the basis of the traditional VCDL structure circuit. 1 STD can be achieved. Compared with the traditional VCDL structure circuit, the implementation circuit of the VCDL structure disclosed in the present invention reduces the phase error caused by the mismatch between stages by performing structural matching on each stage phase output circuit, thereby improving the output phase accuracy and realizing Low power consumption and miniaturization of the chip.

A method for realizing a high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop in an embodiment of the present invention is based on an existing voltage-controlled delay line structure, including an n-stage phase output circuit, including:

In the existing voltage-controlled delay line structure, the connection between the differential delay circuits of the phase output circuits of each stage is disconnected;

From the second stage phase output circuit to the nth stage phase output circuit, a single-end-differential circuit is added to each stage phase output circuit; wherein, the output of the single-end-differential circuit of each stage phase output circuit is the same as the current stage phase output circuit The input of the differential delay circuit is connected, and the input of the single-ended-differential circuit of the phase output circuit of each stage is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage.

The existing voltage-controlled delay line structure includes: a single-ended-differential circuit and a multi-stage phase output circuit;

In the multi-level phase output circuit, the phase output circuits at all levels are composed of a differential delay circuit and a differential-single-ended circuit; wherein, the output of the differential delay circuit is used as the input of the differential-single-ended circuit, and the output of the differential single-ended circuit is used as Output clock signals of phase output circuits at all levels;

The single-ended-differential circuit is used to output differential signals; the single-ended-differential circuit is used to access the reference clock REF;

The output of the single-ended-differential circuit is connected to the input of the differential delay circuit in the first stage phase output circuit; in the second stage to the nth stage phase output circuit, the input of the differential delay circuit in the phase output circuit is connected to the previous stage phase output The differential delay circuit in the circuit.

In summary, the present invention discloses a high-phase precision voltage-controlled delay line (Voltage-Controlled Delay Line, VCDL) structure for a multi-phase delay-locked loop (Delay Locked Loop, DLL), which mainly solves the problem caused by VCDL. The problem of large output phase error caused by the mismatch between stages. Each stage of the phase output circuit of the VCDL structure disclosed by the present invention consists of a single-ended-differential circuit (as shown in Figure 1 module I), a delay unit (as shown in Figure 1 module II) and a differential-single-ended circuit (as shown in Figure 1 module III shown) consists of three parts, among which, the single-ended-differential circuit is used to convert the single-ended input signal into a differential signal; the delay unit is responsible for completing the task of delaying the output of the differential input signal; the differential-single-ended circuit is used to convert The differential signal output by the delay unit is converted into a single-ended clock signal for output. After the input clock passes through the phase output circuit composed of these three modules, it evenly outputs clock signals with the same frequency and different phases. The circuit corresponding to the VCDL structure disclosed by the invention has low power consumption and small scale, and is suitable for low power consumption miniaturized circuit design.

The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art can still modify or equivalently replace the specific embodiments of the present invention. , any modifications or equivalent replacements that do not deviate from the spirit and scope of the present invention are within the protection scope of the claims of the present invention pending application.

Claims (5)

1. A high-phase-accuracy voltage-controlled delay line structure for multi-phase delay phase-locked loops, characterized in that it includes n-stage phase output circuits; Each stage phase output circuit includes: Single-ended-differential circuit for outputting differential signals; a delay unit, configured to delay the differential signal output by the single-ended-differential circuit; Differential-single-ended circuit, for converting the differential output signal of the delay unit into a single-ended signal, as the output clock signal of the phase output circuits at all levels; Among them, the single-ended-differential circuit of the phase output circuit of the first stage is used to access the reference clock REF, and the single-ended-differential circuit of the phase output circuit of other stages is connected to the differential-single-ended circuit of the phase output circuit of the previous stage output; The input of the delay unit of each stage of phase output circuit is connected to the output of the single-ended-differential circuit of this stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected to the output of the differential-single-ended circuit of this stage of phase output circuit enter. 2. A kind of high-phase precision voltage-controlled delay line structure for multi-phase delay phase-locked loop according to claim 1, it is characterized in that, the input signal cycle of described voltage-controlled delay line structure is T, after delaying After delay processing by the timing unit, n clock signals with a delay of T/n at each level are obtained. 3. A kind of high-phase-accuracy voltage-controlled delay line structure for multi-phase delay phase-locked loop according to claim 1, it is characterized in that, the delay unit of each stage phase output circuit all adopts differential pair circuit structure . 4. A kind of high phase precision voltage-controlled delay line structure for multi-phase delay PLL according to claim 1, it is characterized in that, the output of the differential-single-ended circuit of last stage is connected with single-ended- The differential conversion circuit is used to ensure the structural consistency of each stage of the circuit. 5. A method for realizing a high-phase precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop, based on a voltage-controlled delay line structure, comprising an n-level phase output circuit, characterized in that, The voltage-controlled delay line structure includes: a single-ended-differential circuit and a multi-stage phase output circuit; In the multi-level phase output circuit, the phase output circuits at all levels are composed of a differential delay circuit and a differential-single-ended circuit; wherein, the output of the differential delay circuit is used as the input of the differential-single-ended circuit, and the output of the differential single-ended circuit is used as Output clock signals of phase output circuits at all levels; The single-ended-differential circuit is used to output differential signals; the single-ended-differential circuit is used to access the reference clock REF; The output of the single-ended-differential circuit is connected to the input of the differential delay circuit in the first stage phase output circuit; in the second stage to the nth stage phase output circuit, the input of the differential delay circuit in the phase output circuit is connected to the previous stage phase output A differential delay circuit in the circuit; The implementation method includes: In the voltage-controlled delay line structure, the connection between the differential delay circuits of the phase output circuits of each stage is disconnected; From the second stage phase output circuit to the nth stage phase output circuit, a single-end-differential circuit is added to each stage phase output circuit; wherein, the output of the single-end-differential circuit of each stage phase output circuit is the same as the current stage phase output circuit The input of the differential delay circuit is connected, and the input of the single-ended-differential circuit of the phase output circuit of each stage is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage.

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