CN110867457B

CN110867457B - A high capacitance array substrate and manufacturing method thereof

Info

Publication number: CN110867457B
Application number: CN201911135019.6A
Authority: CN
Inventors: 岳华琦; 陈宇怀
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2019-11-19
Filing date: 2019-11-19
Publication date: 2024-12-13
Anticipated expiration: 2039-11-19
Also published as: CN110867457A

Abstract

The invention discloses an array substrate with a high-capacitance structure and a manufacturing method thereof, wherein the method comprises the following steps of manufacturing a buffer layer on the array substrate, manufacturing a hole on the buffer layer, manufacturing a first electrode in the hole, manufacturing a first electrode insulating layer covering the first electrode in the hole, manufacturing a second electrode on the first electrode insulating layer in the hole, manufacturing a second electrode insulating layer covering the second electrode in the hole, manufacturing a third electrode on the second insulating layer in the hole, and further arranging a thin film field effect transistor on the buffer layer outside the hole.

Description

Array substrate with high capacitance structure and manufacturing method

Technical Field

The invention relates to the technical field of display, in particular to an array substrate with a high-capacitance structure and a manufacturing method thereof.

Background

The rapid development in active matrix organic light emitting diode displays (AMOLED) and high performance Active Matrix Liquid Crystal Displays (AMLCD) is worth of many high resolution and high frame rate displays. In order to make the driving circuit have better voltage stabilizing effect, a larger capacity capacitor is usually required to be arranged in the array substrate, but the large capacity capacitor causes large occupied area of the driving circuit, so that the frame size and the pixel size of the display panel cannot be further reduced. How to design and manufacture high-performance and small-sized array substrate structures is an increasingly required research topic.

IGZO (indium gallium zinc oxide) is indium gallium zinc oxide, is an amorphous oxide containing indium, gallium and zinc, has carrier mobility of 20 to 30 times that of amorphous silicon, can greatly improve the charge and discharge rate of TFT to pixel electrode, improves the response speed of pixel, has faster panel refresh frequency, and can realize ultra-high resolution display panel. Meanwhile, the existing amorphous silicon production line can be compatible with an IGZO process by only slightly changing, so that the low-temperature polysilicon (LTPS) has more competitiveness in the aspect of cost.

Disclosure of Invention

Therefore, it is necessary to provide an array substrate with a high capacitance structure and a manufacturing method thereof, which solve the problem of excessive area occupation when preparing a display device.

In order to achieve the above object, the present inventors provide a method for manufacturing an array substrate with a high capacitance structure, comprising the steps of:

Manufacturing a buffer layer on an array substrate;

making holes in the buffer layer;

depositing a first layer of metal, forming a first electrode in the hole, wherein the first electrode is used as a polar plate of the lower capacitor structure;

After covering the first insulating layer, continuing to deposit a second layer of metal, forming a first electrode insulating layer covering the first electrode in the hole, forming a second electrode on the first electrode insulating layer in the hole, wherein the second electrode is used as a common electrode plate of the upper-layer capacitor structure and the lower-layer capacitor structure;

covering the second insulating layer, forming a second electrode insulating layer covering the second electrode in the hole;

Depositing a third layer of metal, and forming a third electrode on the second insulating layer in the hole, wherein the third electrode is used as a polar plate of the upper capacitor structure;

And a thin film field effect transistor is also arranged on the buffer layer outside the hole.

Further, the method also comprises the following steps:

The method comprises the steps of depositing a first layer of metal, extending a first electrode in a hole to the surface of a buffer layer, or extending a second electrode in the hole and the first electrode insulating layer to the surface of an outer buffer layer when the second layer of metal is continuously deposited after the first insulating layer is covered, or extending the second electrode insulating layer in the hole to the surface of the outer buffer layer when the second insulating layer is covered, or extending a third electrode in the hole to the surface of the outer buffer layer when the third layer of metal is deposited, or connecting the third electrode on the surface of the outer buffer layer and the first electrode on the surface of the outer buffer layer.

Further, the manufacturing steps of the thin film field effect transistor are as follows:

After depositing the first layer of metal, continuing to deposit gate metal, forming first metal and gate scanning lines on the buffer layer outside the holes, wherein the first metal is on the buffer layer outside the holes, and the gate scanning lines are on the first metal;

after covering the first insulating layer, continuing to deposit a second layer of metal, forming a gate insulating layer on the gate scanning line, covering and wrapping the gate scanning line and the first metal by the gate insulating layer, and forming a second metal on the gate insulating layer;

Forming a barrier layer on the second metal while covering the second insulating layer;

forming a third metal on the barrier layer to wrap the second metal and both sides of the barrier layer while depositing the third metal, the third metal exposing a central portion of the barrier layer;

And depositing a fourth layer of metal, forming a source electrode signal line on one side of the third metal, and forming a drain electrode on the other side of the third metal.

Further, after depositing the first layer of metal, when continuing to deposit the gate metal, the method further comprises the following steps:

Coating a photoresist on the grid metal, and patterning the photoresist by using a half-tone mask plate with a semi-transparent area, a full-transparent area and a full-shading area, wherein the semi-transparent area corresponds to an incomplete development area after the photoresist is developed, the full-transparent area or the full-shading area corresponds to a complete development area, the incomplete development area corresponds to an area of a first electrode in the capacitor structure, and the complete development area corresponds to an area of a grid scanning line;

etching the gate metal and the first layer metal on the regions outside the fully developed region and the incompletely developed region with the photoresist as a mask;

removing the photoresist on the first layer metal in the incomplete development area through ashing treatment, and reserving the photoresist on the grid metal in the complete development area;

And etching the gate metal in the incompletely developed region to the first layer metal, reserving the first layer metal as a first electrode, and removing the photoresist on the completely developed region to form the first metal and the gate scanning line.

Further, when the second layer of metal is deposited after the first insulating layer is covered, the method further comprises the following steps:

Coating a photoresist on the second metal layer, and patterning the photoresist by using a half-tone mask plate with a semi-transparent area, a full-transparent area and a full-shading area, wherein the semi-transparent area corresponds to an incomplete development area after the photoresist is developed, the full-transparent area or the full-shading area corresponds to a complete development area, the incomplete development area corresponds to an area of a second electrode in the capacitor structure, and the complete development area corresponds to an area of the second metal layer;

Etching the second metal layer on the partial development region and the region outside the full development region, removing the photoresist on the second metal layer in the partial development region by ashing treatment, then hydrogen ion implantation, removing the photoresist on the first insulating layer material in the full development region, reserving the second metal layer and the first insulating layer of the partial development region as a second electrode and a first electrode insulating layer respectively, and reserving the second metal layer and the first insulating layer of the full development region as a second metal and a gate insulating layer respectively.

Further, the method also comprises the following steps:

and covering the third insulating layer material, forming a passivation layer on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, wherein the passivation layer protects the capacitor structure and the thin film field effect transistor.

Further, the material of the first layer of metal is indium tin oxide.

The invention provides an array substrate with a high-capacitance structure, which is characterized in that the array substrate with the high-capacitance structure is prepared by the method for manufacturing the array substrate with the high-capacitance structure.

The invention provides an array substrate with a high capacitance structure, comprising:

a buffer layer is arranged on the array substrate, holes are formed in the buffer layer, and a thin film field effect transistor is arranged on the buffer layer outside the holes;

The first electrode is used as a polar plate of the lower capacitor structure, the first electrode insulating layer covers the first electrode and is used as a dielectric layer of the lower capacitor structure, the second electrode is arranged on the first electrode insulating layer and is used as a common polar plate of the upper capacitor structure and the lower capacitor structure, the second electrode insulating layer covers the second electrode and is used as a dielectric layer of the upper capacitor structure, and the third electrode is arranged on the second electrode insulating layer and is used as a polar plate of the upper capacitor structure.

Further, the thin film field effect transistor includes:

a first metal is arranged on the buffer layer outside the hole, and a grid scanning line is arranged on the first metal;

A gate insulating layer is arranged on the gate scanning line, and the gate insulating layer covers and wraps the gate scanning line and the first metal;

A second metal is arranged on the grid insulating layer, and a barrier layer is arranged on the second metal;

the barrier layer is provided with third metal, the second metal and two sides of the barrier layer are wrapped by the third metal, the third metal is exposed out of the center part of the barrier layer, one side of the third metal is provided with a source electrode signal wire, and the other side of the third metal is provided with a drain electrode.

Compared with the prior art, the thin film field effect transistor with the high-capacitance structure is manufactured by the technical scheme, the circuit driven by the high-capacitance structure has better voltage stabilizing effect, the capacitance value of the storage capacitor can be increased, the occupied area of the capacitor is reduced, and the advantages of improving the pixel density (ppi) of the panel and reducing the frame size of the panel are also achieved.

Drawings

FIG. 1 is a schematic cross-sectional view of a buffer layer and holes formed on an array substrate according to the present invention;

FIG. 2 is a process flow diagram of fabricating a first electrode, a first metal and a gate scan line on an array substrate according to the present invention;

FIG. 3 is a flow chart of a process for fabricating a first electrode insulating layer, a gate insulating layer, a second electrode and a second metal on an array substrate according to the present invention;

FIG. 4 is a schematic cross-sectional view of a second electrode insulating layer and a barrier layer fabricated on an array substrate according to the present invention;

fig. 5 is a schematic cross-sectional view of a thin film field effect transistor according to another embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of a third electrode, a third metal, a source signal line and a drain electrode fabricated on an array substrate according to the present invention;

FIG. 7 is a schematic cross-sectional view of a passivation layer formed on an array substrate according to the present invention;

FIG. 8 is a schematic diagram of a parallel structure of a grid-like capacitor according to the present invention;

Fig. 9 is a schematic cross-sectional view of a gate capacitor structure according to the present invention.

Reference numerals illustrate:

1. An array substrate;

2. A buffer layer;

201. a hole;

3. A first layer of metal;

301. A first electrode;

302. a first metal;

4. A gate metal;

401. A gate scan line;

5. Half-color mask plate;

6. a first insulating layer;

601. A first electrode insulating layer;

602. A gate insulating layer;

7. a second layer of metal;

701. A second electrode;

702. A second metal;

8. a second insulating layer;

801. A second electrode insulating layer;

802. a barrier layer;

9. a third layer of metal;

901. a third electrode;

902. a third metal;

10. a fourth layer of metal;

1001. a source signal line;

1002. A drain electrode;

1100. And a passivation layer.

Detailed Description

In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.

Referring to fig. 1 to 9, the embodiment provides a method for manufacturing an array substrate with a high capacitance structure, which can be performed on an array substrate 1, wherein a field thin film transistor is manufactured on one side of the array substrate 1, and a capacitance structure is manufactured on the other side of the array substrate 1, and the method comprises the steps of manufacturing a buffer layer 2 and a hole 201 on the array substrate 1, wherein the buffer layer 2 is covered on the array substrate 1, and the buffer layer 2 is made of one or more of organic photosensitive material, polyimide (PI), silicon oxide composite film (SiOx), silicon nitride composite film (SiNx) and titanium oxide. After the buffer layer 2 is manufactured, a hole 201 is formed on the buffer layer 2, a photoresist is coated on the buffer layer 2, the photoresist is patterned, namely, the exposure and development are performed to enable the part to be formed with the hole 201 to be opened, then the photoresist is used as a mask to etch the buffer layer 2 to obtain the hole, and the photoresist is removed after the hole is formed. The manufacturing method can manufacture a plurality of holes 201 at the same time, the cross section of the holes 201 can be rectangular, circular or other irregular shapes, for example, the cross section of the holes 201 with rectangular cross section is displayed by the manufacturing method, the width of the cross section gradually decreases from top to bottom, and the width of the hole bottom is smaller than the width of the hole opening, so that the holes 201 with the strip-shaped grid-shaped structures are formed, and grid-shaped capacitor structures can be manufactured in the holes 201 and between the holes 201 and the holes 201.

Next, a first layer of metal 3 and a gate metal 4 are formed on the array substrate 1 to form a first electrode 301, a first metal 302 and a gate scan line 401, referring to fig. 2, the specific process steps are that the first layer of metal 3 and the gate metal 4 are plated on the array substrate 1 by electroplating, vapor deposition or sputtering, and the gate metal 4 is covered on the first layer of metal 3, and the structure is shown in the first diagram of fig. 2. The material of the first layer metal 3 is Indium Tin Oxide (ITO), the thickness of the indium tin oxide film is 100 to 1000 a, and the material of the gate metal 4 is one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity or other alloys. The photoresist on the gate metal 4 is then patterned using a half tone mask 5 having a semi-transparent region 501, a fully transparent region 502 and a fully opaque region 503, as shown in the second diagram of fig. 2. The light transmittance of the semi-transparent region 501 is 50%, the light transmittance of the fully transparent region 502 is 100%, the light transmittance of the fully opaque region 503 is 0%, the semi-transparent region 501 corresponds to an incompletely developed region after photoresist development, the fully transparent region 502 or the fully opaque region 503 corresponds to a completely developed region, the incompletely developed region corresponds to the region of the first electrode 301 in the capacitor structure, and the completely developed region corresponds to the region of the gate scan line 401 of the thin film field effect transistor. The semi-transparent region 501 corresponds to an incompletely developed region, i.e., a region of the first electrode 301 in the capacitor structure, when a negative photoresist is applied, the fully transparent region 502 corresponds to a completely developed region, i.e., a region of the gate scan line 401, and when a positive photoresist is applied, the semi-transparent region 501 corresponds to an incompletely developed region, i.e., a region of the first electrode 301 in the capacitor structure, and the fully light-shielding region 503 corresponds to a completely developed region, i.e., a region of the gate scan line 401. The manufacturing method coats positive photoresist on the grid metal 4, and utilizes a half-tone mask plate with a semi-transparent region 501, a full-transparent region 502 and a full-shading region 503 to pattern the photoresist, wherein the semi-transparent region 501 corresponds to an incomplete development region, the incomplete development region corresponds to a region of the first electrode 301 in the capacitor structure, the full-shading region 503 corresponds to a full development region, and the full development region corresponds to a region of the grid scanning line 401 in the thin film field effect transistor. after the photoresist is developed, the photoresist in the areas outside the incompletely developed areas and the completely developed areas is completely removed, and the photoresist in the incompletely developed areas is thinned compared with the photoresist in the completely developed areas, and the structure is shown in the third graph of fig. 2. Then, the gate metal 4 and the first metal layer 3 on the regions outside the incompletely developed region and the completely developed region are etched with a photoresist and a mask, the structure is as shown in the third diagram of fig. 2, then the photoresist on the first metal layer 3 in the incompletely developed region is removed by ashing treatment, the structure is as shown in the fourth diagram of fig. 2, the gate metal 4 in the incompletely developed region is removed by etching time control or selectivity of an etching liquid, the first metal layer 3 in the incompletely developed region is remained and the first electrode 301 is formed in the hole 201, the gate metal 4 and the first metal layer 3 in the completely developed region are remained and the gate scan line 401 and the first metal 302 are formed on the buffer layer 2 outside the hole 201, and finally the metal is lifted off and photoresist is removed for cleaning. The first electrode 301 and the first metal 302 are on the buffer layer 2, the first electrode 301 and the first metal 302 have a gap, and the gate scan line 401 is on the first metal 302. When the first electrode 301 is formed in the hole 201 as the first electrode 301 of the lower capacitor structure, a portion of the first metal layer 3 on the surface of the buffer layer 2 between the holes 201 and 201 or on the surface of the buffer layer 2 around the holes 201 on both sides may be reserved as the first electrode 301, on the one hand, the first electrode 301 on the surface of the buffer layer 2 may be used as a connection point between the capacitor structure and other circuits, such as parallel connection between the upper capacitor structure and the lower capacitor structure, and on the other hand, the first electrode 301 between the holes 201 and the holes 201 may be connected with the capacitor structures in the two holes 201, thereby further improving the capacitance capacity. The first layer metal 3 and the grid metal 4 are formed once, only the first layer metal 3 is reserved in the capacitor area to serve as an electrode, the indium tin oxide is thinner (100-1000 meter) because the material of the first layer metal 3 is indium tin oxide, the number of strip-shaped grid-shaped holes is increased, the capacity of the capacitor is further improved, and the ohmic contact resistance value can be reduced by taking the indium tin oxide as a bridge to connect the active layer with the source electrode signal line 1001 and the drain electrode 1002, and the electrical property of the thin film field effect transistor is improved. The manufacturing method can directly use metal as the electrode of the capacitor structure, and can simplify the process.

Referring to fig. 3, the specific process is to cover the first insulating layer 6 on the array substrate 1, and then to continue to plate the second metal layer 7 on the first insulating layer 6, wherein the second metal layer 7 can be formed by electroplating, vapor deposition and sputtering, and the structure is shown in the first diagram of fig. 3. The first insulating layer 6 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like, and the second layer metal 7 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), IGZTO, or the like. The photoresist is also patterned using a half tone reticle 5 having a semi-transparent region 501, a fully transparent region 502, and a fully opaque region 503. The light transmittance of the semi-transparent region 501 is 50%, the light transmittance of the fully transparent region 502 is 100%, the light transmittance of the fully opaque region 503 is 0%, the semi-transparent region 501 corresponds to an incompletely developed region after photoresist development, the fully transparent region 502 or the fully opaque region 503 corresponds to a completely developed region, the incompletely developed region corresponds to the region of the second electrode 701 in the capacitor structure, and the completely developed region corresponds to the region of the second metal 702. The semi-transparent region 501 corresponds to an incompletely developed region, i.e., a region of the second electrode 701 in the capacitor structure, if a negative photoresist is applied, and the fully transparent region 502 corresponds to a completely developed region, i.e., a region of the second metal 702, if a positive photoresist is applied, the semi-transparent region 501 corresponds to an incompletely developed region, i.e., a region of the second electrode 701 in the capacitor structure, and the fully light-shielding region 503 corresponds to a completely developed region, i.e., a region of the second metal 702. Referring to the second diagram of fig. 3, a positive photoresist is coated on the second metal layer 7, and the photoresist is patterned by using a half tone mask 5 having a semi-transparent region 501, a full-transparent region 502 and a full-opaque region 503, wherein the semi-transparent region 501 corresponds to an incompletely developed region, the incompletely developed region corresponds to a region of the second electrode 701 in the capacitor structure, the full-opaque region 503 corresponds to a fully developed region, and the fully developed region corresponds to a region of the second metal of the thin film field effect transistor. After the photoresist is developed, the photoresist in the areas outside the incompletely developed areas and the completely developed areas is completely removed, and the photoresist in the incompletely developed areas is thinned compared with the photoresist in the completely developed areas, and the structure is shown in the third graph of fig. 3. The second metal layer 6 is then etched with a photoresist and mask in areas outside the incompletely developed areas and the completely developed areas, leaving the first insulating layer 6, the structure of which is shown in the fourth diagram of fig. 3. Then, the photoresist on the second metal layer 7 in the incompletely developed region is removed by ashing, the metal oxide of the capacitor structure is made conductive by hydrogen ion implantation, and the ohmic contact characteristics between the oxide of the thin film field effect transistor and the source signal line 1001 and drain electrode 1002 are improved, so that the contact resistance is reduced, and the structure is as shown in a fifth graph of fig. 3. After the hydrogen ion implantation, the first insulating layer 6 of the incompletely developed region is remained, a first electrode insulating layer 601 covering the first electrode 301 is formed in the hole 201 and on the surface of the buffer layer 2 between the holes 201 and 201, the second metal 7 of the incompletely developed region is remained, the second electrode 701 is formed in the hole 201, the first insulating layer 6 and the second metal 7 of the completely developed region are remained, the gate insulating layer 602 and the second metal 702 are formed on the buffer layer 2 outside the hole 201, and finally the metals are lifted off and photoresist-removed for cleaning. when the second electrode 701 is formed in the hole 201, the second electrode 701 is generally kept, and a part of the second layer metal 7 on the surface of the buffer layer 2 between the hole 201 and the hole 201 or on the surface of the buffer layer 2 around the holes 201 is also kept as the second electrode 701, so that the second electrode 701 between the hole 201 and the hole 201 can be connected to the capacitance structure in the two holes 201. The manufacturing method can directly use metal as the electrode of the capacitor structure, and can simplify the process.

The first electrode insulating layer 601 covered on the first electrode 301 is used as a dielectric layer of the lower capacitor structure, the first electrode insulating layer 601 realizes isolation between the first electrode 301 and the second electrode 701 in the lower capacitor structure, so that electric connection between the first electrode 301 and the second electrode 701 is avoided, the second electrode 701 is arranged on the first electrode insulating layer 601, the second electrode 601 is used as a common electrode plate of the upper capacitor structure and the lower capacitor structure, the gate insulating layer 602 covers and wraps the gate scanning line 401 and the first metal 302, and the second metal 702 is arranged on the gate insulating layer 602 and is used as an active layer of the thin film field effect transistor.

Then, referring to fig. 4, a second electrode insulating layer 801 and a barrier layer 802 are formed, wherein a second insulating layer 8 is covered on the array substrate 1, and the second insulating layer 8 and the first insulating layer 6 are made of the same material, such as a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, and aluminum oxide. And then, carrying out photoetching patterning on the second insulating layer 8, etching the second insulating layer 8 by taking the photoresist as a mask, exposing two sides of the second metal 702 and two sides of the gate insulating layer, forming a blocking layer 802 on the second metal 702, etching the second insulating layer 8 on the surface of the buffer layer 2 outside the hole 201 to the first electrode 301 by taking the photoresist as a mask, forming a through hole at the bottom of the through hole, forming a second electrode insulating layer 801 covering the second electrode 701 on the second electrode 701 in the hole 201 and on the surface of the buffer layer 2 between the hole 201 and the hole 201, wherein the second electrode insulating layer 801 is used as a dielectric layer of an upper capacitor structure, and the second electrode insulating layer 801 realizes isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding electric connection between the second electrode 701 and the third electrode 901. The first electrode 301 at the bottom of the via hole may be connected to the third electrode 901, thereby realizing connection of the upper layer capacitor structure and the lower layer capacitor structure. After the second electrode insulating layer 801 and the barrier layer 802 are formed, the photoresist is removed. In some embodiments, the blocking layer 802 on the second metal 702 may be formed without fabrication, and may be configured as a BCE-structured thin film field effect transistor according to the need, so as to save a photomask, and the structure is shown in fig. 5.

Referring to FIG. 6, a third metal layer 9 is deposited, a third metal layer 902 is formed on the second metal layer 702 and the barrier layer 802, a third electrode 9 is formed in the hole 201, a part of the third metal layer 9 on the surface of the buffer layer 2 between the holes 201 and 201 or on the surface of the buffer layer 2 around the holes 201 on both sides is also reserved as the third electrode 901, the third electrode 901 can be connected with the first electrode 301 through holes of the second electrode insulating layer 802 on the first electrode 301, and after the third electrode 901 is connected with the first electrode 301, the upper capacitor structure and the lower capacitor structure are connected in parallel. The manufacturing method can directly use metal as the electrode of the capacitor structure, and can simplify the process.

The third metal 902 wraps the second metal 702 over the barrier layer 802 and both sides of the barrier layer 802, with the third metal 902 exposing a central portion of the barrier layer 802, i.e., the third metal 902 has two portions. After the third metal 902 is fabricated, a fourth metal 10 is deposited, where the fourth metal 10 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), IGZTO, and the source signal line 1001 is formed on one side of the third metal 902, and the drain electrode 1002 is formed on the other side of the third metal 902, and the source signal line 1001 and the drain electrode 1002 have a gap, and the structure is shown in fig. 6. After the third electrode 901, the source signal line 1001 and the drain electrode 1002 are manufactured, the metal is lifted off and photoresist is removed for cleaning.

In order to protect the capacitor structure and avoid direct contact between the external structure and the capacitor structure and the thin film field effect transistor, the passivation layer 1100 is also fabricated by the fabrication method, referring to fig. 7, the passivation layer 1100 may be plated by chemical vapor deposition, and the passivation layer 1100 is made of materials such as silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), titanium oxide, and aluminum oxide. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, the third electrode 901, and the like, and after the covering, only the passivation layer 1100 is contacted from the outside, and the capacitor structure and the thin film field effect transistor are not contacted.

Referring to fig. 8 to 9, the three-dimensional grid structure capacitor of the invention can effectively reduce the occupied area of the capacitor region compared with the original flat plate type capacitor, and reduce the size of the capacitor under the condition of keeping the same capacity, and the capacitor region of the array substrate is reserved with metal oxide and is conductive to be used as a capacitor electrode, so that the ohmic contact characteristic is improved, the contact resistance is reduced, two groups of parallel capacitors with excellent performance are formed, and the capacity of the capacitor is further increased. Referring to fig. 8, in the case where the parallel capacitance formula C and = c1+c2 (C1, C2 are the upper and lower capacitor structures) is equal to the holding capacity, the actual occupied area of the grid capacitor can be further reduced by 50% compared to the theoretical capacitance area of the flat panel, referring to fig. 9, in which the capacitance area s= (s1+s2+s3+s4) n of the grid capacitor, the occupied area S _{Real world} = (s1 '+s2+s3+s4')n, and the actual occupied area of the grid capacitor can be reduced by 33% compared to the capacitance area of the flat panel in the case where the holding capacity is equal to the holding capacity according to the trigonometric function S1 '=sin α S1, if the design S1' =s2=s3, taper α=60°.

The first layer metal and the gate metal are formed once, and only indium tin oxide (the material of the first layer metal) is reserved in the capacitance area as an electrode, and the indium tin oxide is thinner (100 to 1000 meter), so that the number of strip-shaped grid-shaped holes is increased, and the capacitance capacity is further improved. And secondly, the indium tin oxide is used as a bridge to connect the active layer with the source electrode and the drain electrode, so that the ohmic contact resistance can be reduced, and the electrical property of the thin film field effect transistor is improved. The electrode area of the manufacturing method can also directly use metal as an electrode plate, and the process can be simplified.

The invention provides an array substrate with a high-capacitance structure, as shown in fig. 1,4 to 9, and the array substrate with the high-capacitance structure of the embodiment can be manufactured according to the above method. The array substrate with the high-capacitance structure comprises an array substrate 1, wherein a buffer layer 2 is arranged on the array substrate 1, and the buffer layer 2 is made of one or more of organic photosensitive materials, polyimide films (PI), silicon oxide composite films (SiOx), silicon nitride composite films (SiNx) and titanium oxide. A plurality of holes 201 are provided in the buffer layer 2, and the structure is as shown in fig. 1. The cross section of the hole 201 of the present invention may be rectangular, circular, or other irregular shapes, and the structure is shown in fig. 6, for example, the cross section of the hole 201 with a bar-shaped grid structure is rectangular, the width of the cross section gradually decreases from top to bottom, the width of the hole bottom is smaller than the width of the hole opening, and grid-shaped capacitor structures are arranged in the hole 201 and between the holes 201 and 201. A thin film field effect transistor is provided on the buffer layer 2 outside the hole 201.

Referring to fig. 4, a first electrode 301, a first electrode insulating layer 601 and a second electrode 701 are sequentially disposed in the hole 201 and between the hole 201 and the hole 201, wherein the first electrode 301 is used as a plate of a lower capacitor structure, the first electrode insulating layer 601 covers the first electrode 301 and is used as a dielectric layer of the lower capacitor structure, the second electrode is disposed on the first electrode insulating layer and is used as a common plate of an upper capacitor structure and a lower capacitor structure, the second electrode insulating layer covers the second electrode and is used as a dielectric layer of the upper capacitor structure, and the first electrode insulating layer 601 realizes isolation between the first electrode 301 and the second electrode 701 in the lower capacitor structure, so as to avoid electrical connection between the first electrode 301 and the second electrode 701. The first electrode 301, the first electrode insulating layer 601, and the second electrode 701 constitute a lower capacitance structure. Since the first electrode 301 and the second electrode 701 on both sides of the inner wall of the hole are grid-shaped planes, the area of the metal can be greatly increased, and thus, a larger capacitance value can be realized. While reducing parasitic capacitance effects and the required semiconductor device area. Referring to fig. 9, the capacitance area s= (s1+s2+s3+s4) ×n of the grid-like capacitor, the occupied area S _{Real world} = (s1 '+s2+s3+s4')×n, and if s1 '=s2=s3, taper α=60° is designed according to the trigonometric function s1' =sinα×s1, the actual occupied area of the grid-like capacitor can be reduced by 33% compared with the conventional plate capacitor area under the condition of equal holding capacity.

The first electrode 301 is made of indium tin oxide, which is thinner (100 to 1000 meter), which is beneficial to increasing the number of the first electrode 301 and further increasing the capacitance, and secondly, the ohmic contact resistance can be reduced by taking the indium tin oxide as a bridge to connect the active layer with the source signal line 1001 and the drain 1002, and the electrical performance of the thin film field effect transistor can be improved. The first electrode insulating layer 601 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like.

Referring to fig. 6, a second electrode insulating layer 801 and a third electrode 901 are sequentially disposed in the hole 201 and between the hole 201 and the hole 201, the second electrode insulating layer 801 covers the second electrode 701 and is used as a dielectric layer of the upper capacitor structure, the third electrode 901 is disposed on the second electrode insulating layer 801 and is used as a plate of the upper capacitor structure, and the first electrode insulating layer 601, the second electrode insulating layer 801 and the second electrode 701 on the surface of the buffer layer 2 are exposed to the first electrode 301 below. The second electrode insulating layer 801 realizes isolation between the second electrode 701 and the third electrode 901 in the upper capacitance structure, thereby avoiding electrical connection between the second electrode 701 and the third electrode 901. The second electrode 701, the second electrode insulating layer 801, and the third electrode 901 constitute a lower-layer capacitance structure. Because the second electrode 701 and the third electrode 901 on two sides of the inner wall of the hole are grid-shaped planes, the area of metal can be greatly increased, and a larger capacitance value can be realized. The first electrode 301 and the third electrode 901 on the surface of the buffer layer 2 are connected to realize parallel connection of the upper and lower capacitor structures, referring to fig. 8, according to the parallel capacitance formula C and = c1+c2 (C1, C2 are upper and lower capacitor structures), the actual occupied area of the grid capacitor can be further reduced by 50% compared with the theoretical capacitance area of the flat plate.

Referring to fig. 6, a thin film field effect semiconductor is disposed on the buffer layer 2 outside the hole 201, and the thin film field effect semiconductor includes a first metal 302 disposed on the buffer layer 2 outside the hole 201, wherein the first metal 302 is indium tin oxide, and a gate scan line 401 is disposed on the first metal 302, and the gate scan line 401 is one or more of metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and other alloys.

A gate insulating layer 602 is disposed on the gate scan line 401, and the gate insulating layer 602 covers and encapsulates the gate scan line 401 and the first metal 302, and the gate insulating layer 602 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like.

A second metal 702 is provided on the gate insulating layer 602, the second metal 702 being a metal oxide such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), IGZTO, or the like, and a barrier layer 802 is provided on the second metal 702, the second metal 702 being on the gate insulating layer 602 and functioning as an active layer of a thin film field effect transistor. In some embodiments, the barrier layer may not be provided, and the structure is as shown in fig. 5.

The third metal 902 is disposed on the barrier layer 802, the third metal 902 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), IGZTO, etc., the third metal 903 wraps the second metal 702 and both sides of the barrier layer 802, the third metal 902 exposes a center portion of the barrier layer 802, a source signal line 1001 is disposed on one side of the third metal 902, a drain electrode 1002 is disposed on the other side of the third metal 903, the source signal line 1001 and the drain electrode 1002 are metal oxides such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), IGZTO, etc., and the source signal line 1001 and the drain electrode 1002 have a gap, as shown in fig. 6.

In order to realize the protection of the capacitor structure and avoid the direct contact between the external structure and the capacitor structure and the thin film field effect transistor, a passivation layer 1100 is arranged on the capacitor region and the thin film field effect transistor, and the passivation layer 1100 is made of materials such as silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), titanium oxide, aluminum oxide and the like. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, the third electrode 901, and the like, and after the covering, only the passivation layer 1100 is contacted from the outside, and the capacitor structure and the thin film field effect transistor are not contacted.

It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.

Claims

1. The manufacturing method of the array substrate with the high-capacitance structure is characterized by comprising the following steps of:

Manufacturing a buffer layer on an array substrate;

making holes in the buffer layer;

2. The method for manufacturing an array substrate with a high capacitance structure according to claim 1, further comprising the steps of:

3. The method for manufacturing an array substrate with a high capacitance structure according to claim 2, wherein the manufacturing steps of the thin film field effect transistor are as follows:

4. The method for manufacturing an array substrate with a high-capacitance structure according to claim 3, further comprising the steps of, after depositing the first metal layer, continuing to deposit the gate metal:

5. The method for manufacturing an array substrate with a high-capacitance structure according to claim 3, further comprising the steps of, after covering the first insulating layer, continuing to deposit the second metal layer:

Coating a photoresist on the second metal layer, and patterning the photoresist by using a half-tone mask plate with a semi-transparent area, a full-transparent area and a full-shading area, wherein the semi-transparent area corresponds to an incomplete development area after the photoresist is developed, the full-transparent area or the full-shading area corresponds to a complete development area, the incomplete development area corresponds to the area of the second electrode in the capacitor structure, and the complete development area corresponds to the area of the second metal layer;

6. The method for manufacturing an array substrate with a high capacitance structure according to claim 1,2 or 3, further comprising the steps of:

7. The method for manufacturing an array substrate with a high-capacitance structure according to claim 1,2 or 3, wherein the material of the first layer of metal is indium tin oxide.

8. An array substrate having a high capacitance structure, wherein the array substrate having a high capacitance structure is manufactured by the manufacturing method of any one of claims 1 to 7.

9. An array substrate with a high capacitance structure, comprising:

10. The array substrate with high capacitance structure according to claim 9, wherein the thin film field effect transistor comprises: