CN110867438A - Power semiconductor module substrate - Google Patents

Abstract

The invention discloses a power semiconductor module substrate. The power semiconductor module substrate includes: the semiconductor device includes a first power metallization, a second power metallization, a third power metallization, a fourth power metallization, and an auxiliary metallization formed between the first power metallization and the second power metallization and between the third power metallization and the fourth power metallization, a gate signal terminal being formed on the auxiliary metallization, the auxiliary metallization extending in an arrangement direction of the transistor chips and the diode chips at least to a position facing a control electrode of the transistor chip located at an outermost edge in the arrangement direction. According to the invention, the stray inductance and the unevenness degree of the parallel chips can be reduced through reasonable arrangement of the driving loop.

Description

Power semiconductor module substrate

technical field

The present invention relates to a power semiconductor module substrate.

Background technique

In power semiconductor chips, transistor chips are usually used. For a transistor chip with a control terminal, the schematic diagram of the internal drive circuit of the power module is shown in Figure 3. Among them, Cg1, Cg2, and Cg3 represent the gate capacitances of three transistor chips connected in parallel, respectively, and the current capacity of the chips is determined by the voltage on the gate capacitors. Tg and Te are ports for connecting the power semiconductor module to an external driving circuit, and are used for receiving driving signals. Rg0 and Lg0 are the stray resistance and stray inductance of the common part of the chip drive circuit, respectively. Rg1, Lg1 and Rg2, Lg2 and Rg3, Lg3 are the separate stray resistance and stray inductance caused by the positional distribution of the three transistor chips, respectively. During the turn-on process of the power semiconductor module, the driving voltage applied to Tg and Te rises from a specific negative value to a positive value, causing the voltage across the gate capacitor to rise, so that the current through the power terminal of the transistor rises and the transistor turns on; the power semiconductor During the turn-off process of the module, the driving voltage applied to Tg and Te decreases from a specific positive value to a negative value, which causes the voltage across the gate capacitor to drop, so that the current through the power terminal of the transistor drops and the transistor turns off.

If the stray inductance value in the module drive circuit is large, it is easy to cause voltage oscillation between the stray inductance and the gate capacitance of the chip during the switching process of the module. The threshold voltage may cause the chip to be turned off by mistake; if the voltage across the gate capacitor is higher than the threshold voltage that turns the chip off due to oscillation during the turn-off process, it may cause the chip to be turned on by mistake. The above two situations are not conducive to the reliable operation of the power semiconductor module. The gate capacitance is determined by the chip itself. When designing the power module, the stray inductance of the drive loop should be minimized to reduce the risk of false turn-on and false turn-off at high switching speeds.

If the stray parameters of the parallel chips are inconsistent, the charging and discharging speeds of the gate capacitors will be inconsistent during the switching process. As a result, the power current passing through the chip during the switching process is uneven, resulting in the inconsistency of losses on the parallel chips, which is finally reflected in the temperature difference of the chips. When the power module works at full power, the over-temperature and over-current caused by the uneven current distribution of the chip may cause the failure of the semiconductor components, affecting the reliability and output power of the module.

Therefore, it becomes more and more urgent to reduce the stray inductance and unevenness of the parallel chips through a reasonable drive circuit arrangement.

SUMMARY OF THE INVENTION

One object of the present invention is to overcome the defects of the prior art, and to provide a power semiconductor module substrate that realizes low stray inductance of a power module driving circuit and a balanced stray inductance between different chips.

In order to achieve the above purpose, the present invention proposes the following technical solutions: a power semiconductor module substrate, comprising:

a first power metal coating, on which N transistor chips and N diode chips belonging to the first bridge arm switch are arranged in parallel in two rows, and N is a positive integer;

a second power metal coating, on which a first emitter signal terminal is formed;

a third power metal coating, on which N transistor chips and N diode chips belonging to the second bridge arm switch are arranged in parallel in two rows;

a fourth power metal coating on which a second emitter signal terminal is formed; and

Auxiliary metal coating, the auxiliary metal coating is formed between the first power metal coating and the second power metal coating and between the third power metal coating and the fourth power metal coating, in the auxiliary metal coating are formed with gate signal terminals,

The auxiliary metal coating extends in the arrangement direction of the transistor chips and the diode chips, at least to a position directly opposite to the control electrodes of the transistor chips located at the most edge in the arrangement direction.

Preferably, the distance between the diode chip and the gate signal terminal is greater than the distance between the transistor chip and the gate signal terminal.

Preferably, the power electrodes on the upper surfaces of the transistor chips and the diode chips are connected to each other and the power electrodes on the upper surfaces of the transistor chips and the diode chips are connected to other power metal layers by connecting means.

Preferably, the connecting device is a binding wire.

Preferably, the auxiliary metallization layer is insulated from other power metallization layers.

Preferably, both the first emitter signal terminal and the second emitter signal terminal are close to the gate signal terminal.

According to the power semiconductor module substrate provided by the present invention, the stray inductance and unevenness of the parallel chips can be reduced through reasonable driving loop arrangement.

Description of drawings

FIG. 1 is a top view of a power semiconductor module substrate of the present invention.

FIG. 2 is a schematic diagram of the switch part of the bridge arm in FIG. 1 .

FIG. 3 is a schematic diagram of an internal drive circuit of a power module in the prior art.

Detailed ways

The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.

A first embodiment of the present invention is a power semiconductor module substrate. As shown in FIG. 1 , the power semiconductor module substrate includes: a first power metal coating, a second power metal coating, a third power metal coating, a fourth power metal coating, and an auxiliary metal coating.

Since the current capacity of a single power semiconductor chip is limited, in order to expand the power processing capacity of the power semiconductor module, a multi-chip parallel connection is used inside the large-capacity power semiconductor module of the present invention to form a bridge arm switch.

As shown in Figure 2, in each bridge arm switch, in order to achieve bidirectional flow of current or reduce losses, the paralleled chips usually use transistor chips whose switching states can be controlled by control electrodes and diode chips with unidirectional conduction capability. The transistor chip and the diode chip are connected in parallel at their power electrodes. In Figures 1 and 2, three transistor chips and three diode chips are shown in each arm switch. However, the present invention is not limited to this, and other numbers of transistor chips and diode chips are also possible.

The semiconductor chips belonging to the same bridge arm switch are arranged on the first power metal coating, thereby forming a first power potential region on the first power metal coating, three transistor chips and three diodes belonging to the first bridge arm switch The chips are arranged in parallel in two rows as shown. The transistor chip array is in close proximity to the gate control terminal on the auxiliary metallization, and the diode chip array is away from the gate control terminal. Although in the present invention, the distance between the diode chip and the gate signal terminal is larger than the distance between the transistor chip and the gate signal terminal, it is not limited to this, and other suitable arrangements may be used.

The power electrodes on the upper surfaces of the transistor and the diode are connected to each other and other power metal layers (second and third power metal layers) through connecting means. The connection device may be, for example, a binding wire, but is not limited thereto, and may be other various connection components. The second metal cladding layer, the third metal cladding layer, the first metal cladding layer and the second metal cladding layer are insulated from each other, and the power electrodes on the upper surface of the chip, the connecting device, the second metal cladding layer and the third metal cladding layer form the second power potential area.

The semiconductor chips belonging to the same bridge arm switch are arranged on the third power metal coating, and the three transistor chips and the three diode chips belonging to the second bridge arm switch are arranged in parallel in two rows as shown in the figure.

The gate control terminal of the power module is arranged on the auxiliary metal cladding layer, and the auxiliary metal cladding layer and the other power metal cladding layers are insulated from each other to form an auxiliary potential area.

The auxiliary metal coating extends along the chip edge along the arrangement direction of a row of chips close to the signal terminals, that is, the arrangement direction of the transistor chips and the diode chips (horizontal direction in Figure 1), at least to the position with the shortest distance from the chip control electrodes ( facing position), the landing positions of the control electrode connecting device are all facing the position. As shown in Figure 1, an auxiliary metal coating is formed between the first power metal coating and the second power metal coating, and an auxiliary metal coating is formed between the third power metal coating and the fourth power metal coating .

The first emitter signal terminal of the power module is located on the second power metallization layer and as close as possible to the gate signal terminal. The second emitter signal terminal of the power module is located on the fourth power metallization layer and as close as possible to the gate signal terminal.

As described above, with the power semiconductor module substrate of the first embodiment, since the auxiliary metal layer where the gate control terminal is located extends along the arrangement direction of the transistor chip array, and at least extends to the position with the shortest distance to the control electrode of the transistor chip, that is, It has a balanced gate path, so it can reduce the stray inductance of the internal drive circuit of the power semiconductor module, reduce the unbalanced degree of the stray parameters of the drive circuit of the parallel power semiconductor chip, thereby reducing the error of the power semiconductor module during high-speed switching. The triggering risk improves the operational reliability of the module, and increases the output power of the power semiconductor module due to the power current between the parallel chips in the process of equalizing the switching.

It should be noted that each unit mentioned in each device embodiment of the present invention is a logical unit. Physically, a logical unit may be a physical unit, a part of a physical unit, or a plurality of physical units. The combination of units is implemented, the physical implementation of these logical units is not the most important, and the combination of functions implemented by these logical units is the key to solving the technical problem proposed by the present invention. In addition, in order to highlight the innovative part of the present invention, the above-mentioned device embodiments of the present invention do not introduce units that are not very closely related to solving the technical problems proposed by the present invention, which does not mean that there are no other device embodiments in the above-mentioned device embodiments. unit.

It should be noted that, in the claims and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or Any such actual relationship or order between these entities or operations is implied. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a" does not preclude the presence of additional identical elements in a process, method, article, or device that includes the element.

Although the present invention has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the invention The spirit and scope of the invention.

Claims (7)

1. A power semiconductor module substrate, comprising:

a first power metal coating on which N transistor chips and N diode chips belonging to a first bridge arm switch are arranged in parallel in two rows, N being a positive integer;

a second power metallization on which a first emitter signal terminal is formed;

a third power metal coating on which N transistor chips and N diode chips belonging to the second bridge arm switch are arranged in parallel in two rows;

a fourth power metallization on which a second emitter signal terminal is formed; and

an auxiliary metallization formed between the first power metallization and the second power metallization and between the third power metallization and the fourth power metallization, a gate signal terminal being formed on the auxiliary metallization,

the auxiliary metal coating extends in the arrangement direction of the transistor chips and the diode chips at least to a position facing the control electrode of the transistor chip located at the outermost edge in the arrangement direction.

2. The power semiconductor module substrate of claim 1,

the distance between the diode chip and the grid signal terminal is larger than the distance between the transistor chip and the grid signal terminal.

3. The power semiconductor module substrate of claim 1,

the power electrodes on the upper surfaces of the transistor chip and the diode chip are connected to one another and to further power metals by means of connecting devices.

4. A power semiconductor module substrate according to claim 3, characterized in that the connection means are binding wires.

5. The power semiconductor module substrate of claim 1, wherein the auxiliary metallization layer is insulated from other power metallization layers.

6. The power semiconductor module substrate of claim 1, wherein the first emitter signal terminal and the second emitter signal terminal are both proximate to the gate signal terminal.

7. The power semiconductor module substrate of claim 1, wherein N is 3.

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