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CN110858574A - Packaging structure of ultra-thin chip - Google Patents

Packaging structure of ultra-thin chip Download PDF

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Publication number
CN110858574A
CN110858574A CN201810961402.6A CN201810961402A CN110858574A CN 110858574 A CN110858574 A CN 110858574A CN 201810961402 A CN201810961402 A CN 201810961402A CN 110858574 A CN110858574 A CN 110858574A
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CN
China
Prior art keywords
chip
gasket
pad
electrically connected
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810961402.6A
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Chinese (zh)
Inventor
敖利波
曹俊
江伟
史波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gree Electric Appliances Inc of Zhuhai
Original Assignee
Gree Electric Appliances Inc of Zhuhai
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Publication date
Application filed by Gree Electric Appliances Inc of Zhuhai filed Critical Gree Electric Appliances Inc of Zhuhai
Priority to CN201810961402.6A priority Critical patent/CN110858574A/en
Publication of CN110858574A publication Critical patent/CN110858574A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention discloses a packaging structure of an ultrathin chip, which is used for solving the problem that an IGBT chip is warped due to large thermal expansion coefficient of a base in the prior art, so that a device is invalid. According to the packaging structure of the ultrathin chip, the chip seat of the lead frame is provided with the chip groove with the preset shape and size, the first gasket with the thermal expansion coefficient smaller than that of the chip seat is assembled in the chip groove, the chip is welded on the first gasket, and the first gasket is electrically connected with the chip. Therefore, the human expansion coefficient of the first gasket is smaller than that of the lead frame, the packaging stress of the chip and the first gasket is matched, when the temperature changes, the warpage of the first gasket is smaller than that of the lead frame, and further the warpage of the chip arranged on the first gasket is reduced, so that the damage of crystal cells inside the chip caused by the unmatched packaging stress is small, the possibility of the damage is low, and the yield and the reliability of the device packaging structure are improved.

Description

Packaging structure of ultra-thin chip
Technical Field
The invention relates to the technical field of wireless communication, in particular to a packaging structure of an ultrathin chip.
Background
With the continuous development of chip manufacturing technology, the thickness of an Insulated Gate Bipolar Transistor (IGBT) chip is continuously reduced, and the mechanical strength of the chip is gradually poor; the chip is directly welded on the copper frame through the bonding material in the traditional packaging structure, and the packaging stress can be mismatched due to the large thermal expansion coefficient of the copper material, so that the chip is warped, the crystal cell inside the chip is damaged or the energy band is bent due to the warping of the chip, and finally the device fails.
In summary, the conventional IGBT chip is warped due to the large thermal expansion coefficient of the base, and the device fails.
Disclosure of Invention
The invention provides a packaging structure of an ultrathin chip, which is used for solving the problem that in the prior art, an IGBT chip is warped due to large thermal expansion coefficient of a base, so that a device is invalid.
The embodiment of the invention provides a packaging structure of an ultrathin chip, which comprises a chip and a lead frame for bearing the chip, wherein the lead frame comprises a chip seat; a first gasket with a thermal expansion coefficient smaller than that of the chip seat is assembled in a chip groove arranged on the chip seat; the chip is arranged on the first gasket in the chip groove, wherein the chip is electrically connected with the first gasket in the chip groove.
According to the packaging structure of the ultrathin chip, the chip seat of the lead frame is provided with the chip groove with the preset shape and size, the first gasket with the thermal expansion coefficient smaller than that of the chip seat is assembled in the chip groove, the chip is welded on the first gasket, and the first gasket is electrically connected with the chip. Therefore, the human expansion coefficient of the first gasket is smaller than that of the lead frame, the packaging stress of the chip and the first gasket is matched, when the temperature changes, the warpage of the first gasket is smaller than that of the lead frame, and further the warpage of the chip arranged on the first gasket is reduced, so that the damage of crystal cells inside the chip caused by the unmatched packaging stress is small, the possibility of the damage is low, and the yield and the reliability of the device packaging structure are improved.
In one possible embodiment, the first pad may be disposed in a chip groove on the chip carrier by interference fit, solder paste welding or resistance welding.
According to the packaging structure, the first gasket is arranged on the chip groove with the preset shape and size formed in the chip seat of the lead frame in an interference fit, solder paste welding and resistance welding mode so as to bear a chip, and packaging stress which is more matched with the chip in a mode of directly welding the chip on the chip seat is provided, so that the failure rate of a device of the packaging structure is reduced.
In one possible embodiment, the chip is electrically connected to the first pad in the chip slot by soldering a core wire or a bonding material.
In the device, the chip is electrically connected with the first gasket in the chip groove by welding the welding core wire or the bonding material, so that a bridge circuit can be realized, and heat generated by the chip is taken away when the chip works.
In one possible embodiment, wherein the first gasket is made of a copper-molybdenum alloy material.
In the above package structure, the copper-molybdenum alloy has a thermal expansion coefficient smaller than that of the chip holder, and at the same time, has good electrical conductivity and good thermal conductivity, and can be used as a preferred material in the embodiment of the present invention.
In a possible embodiment, a side of the chip facing away from the chip carrier is provided with a second spacer, wherein the chip is electrically connected to the second spacer on the side of the chip facing away from the chip carrier.
In the packaging structure, a second gasket can be arranged on one side of the chip, which is far away from the chip seat, of the chip, and the emitter welding point of the chip is electrically connected with the second gasket arranged on one side of the chip, which is far away from the chip seat, so that the emitter pin and the second gasket which are arranged on the chip seat in parallel with the grid pin can be bonded and connected through an aluminum lead, and the electric connection between the chip and the emitter pin is achieved. Due to the arrangement of the second gasket, the aluminum wires for bonding the chip and the emitter pin are not directly welded on the chip but bonded on the second gasket, so that the bonding pressure is uniformly distributed, the chip damage is reduced, and the yield and the reliability of the device packaging structure are improved.
In one possible embodiment, the second spacer on the side of the chip facing away from the chip carrier has a coefficient of thermal expansion which is smaller than the coefficient of thermal expansion of the chip carrier.
In the packaging structure, the thermal expansion coefficient of the second gasket on the side of the chip, which is far away from the chip seat, is smaller than that of the chip seat, so that the packaging stress between the second gasket and the chip is matched, when the temperature changes, the warping of the second gasket is smaller, and the warping of the chip, which is electrically connected with the second gasket and is arranged on the first gasket, is also smaller, thereby reducing the damage of crystal cells in the chip caused by the mismatching of the packaging stress, and improving the yield and the reliability of the device packaging structure.
In a possible embodiment, the chip is electrically connected to the second pads on the side of the chip facing away from the chip carrier by means of solder bumps or bonding material.
In the packaging structure, the chip and the second gasket positioned on one side of the chip, which is far away from the chip seat, are electrically connected through welding a welding core or a bonding material.
In a possible embodiment, the package structure further includes an emitter pin having one end soldered to the second pad by soldering an aluminum wire.
In the packaging structure, the second gasket is electrically connected with the emitter pin through the welding aluminum wire.
In one possible embodiment, the second gasket is made of a copper-molybdenum alloy material.
In the packaging structure, the copper-molybdenum alloy is used as a second gasket and is electrically connected with the emitter pin through the aluminum wire, and due to the arrangement of the copper-molybdenum alloy gasket, the aluminum wires for bonding the chip and the emitter pin are not directly welded on the chip, so that the bonding pressure is uniformly distributed, the chip damage is reduced, the yield and the reliability of the packaging structure of the device are improved, and meanwhile, due to the small thermal expansion coefficient of the copper-molybdenum alloy, the warping caused by temperature change is relatively small, the damage of a crystal cell in the chip is reduced, the yield and the reliability of the packaging structure of the device are improved, and meanwhile, the packaging structure of the device has good electrical conductivity and good thermal conductivity and is an optimal material in the embodiment of the invention.
In one possible implementation mode, a gate bonding pad is arranged on the chip, and the gate bonding pad is electrically connected with the gate pin through a welding aluminum wire.
In the packaging structure, the chip is electrically connected with the grid pin through the aluminum wire connected to the grid bonding pad, and further electrically connected with an external circuit through the grid pin.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural view of an ultra-thin chip package structure provided in an embodiment of the present invention after chips are arranged;
fig. 2 is a schematic structural diagram of an ultra-thin chip package structure provided in an embodiment of the present invention after a second gasket is arranged;
fig. 3 is a schematic structural diagram of an ultra-thin chip package structure provided in an embodiment of the present invention after aluminum wire bonding is completed;
fig. 4 is a schematic diagram of plastic package after electrical connection of chips in the ultra-thin chip package structure provided in the embodiment of the present invention is completed;
fig. 5 is a schematic diagram of the ultra-thin chip package structure according to the embodiment of the present invention after the chip is electrically connected and then plastic package is completed;
fig. 6 is a schematic diagram of a packaged chip in the ultra-thin chip packaging structure according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a package structure of an ultra-thin chip, which includes a chip 1 and a lead frame 2 for carrying the chip 1, wherein the lead frame includes a chip pad 21; a first gasket 22 with a thermal expansion coefficient smaller than that of the chip seat 21 is assembled in a chip groove 210 arranged on the chip seat 21; the chip 1 is disposed on the first pad 22 in the chip slot 210, wherein the chip 1 is electrically connected to the first pad 22 in the chip slot 210.
In the packaging structure of the ultrathin chip 1, the chip seat 21 of the lead frame is provided with the chip groove 210 with the preset shape and size, the first gasket 22 with the thermal expansion coefficient smaller than that of the chip seat 21 is assembled in the chip groove 210, the chip 1 is welded on the first gasket 22, and the first gasket 22 is electrically connected with the chip 1. Thus, since the coefficient of human expansion of the first pad 22 is smaller than that of the lead frame 2, the package stress of the chip 1 is matched with that of the first pad 22, and when the temperature changes, the warpage of the first pad 22 is smaller than that of the lead frame, and further the warpage of the chip 1 disposed on the first pad 22 is also reduced, so that the damage of the crystal cell inside the chip 1 due to the unmatched package stress is reduced, and the yield and reliability of the device package structure are improved.
Wherein a collector pad 11 and a gate pad 12 are provided on the chip for making electrical connection with gate lead 27 and emitter lead 25, respectively.
Alternatively, the first pad 22 may be disposed in the chip slot 210 of the chip carrier 21 by interference fit, solder paste welding or resistance welding.
In the above package structure, the first pad 22 is disposed on the chip slot 210 with a predetermined shape and size formed on the chip seat 21 of the lead frame in an interference fit, solder paste welding or resistance welding manner, so as to bear the chip 1, and provide a package stress more matched with that of the prior art in which the chip 1 is directly welded on the chip seat 21, thereby reducing the failure rate of the packaged device.
For example:
1. the first spacer 22 may be disposed in the chip slot 210 of the chip carrier 21 by interference fit.
When the first pad 22 is disposed in the chip groove 210 of the chip carrier 21 by interference fit, the cotter of the first pad 22 for being inserted into the chip groove 210 is slightly larger than the size of the chip groove 210, and then is forcibly pressed into the chip groove 210 by mechanical means, thus completing the arrangement of the first pad 22.
2. The first pads 22 may be disposed in the chip slots 210 of the chip base 21 by solder paste.
When the first pads 22 are disposed in the chip grooves 210 of the die pad 21 by solder paste soldering, solder paste for soldering the first chip 1 needs to be first placed in the chip grooves 210, then the first pads 22 are placed on the solder material, and then soldering is performed to complete the configuration of the first pads 22.
3. The first pad 22 may be resistance welded to the chip holder 21 in the chip groove 210.
When the first gasket 22 is disposed in the chip groove 210 of the chip carrier 21 by resistance welding, firstly, the contact surfaces between the electrodes and the first gasket 22 and between the first gasket 22 and the bottom of the chip groove 210 need to be cleaned; pressure needs to be applied to the first gasket 22 during the whole welding process, so that the first gasket 22 can fit the bottom of the chip groove 210, and electric arcs are prevented from occurring on the contact surfaces; the connection is achieved by melting the contact surface between the first pad 22 and the bottom of the chip pocket 210 under the pressure of a certain electrode and using resistance heat generated when current passes through the first pad 22.
Optionally, the chip 1 and the first pad 22 in the chip slot 210 are electrically connected by soldering a core wire or a bonding material.
In the above device, the chip 1 and the first pad 22 in the chip slot 210 are electrically connected by soldering a core wire or a bonding material, so that a bridge circuit can be realized and heat generated by the power chip 1 can be taken away when the power chip 1 operates.
Optionally, wherein the first gasket 22 is a first gasket 22 made of a copper-molybdenum alloy material.
In the above package structure, the copper-molybdenum alloy has a thermal expansion coefficient smaller than that of the chip carrier 21, and at the same time, has good electrical conductivity and good thermal conductivity, and can be used as a preferred material in the embodiment of the present invention.
In the prior art, the chip is electrically connected to the emitter pin by directly soldering an aluminum wire to a collector pad of the chip, which may cause mechanical damage if the chip is directly impacted by bonding pressure of the aluminum wire.
In order to solve the above problem, an embodiment of the present invention further provides a package structure of an ultra-thin chip to reduce chip damage, which is shown in fig. 2.
Optionally, a second pad 23 is disposed on a side of the chip 1 facing away from the chip carrier 21, wherein the chip 1 is electrically connected to the second pad 23 on the side of the chip 1 facing away from the chip carrier 21.
In the above package structure, a second pad 23 may be further disposed on a side of the chip 1 away from the chip base 21, and an emitter bonding pad of the chip 1 is electrically connected to the second pad 23 disposed on the side of the chip 1 away from the chip base 21, so that an electrical connection between the chip 1 and an emitter lead 23 can be achieved by using an emitter lead 25 and a second pad 23, which are connected to the chip base 21 in parallel with the gate lead 27, and connected by aluminum wire bonding. Due to the arrangement of the second gasket 23, the emitter aluminum wires 24 of the bonding chip 1 and the emitter lead 25 are not directly welded on the chip 1 but bonded on the second gasket 23, so that the bonding pressure is uniformly distributed, the damage of the chip 1 is reduced, and the packaging yield and reliability of the device are improved.
When the chip 1 and the second pad 23 are electrically connected, a core wire or a bonding material is arranged on the transmitter pad 11 of the chip 1, and the second pad 23 is soldered to the emitter pad 11 of the chip, thereby electrically connecting the chip 1 and the second pad 23.
Optionally, the second spacer 23 on the side of the chip 1 facing away from the chip carrier 21 has a thermal expansion coefficient smaller than that of the chip carrier 21.
In the packaging structure, the thermal expansion coefficient of the second gasket 23 on one side of the chip 1 departing from the chip seat 21 is smaller than that of the chip seat 21, so that the packaging stress between the second gasket 23 and the chip 1 is matched, when the temperature changes, the warpage of the second gasket 23 is smaller, and the warpage of the chip 1 electrically connected with the second gasket and arranged on the first gasket 22 is reduced, so that the damage of the crystal cell inside the chip 1 caused by the mismatching of the packaging stress is reduced, and the packaging yield and reliability of the device are improved.
Optionally, the chip 1 and the second pad 23 on the side of the chip 1 away from the chip base 21 are electrically connected by soldering a core wire or a bonding material.
In the above package structure, the chip 1 and the second pad 23 on the side of the chip 1 away from the chip base 21 are electrically connected by soldering a core wire or a bonding material.
In specific implementation, a core wire or a bonding material is directly placed on the emitter bonding pad 11 of the chip 1, and then the second chip 1 is placed on the core wire or the bonding material and directly welded, so that the chip 1 and the second pad 23 can be electrically connected.
Optionally, the package structure further includes an emitter pin 25 having one end welded to the second pad 23 by an aluminum wire.
In this way, the electrical connection between the chip 1 and the emitter pin can be realized by the electrical connection between the second pad 23 and the emitter pin.
Optionally, the second gasket 23 is made of a copper-molybdenum alloy material.
In the packaging structure, the copper-molybdenum alloy is used as the second gasket 23 and is electrically connected with the emitter pin through the aluminum wire, because the copper-molybdenum alloy gasket is arranged, the aluminum wire for bonding the chip 1 and the emitter pin 25 is not directly welded on the chip 1, so that the bonding pressure is uniformly distributed, the damage of the chip 1 is reduced, the packaging yield and reliability of the device are improved, meanwhile, because the thermal expansion coefficient of the copper-molybdenum alloy is small, the warping caused by temperature change is relatively small, the damage of the crystal cell in the chip 1 is reduced, the packaging yield and reliability of the device are improved, and meanwhile, the copper-molybdenum alloy has good electrical conductivity and good thermal conductivity and is a preferred material in the embodiment of the invention.
Optionally, a gate pad 11 is disposed on the chip 1, and the gate pad 11 is electrically connected to the gate pin 25 by an aluminum wire.
In the above package structure, the chip 1 is electrically connected to the gate pin 27 through the gate aluminum wire 26 connected to the gate pad 12, and further electrically connected to an external circuit through the gate pin 27, specifically referring to fig. 1 and 3.
In specific implementation, two ends of the aluminum wire are respectively welded with the gate pad and the gate pin 27, so that the gate pad and the gate pin 27 are in point connection, and further, the chip 1 and the gate pin 27 are electrically connected, so that the chip 1 after being packaged can be electrically connected with an external circuit.
After the chip 1 can be electrically connected to the outside through the gate terminal 27, the collector terminal, and the emitter terminal 25, the epoxy resin 3 is also required to package the entire package carrying the chip 1.
In specific implementation, a mold suitable for encapsulating all the electrically connected chips 1 is needed, the electrically connected chips 1 are placed in the mold, the epoxy resin 3 for encapsulating the chips 1 is melted, the melted epoxy resin 3 is injected into the mold for placing the electrically connected chips 1 through an injection molding machine, and after the epoxy resin 3 is solidified, the mold is taken out, so that the chips 1 are completely encapsulated by the epoxy resin 3, which can be specifically seen in fig. 4 and 5.
Finally, as shown in fig. 5 and 6, the excess tie bars on the frame of the chip 1 completely encapsulated by the epoxy resin 3, and the portions of the gate lead 27, the collector lead, and the emitter lead 25 are cut off, so that the chip 1 is encapsulated.
The present application is described above with reference to block diagrams and/or flowchart illustrations of methods, apparatus (systems) and/or computer program products according to embodiments of the application. It will be understood that one block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the subject application may also be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A packaging structure of an ultrathin chip comprises a chip and a lead frame for bearing the chip, wherein the lead frame comprises a chip holder; the chip is characterized in that a first gasket with a thermal expansion coefficient smaller than that of the chip seat is assembled in a chip groove arranged on the chip seat;
the chip is arranged on the first gasket in the chip groove, wherein the chip is electrically connected with the first gasket in the chip groove.
2. The package structure of claim 1, wherein the first pads are disposed in the chip slots on the chip carrier by interference fit, solder paste bonding, or resistance welding.
3. The package structure of claim 1, wherein the chip is electrically connected to the first pad in the chip slot by a solder core or a bonding material.
4. The package structure of claim 3, wherein the first spacer is made of a copper-molybdenum alloy material.
5. The package structure of claim 1, wherein a side of the chip facing away from the chip carrier is provided with a second pad, wherein the chip is electrically connected to the second pad on the side of the chip facing away from the chip carrier.
6. The package structure of claim 5, wherein the second spacer on a side of the chip facing away from the chip carrier has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the chip carrier.
7. The package structure of claim 5, wherein the chip is electrically connected to the second pad on a side of the chip facing away from the chip carrier by a solder core or a bonding material.
8. The package structure of claim 6, further comprising an emitter lead having one end bonded to the second pad by a bonded aluminum wire.
9. The package structure of claim 7, wherein the second gasket is made of a copper-molybdenum alloy material.
10. The package structure of claim 1, wherein a gate pad is disposed on the chip and electrically connected to the gate lead by a solder aluminum wire.
CN201810961402.6A 2018-08-22 2018-08-22 Packaging structure of ultra-thin chip Pending CN110858574A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262720A1 (en) * 2003-06-30 2004-12-30 Renesas Technology Corp. Semiconductor device
CN101226903A (en) * 2007-01-15 2008-07-23 罗姆股份有限公司 Semiconductor device
CN205960972U (en) * 2016-08-26 2017-02-15 江苏扬杰半导体有限公司 Low thermal resistance H bridge

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262720A1 (en) * 2003-06-30 2004-12-30 Renesas Technology Corp. Semiconductor device
CN101226903A (en) * 2007-01-15 2008-07-23 罗姆股份有限公司 Semiconductor device
CN205960972U (en) * 2016-08-26 2017-02-15 江苏扬杰半导体有限公司 Low thermal resistance H bridge

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Application publication date: 20200303