CN110854179B - A radiation-hardened silicon-based bipolar transistor structure and preparation method based on self-built electric field - Google Patents

Abstract

The invention discloses a radiation-reinforced silicon-based bipolar transistor structure based on a self-built electric field and a preparation method thereof, wherein the structure is formed by multilayer wiring: a ground potential layer communicated with the lowest potential is formed on the surface of the transistor through a multilayer wiring process, so that a self-built electric field pointing to the ground potential layer is formed in the silicon dioxide insulating layer between each doped region of the transistor and the ground potential layer. The self-built electric field inhibits positive charges generated by total dose radiation in the silicon dioxide insulating layer from moving to the silicon-silicon dioxide interface, so that the number of positive charges which are induced by the radiation and reach the silicon-silicon dioxide interface and form new interface states is reduced, and the total dose radiation resistance of the bipolar transistor is improved.

Description

A radiation-hardened silicon-based bipolar transistor structure and preparation method based on self-built electric field

technical field

The invention belongs to the technical field of silicon-based transistors, and in particular relates to a radiation-hardened silicon-based bipolar transistor structure and a preparation method based on a self-built electric field.

Background technique

Conventional silicon-based bipolar transistors include NPN transistors and PNP transistors. Their structures are selectively doped with P-type or N-type impurities in different regions of the silicon substrate or epitaxial layer to form NPN or PNP structures, and are realized by wires. The final transistor structure also needs to cover a layer of silicon dioxide on the surface of the transistor as an insulating layer between the metal lead and the doped region of the transistor to avoid short circuits between different doped regions of the transistor through metal connections.

When the silicon-based bipolar transistor is irradiated with the total dose, the radiation ionization effect will cause a large amount of radiation-induced positive charges to be generated in the silicon dioxide insulating layer on the surface of the transistor. When these positive charges move to the silicon-silicon dioxide interface, It will react with the dangling bonds at the interface to generate a new interface state, increase the recombination center on the surface of the transistor base, increase the recombination current of the transistor, and decrease the gain, which will cause the transistor to fail under the action of total dose radiation.

Contents of the invention

The invention provides a radiation-hardened silicon-based bipolar transistor structure and a preparation method based on a self-built electric field. The novel structure can effectively improve the total dose radiation resistance of the transistor.

In order to achieve the above purpose, a radiation-hardened silicon-based bipolar transistor structure based on a self-built electric field according to the present invention includes a bipolar transistor body, an insulating layer, a ground potential layer, an insulating dielectric layer and circuit wiring arranged in sequence from bottom to top An interconnection layer; wherein, the main body of the bipolar transistor is a doped silicon wafer; the insulating layer covers the upper surface of the main body of the bipolar transistor, and the insulating layer is provided with a potential electrode contact window and a bipolar transistor electrode lead-out contact window , the upper surface of the insulating layer is covered with a ground potential layer, and the ground potential layer includes a ground potential electrode and a plurality of bipolar transistor lead-out electrodes; the upper surface of the ground potential layer is covered with an insulating medium layer, and the insulating medium layer is provided with The electrode lead-out contact window, the upper surface of the insulating medium layer is covered with a circuit wiring interconnection layer, and the circuit wiring interconnection layer is connected to the lead-out electrode of the bipolar transistor through the electrode lead-out contact window.

Further, the material of the ground potential layer is AlSiCu or doped polysilicon.

Further, the circuit wiring interconnection layer is formed of aluminum silicon copper.

Further, the material of the insulating layer is silicon dioxide, and the thickness is ±10%.

Further, the material of the insulating dielectric layer is silicon dioxide, and the thickness is ±10%.

A method for preparing the aforementioned radiation-hardened silicon-based bipolar transistor structure based on a self-built electric field, comprising the following steps:

Step 1. Perform selective doping of impurities in different regions on the silicon wafer to obtain the main body of the bipolar transistor, and then form an insulating layer on the main body of the bipolar transistor;

Step 2, etching on the insulating layer to form a ground potential electrode contact window and a bipolar transistor electrode lead-out contact window;

Step 3, depositing the first metal layer on the surface of the product obtained in step 2;

Step 4, etching on the first metal layer to form a ground potential layer;

Step 5, forming an intermetallic insulating dielectric layer with chemical vapor deposition on the product obtained in step 4;

Step 6, etching on the intermetallic insulating dielectric layer to form a bipolar transistor electrode lead-out contact window;

Step 7, depositing a second metal layer on the surface of the product obtained in step 6;

Step 8, etching on the second metal layer to form a circuit wiring interconnection layer.

Further, in step 3, the material of the first metal layer is AlSiCu or doped polysilicon.

Compared with the prior art, the present invention has at least the following beneficial technical effects:

Aiming at the influence mechanism of total dose radiation on silicon-based bipolar transistors, a ground potential layer connected to the lowest potential is formed on the surface of the transistor through multi-layer wiring technology, so that the connection between each doped region of the transistor and the ground potential layer A self-built electric field pointing to the ground potential layer is formed in the silicon dioxide insulating layer, which inhibits the positive charge generated in the silicon dioxide layer by the total dose of radiation from moving to the silicon-silicon dioxide interface, thereby reducing radiation-induced The number of positive charges reaching the silicon-silicon dioxide interface and forming new interface states, thereby improving the total dose radiation resistance of bipolar transistors.

Furthermore, the material of the ground potential layer is AlSiCu or doped polysilicon. AlSiCu and doped polysilicon are the most commonly used materials for the first interconnection wiring layer in the manufacturing process of silicon-based bipolar transistors. As a ground potential layer, the material can be compatible with the mature silicon-based bipolar process, reducing process cost and process difficulty.

Further, the circuit wiring interconnection layer is formed of aluminum silicon copper, aluminum silicon copper (pure aluminum, aluminum silicon, aluminum copper) is the most commonly used interconnection wiring material in the manufacturing process of silicon-based bipolar transistors, choose this aluminum silicon copper As a circuit wiring interconnection layer, it is compatible with a mature silicon-based bipolar process, reducing process cost and process difficulty.

Further, the material of the insulating layer is silicon dioxide, and the thickness is (500nm-800nm)±10%. Using silicon dioxide within this thickness range has lower process cost and process difficulty under the premise of ensuring the insulating effect.

Further, the material of the insulating medium layer is silicon dioxide, and the thickness is (500nm-800nm)±10%. Using silicon dioxide within this thickness range has lower process cost and process difficulty under the premise of ensuring the insulation effect.

A method for preparing a radiation-hardened silicon-based bipolar transistor based on a self-built electric field. The self-built electric field bipolar transistor structure is realized through a mature silicon-based transistor multilayer wiring process, which is fully compatible with the existing silicon-based transistor manufacturing process. Under the premise of device performance and reliability, it has the advantages of mature and controllable process, low cost and process difficulty.

Description of drawings

Figure 1: A longitudinal cross-sectional view of a bipolar transistor with a traditional structure;

Figure 2: Top view of a bipolar transistor with a traditional structure;

Figure 3: Longitudinal cross-sectional view of bipolar transistor with self-built electric field structure;

Figure 4: Top view of bipolar transistor with self-built electric field structure;

Figure 5: The traditional bipolar process completes the selective doping of impurities in different regions, forming a bipolar transistor structure and forming a silicon dioxide insulating layer;

Figure 6: Photoetching and etching to form ground potential electrode contacts and bipolar transistor electrode lead-out contact windows on the silicon dioxide insulating layer;

Figure 7: Deposit metal or doped polysilicon as ground potential layer and transistor lead-out electrode;

Figure 8: The ground potential layer is formed by photolithography, and the rest of the surface of the transistor is covered by the ground potential layer except for the lead-out electrode. The ground potential layer is connected to the P-type isolation area of the bipolar transistor through the contact lead-out window to ensure that the circuit works at the lowest potential;

Figure 9: Depositing a multi-layer inter-wiring silicon dioxide insulating layer;

Figure 10: photolithography to form the electrode lead-out contact window of the bipolar transistor;

Figure 11: Deposition to form interconnection metal;

Figure 12: Photolithographic etching forms metal interconnection patterns.

In the drawings: 101——N-type epitaxial layer of NPN transistor; 102——N-type epitaxial layer of PNP transistor; 2——P-type isolation region; 3——P-type silicon substrate; 41——NPN transistor P 42——P-type collector region of PNP transistor; 43——P-type emitter region of PNP transistor; 51——N-type emitter region of NPN transistor; 52——N-type extension lead-out region of NPN transistor; 6——two Silicon oxide insulating layer; 7—metal interconnection line; 8—ground potential layer; 81—ground potential electrode; 82—bipolar transistor lead-out electrode, 10—first metal layer; 11—intermetallic Insulation medium; 12—electrode lead-out contact window; 13—aluminum-silicon-copper metal layer; 14—N-type buried layer.

Detailed ways

In order to make the purpose and technical solution of the present invention clearer and easier to understand. The present invention will be further described in detail below in conjunction with the drawings and embodiments. The specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", " The orientations or positional relationships indicated by "vertical", "horizontal", "top", "bottom", "inner" and "outer" are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and Simplified descriptions, rather than indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and thus should not be construed as limiting the invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

As shown in Fig. 1 and Fig. 2, the NPN bipolar transistor of traditional structure comprises NPN transistor and PNP transistor, and NPN transistor and PNP transistor share P-type silicon substrate 3, above P-type silicon substrate 3, P-type isolation region 2 The NPN transistor and the PNP transistor are separated, and the N-type epitaxial layer 101 of the NPN transistor is provided with an NPN transistor N-type emitter region 51, an NPN transistor N-type extension lead-out region 52, and a PNP transistor P-type collector region 41; the N-type transistor of the PNP transistor A PNP transistor P-type collector region 42 and a PNP transistor P-type emitter region 43 are disposed on the epitaxial layer 102 . The uppermost end of the NPN bipolar transistor is a silicon dioxide insulating layer 6 and a metal interconnection line 7 .

Aiming at the influence mechanism of total dose radiation on silicon-based bipolar transistors, the present invention proposes a new type of bipolar transistor junction that improves the anti-total dose radiation capability of transistors through a self-built electric field, and is formed by multilayer wiring: through multilayer wiring technology A ground potential layer connected to the lowest potential is formed on the surface of the transistor, so that a self-built electric field pointing to the ground potential layer is formed in the silicon dioxide insulating layer between each doped region of the transistor and the ground potential layer. The self-built electric field suppresses the positive charges generated in the silicon dioxide insulating layer by the total dose of radiation from moving to the silicon-silicon dioxide interface, thereby reducing the possibility of radiation-induced positive charges reaching the silicon-silicon dioxide interface and forming new interface states. Quantity, thereby improving the ability of bipolar transistors to resist total dose radiation.

Example 1

A radiation-hardened silicon-based bipolar transistor structure based on a self-built electric field, including a bipolar transistor body 100, a silicon dioxide insulating layer 6, a ground potential layer 8, an insulating dielectric layer 11, and circuit wiring interconnections arranged in sequence from bottom to top Layer 7. Wherein, the body of the bipolar transistor is a doped silicon wafer. The insulating layer 6 covers the upper surface of the bipolar transistor main body 100, and the silicon dioxide insulating layer 6 is provided with a ground potential electrode contact window and a bipolar transistor electrode lead-out contact window, and the upper surface of the silicon dioxide insulating layer 6 is covered with a ground potential layer 8 , the ground potential layer 8 includes a ground potential electrode 81 and a plurality of bipolar transistor lead-out electrodes 82; the ground potential layer 8 is provided with a groove for accommodating the terminal, and the upper surface of the ground potential layer 8 is covered with an insulating medium layer 11, which is insulated An electrode extraction contact window 12 is opened on the dielectric layer 11, and the upper surface of the insulating dielectric layer 11 is covered with a circuit wiring interconnection layer 7. The circuit wiring interconnection layer 7 is connected to the bipolar transistor extraction electrode 82 through the electrode extraction contact window 12.

Wherein, the ground potential layer 8 is formed by Al-Si-Cu sputtering, with a thickness of 550nm±10%.

The metal layer 2 forms the circuit wiring interconnection layer 7; the insulating layer 6 between the ground potential layer 8 and the bipolar transistor body 100 is made of silicon dioxide, with a thickness of 800nm; the circuit wiring interconnection layer 7 and the ground potential layer 8 The material of the insulating layer is silicon dioxide with a thickness of 800nm±10%, and the material of the circuit wiring interconnection layer 7 is aluminum silicon copper with a thickness of 1.5 μm±10%.

Compared with the bipolar transistor with traditional structure, the bipolar transistor with self-built electric field structure, after 100krad (Si) total dose radiation, the attenuation of NPN transistor magnification is reduced from 41% to 27%, and the attenuation of PNP transistor magnification Reduced from 29% to 12%, the bipolar transistor with self-built electric field structure has higher anti-total dose radiation ability.

A method for preparing a radiation-hardened silicon-based bipolar transistor based on a self-built electric field, comprising the following steps:

Step 1. Referring to FIG. 5 , the selective doping of impurities in different regions is completed through a traditional bipolar process to form a bipolar transistor body 100 , and a silicon dioxide insulating layer 6 is formed on the upper surface of the bipolar transistor body 100 ;

Step 2. Referring to FIG. 6, coat a photoresist of 1.3 μm on the surface of the silicon dioxide insulating layer 6, and form a ground potential electrode contact window 15 and a bipolar transistor electrode lead-out contact window 12 through exposure, development and etching, and engrave After the etching is completed, remove the photoresist on the surface of the silicon wafer by H ₂ SO ₄ +H ₂ O ₂ solution;

Step 3. With reference to Fig. 7, by metal sputtering process, the thick first metal layer 10 of 550nm is deposited on the silicon chip surface, and the material of the first metal layer 10 is aluminum silicon copper;

Step 4. Referring to FIG. 8, coat a 2.2 μm photoresist on the upper surface of the aluminum-silicon-copper metal layer 10, and form a ground potential electrode 81 and a transistor lead-out electrode 82 through exposure, development and etching. After the metal etching is completed, pass Plasma etching and organic solvent cleaning agent solution remove the photoresist coated in this step;

Step 5. Referring to FIG. 9, an intermetallic insulating dielectric 11 is formed by plasma-enhanced chemical vapor deposition (PECVD), and the dielectric material is silicon dioxide with a thickness of 800nm;

Step 6. Referring to FIG. 10, coat a 1.3 μm photoresist on the surface of the intermetallic insulating medium 11, and form a bipolar transistor electrode lead-out contact window 12 through exposure, development, and etching. After the etching is completed, conduct plasma etching and EKC solution removes the photoresist on the surface of the silicon wafer;

Step 7. With reference to FIG. 11 , through the metal sputtering process, an aluminum-silicon-copper metal layer 13 with a thickness of 1.5 μm is deposited on the surface of the product obtained in step 6;

Step 8. Referring to Figure 12, the surface of the product obtained in step 7 is coated with 2.2m photoresist, and a metal interconnection pattern is formed through exposure, development and etching. After the metal etching is completed, it is removed by plasma etching and EKC solution Silicon wafer surface photoresist.

Example 2

A radiation-hardened silicon-based bipolar transistor structure based on a self-built electric field, including a bipolar transistor body 100, a silicon dioxide insulating layer 6, a ground potential layer 8, an insulating dielectric layer 11, and circuit wiring interconnections arranged in sequence from bottom to top Layer 7. Wherein, the body of the bipolar transistor is a doped silicon wafer. The insulating layer 6 covers the upper surface of the bipolar transistor main body 100, and the silicon dioxide insulating layer 6 is provided with a ground potential electrode contact window and a bipolar transistor electrode lead-out contact window, and the upper surface of the silicon dioxide insulating layer 6 is covered with a ground potential layer 8 , the ground potential layer 8 includes a ground potential electrode 81 and a plurality of bipolar transistor lead-out electrodes 82; the ground potential layer 8 is provided with a groove for accommodating the terminal, and the upper surface of the ground potential layer 8 is covered with an insulating medium layer 11, which is insulated An electrode extraction contact window 12 is opened on the dielectric layer 11, and the upper surface of the insulating dielectric layer 11 is covered with a circuit wiring interconnection layer 7. The circuit wiring interconnection layer 7 is connected to the bipolar transistor extraction electrode 82 through the electrode extraction contact window 12.

Among them, the ground potential layer 8 is formed of polysilicon, the doped polysilicon thickness is 200nm±10%, and the square resistance is 30Ω/□; the metal aluminum silicon copper layer forms the circuit wiring interconnection layer 7; the ground potential layer 8 and the bipolar transistor body 100 The insulating layer 6 between them is silicon dioxide, with a thickness of 500nm±10%; the material of the insulating layer between the circuit wiring interconnection layer 7 and the ground potential layer 8 is silicon dioxide, with a thickness of 500nm±10%, and the metal material is aluminum silicon Copper, thickness 1.5μm ± 10%.

Compared with the bipolar transistor with traditional structure, the bipolar transistor with self-built electric field structure, after 100krad (Si) total dose radiation, the attenuation of NPN transistor magnification is reduced from 41% to 27%, and the attenuation of PNP transistor magnification Reduced from 29% to 12%, the bipolar transistor with self-built electric field structure has higher anti-total dose radiation ability.

This structure can be realized by the following methods:

Step 1. Referring to FIG. 5, the selective doping of impurities in different regions is completed through a traditional bipolar process to form a bipolar transistor body and a silicon dioxide insulating layer 6;

Step 2. Referring to FIG. 6, coat a photoresist of 1.3 μm on the surface of the insulating layer 6, and form a ground potential electrode contact and a bipolar transistor electrode lead-out contact window through exposure, development and etching. After the etching is completed, pass _H2 SO ₄ +H ₂ O ₂ solution removes the photoresist on the surface of the insulating layer 6;

Step 3. With reference to Fig. 7, by low-pressure chemical vapor deposition (LPCVD) process, the doped polysilicon of 200nm thickness is deposited on the silicon chip surface, and the square resistance of polysilicon is 30Ω/□;

Step 4. Referring to Figure 8, coat a 1.3 μm photoresist on the surface of doped polysilicon, and form a ground potential layer and a transistor lead-out electrode through exposure, development and etching, and then conduct plasma etching and H ₂ SO ₄ +H ₂ O ₂ solution to remove the photoresist on the doped polysilicon surface;

Step 5. Referring to FIG. 9, an intermetallic insulating dielectric 11 is formed by plasma-enhanced chemical vapor deposition (PECVD), and the dielectric material is silicon dioxide with a thickness of 500nm;

Step 6. Referring to FIG. 10 , coat a 1.3 μm photoresist on the surface of the intermetallic insulating medium 11, and form a bipolar transistor electrode lead-out contact window 12 through exposure, development and etching. After the etching is completed, conduct plasma etching and H ₂ SO ₄ +H ₂ O ₂ solution to remove photoresist;

Step 7. With reference to FIG. 11 , through the metal sputtering process, an aluminum-silicon-copper metal layer 13 with a thickness of 1.5 μm is deposited on the surface of the product obtained in step 6;

Step 8. Referring to FIG. 12, coat 2.2m of photoresist on the surface of the aluminum-silicon-copper metal layer 13, and form a metal interconnection pattern through exposure, development and etching. After the metal etching is completed, plasma etching and EKC The solution removes the photoresist on the surface of the silicon wafer.

The new self-built electric field structure bipolar transistor and the traditional structure bipolar transistor carried out the total dose radiation test evaluation respectively: after 100krad (Si) total dose radiation, the new self-built electric field structure NPN transistor magnification decays 27.13%, LPNP The transistor magnification attenuation is 12.90%; the traditional structure NPN transistor magnification attenuation is 41.78%, and the LPNP transistor magnification attenuation is 29.68%. The total dose radiation resistance of the new structure transistor is higher than that of the traditional structure bipolar transistor.

The above content is only to illustrate the technical ideas of the present invention, and cannot limit the protection scope of the present invention. Any changes made on the basis of the technical solutions according to the technical ideas proposed in the present invention shall fall within the scope of the claims of the present invention. within the scope of protection.

Claims (7)

1. The radiation-reinforced silicon-based bipolar transistor structure based on the self-built electric field is characterized by comprising a bipolar transistor main body (100), an insulating layer (6), a ground potential layer (8), an insulating medium layer (11) and a circuit wiring interconnection layer (7) which are sequentially arranged from bottom to top; the bipolar transistor comprises an insulating layer (6), a ground potential layer (8) and a plurality of bipolar transistor extraction electrodes (82), wherein the insulating layer (6) covers the upper surface of a bipolar transistor main body (100), a potential electrode contact window and a bipolar transistor electrode extraction contact window are formed in the insulating layer (6), the upper surface of the insulating layer (6) is covered with the ground potential layer (8), and the ground potential layer (8) comprises a ground potential electrode (81) and a plurality of bipolar transistor extraction electrodes (82); the ground potential layer (8) upper surface covers has insulating medium layer (11), electrode extraction contact window (12) have been seted up on insulating medium layer (11), insulating medium layer (11) upper surface covers has circuit wiring interconnect layer (7), circuit wiring interconnect layer (7) are connected through electrode extraction contact window (12) and bipolar transistor extraction electrode (82).

2. A radiation-hardened silicon-based bipolar transistor structure according to claim 1, characterized in that the material of the ground potential layer (8) is aluminum-silicon-copper or doped polysilicon.

3. A radiation-hardened silicon-based bipolar transistor structure according to claim 1, wherein the circuit wiring interconnect layer (7) is formed of aluminum silicon copper.

4. The self-built electric field-based radiation-hardened silicon-based bipolar transistor structure according to claim 1, wherein the insulating layer (6) is silicon dioxide with a thickness of (500 nm-800 nm) ± 10%.

5. The self-built electric field-based radiation-reinforced silicon-based bipolar transistor structure according to claim 1, wherein the insulating dielectric layer (11) is silicon dioxide with a thickness of (500 nm-800 nm) ± 10%.

6. A method of fabricating a self-built electric field based radiation-hardened silicon-based bipolar transistor structure according to claim 1, comprising the steps of:

step 1, carrying out impurity selective doping in different areas on a silicon wafer to obtain a bipolar transistor main body (100), and then forming an insulating layer (6) on the bipolar transistor main body (100);

step 2, etching on the insulating layer (6) to form a ground potential electrode contact window (15) and a bipolar transistor electrode leading-out contact window (12);

step 3, depositing a first metal layer (10) on the surface of the product prepared in the step 2;

step 4, etching the first metal layer (10) to form a ground potential layer;

step 5, forming an intermetallic insulating medium layer (11) on the product prepared in the step 4 by chemical vapor deposition;

step 6, etching on the inter-metal insulating medium layer (11) to form a bipolar transistor electrode leading-out contact window (12);

step 7, depositing a second metal layer (13) on the surface of the product obtained in the step 6;

and 8, etching the second metal layer (13) to form a circuit wiring interconnection layer (7).

7. The method of fabricating a self-created electric field based radiation-hardened silicon-based bipolar transistor structure according to claim 6, wherein in step 3, the material of the first metal layer (10) is aluminum-silicon-copper or doped polysilicon.

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