CN110850819A - Single-arm combined equipment scheduling method, system, mobile terminal and storage medium - Google Patents

Abstract

The invention is applicable to the technical field of semiconductor manufacturing automation equipment, and provides a scheduling method, system, mobile terminal and storage medium for a single-arm combined equipment. The method includes: analyzing the schedulability of the single-arm combined equipment when multiple varieties of wafers are processed simultaneously , and propose deadlock avoidance rules according to the schedulability; establish a Petri net model according to the deadlock avoidance rules; obtain the local processing strategy, and calculate the processing strategy in the Petri net model, so as to obtain a single arm when processing multiple varieties of wafers at the same time. The optimal scheduling algorithm of the combined equipment; the single-arm combined equipment is controlled to perform processing scheduling according to the optimal scheduling algorithm. The invention can avoid the system deadlock problem caused by the simultaneous processing of multi ^- variety wafers, reduce the wafer quality and damage the SACT equipment. It can effectively deal with the scheduling problem of simultaneous processing of multi-variety wafers, and reduce the production time wasted due to system debugging.

Description

Single-arm combined equipment scheduling method, system, mobile terminal and storage medium

technical field

The present invention relates to the technical field of semiconductor manufacturing automation equipment, and in particular, to a scheduling method, system, mobile terminal and storage medium for single-arm combined equipment.

Background technique

In recent years, due to the expansion of market demand, the improvement of the investment environment, and the transfer of the global semiconductor industry to China, the development of my country's integrated circuit industry has maintained continuous growth, which has further stimulated the growth of demand for basic materials such as monocrystalline silicon and polycrystalline silicon. Combination equipment is the most critical type of equipment for manufacturing silicon wafers, and its highly automated manufacturing system can effectively respond to market demands. However, the wafer contains multiple layers of circuits, and the processing environment is high temperature and high pressure. It is not easy to schedule and control the manufacturing system to be put into production. Studying the scheduling and control requirements of combined equipment in different operating environments has become the focus of attention in this field.

The combined equipment usually contains 4-6 manufacturing units (MU), vacuum locks (loadlock, LL) and transport unit (TU) for loading the wafers to be processed and finished wafers, and the corresponding combined equipment is called For single-arm combination equipment (single-arm cluster tools, SATCs) and dual-arm combination equipment (dual-arm cluster tools, DACLs). The TU is located in the center of the equipment, and the other MUs are radially distributed and controlled by the computer. The equipment has a unique single-wafer manufacturing technology, that is, at the same time, any MU can only process a single wafer at most. Typically, two LLs are set up in a combined facility, and each LL can hold 25 wafers of the same type. The wafer to be processed needs to be unloaded from the LL by the robot and loaded into the system; then, different MUs are accessed in sequence according to the wafer processing process; finally, the robot will load the finished wafer into the LL again.

As wafer manufacturing shifts from high-volume and low-variety to customer-customized, it leads to frequent system switching and debugging, and finding new scheduling methods will inevitably waste a lot of time and cost. In order to improve the utilization and flexibility of the equipment, the combined equipment is more used to process multiple types of wafers at the same time, and the process paths of different types of wafers have MU sharing. However, existing scheduling and control methods are only applicable to a single variety or a specific wafer variety. In addition, the combined device has no buffer, and the limited MU brings the problem of resource competition, which is easy to cause system deadlock.

SUMMARY OF THE INVENTION

The technical problem to be solved by the embodiments of the present invention is that in the scheduling process of the existing single-arm combined equipment, since the scheduling method is only applicable to a single variety or a specific wafer variety, the problem of a high system lock rate is caused.

The embodiments of the present invention are implemented in this way, a method for scheduling a single-arm combined equipment, the method comprising:

Analyze the schedulability of single-arm combined equipment when multiple varieties of wafers are processed simultaneously, and propose deadlock avoidance rules according to the schedulability;

Establish a Petri net model according to the deadlock avoidance rule;

Obtaining a local processing strategy, and calculating the processing strategy in the Petri net model, so as to obtain the optimal scheduling algorithm of the single-arm combination device when multiple varieties of wafers are processed simultaneously;

Control the single-arm combined equipment to perform processing scheduling according to the optimal scheduling algorithm

Further, the step of proposing deadlock avoidance rules according to the schedulability includes:

When the robot in the single-arm combination equipment unloads the wafer from the manufacturing unit MU _i (i∈Nn) and moves to the next processing step Si _-next , one of the following conditions must be met:

When the number of wafers to be processed in the manufacturing unit MU _i (i=0) is not less than 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈Nn ⁺ ) is 1, Si _-next =MU _i-next is an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _n+1 .

Further, the described step of establishing a Petri net model according to the deadlock avoidance rule includes:

Obtain the operating characteristics of the system and the action sequence of the manipulator when the single-arm combination device simultaneously processes multiple varieties of wafers stored in the deadlock avoidance rule;

To establish the Petri net model according to the operating characteristics and the action sequence of the manipulator;

i∈N_ζ ⁺，

x_j ⁱ∈N_n ⁺，m_i≤n。Among them, the single-arm combination equipment processes multiple types of wafers at the same time, and the wafer flow of the i-th type of wafers

i∈N _ζ ⁺ ,

x _j ⁱ ∈N _n ⁺ , and m _i ≤n.

Further, the functional relationship between the location and transition of the single-arm combination device is as follows:

u₀ ^(i)·＝{d₀₁ ⁽ⁱ⁾}，

u _j ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , w _j ⁽ⁱ⁾ },

u ₀ ⁽ⁱ⁾ = {d ₀₁ ⁽ⁱ⁾ },

u₀′^(i)·＝{d₀₁ ⁽ⁱ⁾}，

u ₀ ′ ⁽ⁱ⁾ = {p ₀ ⁽ⁱ⁾ , d ₀ ⁽ⁱ⁾ } ^, u _j ′ ⁽ⁱ⁾ = {p _j ′ ⁽ⁱ⁾ },

u ₀ ′ ⁽ⁱ⁾ = {d ₀₁ ⁽ⁱ⁾ },

l_j ^(i)·＝{p_j ⁽ⁱ⁾，r}，

^·l_n+1＝{p_n+1′}，l_n+1 ^·＝{p_n+1，r}；l _j ⁽ⁱ⁾ = {d _(j-1)j ⁽ⁱ⁾ },

l _j ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , r},

^· l _n+1 = {p _n+1 ′}, l _n+1 ^· = {p _n+1 , r};

l_j′^(i)·＝{p_j′⁽ⁱ⁾}，

l_n+1′^(i)·＝{p₀ ⁽ⁱ⁾，d₀ ⁽ⁱ⁾，p_n+1}；

l _j ′ ⁽ⁱ⁾ ＝{p _j ′ ⁽ⁱ⁾ },

l _n+1 ′ ^(i)· ={p ₀ ⁽ⁱ⁾ , d ₀ ⁽ⁱ⁾ , p _n+1 };

v_rj ^(i)·＝{p_j ⁽ⁱ⁾，w_j ⁽ⁱ⁾}，

v _rj ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , w _j ⁽ⁱ⁾ },

r represents a single-arm manipulator;

表示晶圆在第j道工序加工时制造单元

对应的资源库所，

x_j ⁱ∈N_n ⁺；

Indicates the manufacturing unit when the wafer is processed in the jth process

the corresponding repository,

x _j ⁱ ∈N _n ⁺ ;

p ₀ ⁽ⁱ⁾ means that the single-arm combination device places the i-th wafer to be processed in the input;

p _j ⁽ⁱ⁾ indicates that the i-th type of wafer is processed in the j-th process,

p _j ′ ⁽ⁱ⁾ indicates that the i-th type of wafer is processed in the j-th process,

p _n+1 ⁽ⁱ⁾ represents the i-th finished wafer placed in the output of the single-arm combination device;

p _n+1 ' indicates that the robot moves to the output end and is ready to load the finished wafer to the output end;

与p_n+1′，无实意； for connection

and p _n+1 ′, meaningless;

j＜k；d _jk ⁽ⁱ⁾ means that the robot moves the i-th wafer from the j-th process to the k-th process,

j <k;

w _j ⁽ⁱ⁾ represents the waiting time before the machine unloads the i-th wafer from the j-th process;

v _rj ⁽ⁱ⁾ means that the unloaded manipulator moves to the jth process,

u _j ⁽ⁱ⁾ means that the robot unloads the i-th wafer from the j-th process,

u _j ′ ⁽ⁱ⁾ means that the robot unloads the i-th wafer from the j-th process,

l _j ⁽ⁱ⁾ means that the robot loads the i-th type of wafer to the j-th process,

l _j ′ ⁽ⁱ⁾ means that the robot loads the i-th type of wafer to the j-th process,

Further, the processing strategy is that when a plurality of processing modules in the single-arm combined equipment process wafers at the same time, the robot on the single-arm combined equipment moves to the target module that processes the wafers fastest, and processes all the wafers. described wafer unloading on the target module.

Another object of the embodiments of the present invention is to provide a single-arm combined equipment scheduling system, the system includes:

The analysis module is used to analyze the schedulability of the single-arm combination equipment when multiple varieties of wafers are processed at the same time, and propose deadlock avoidance rules according to the schedulability;

A modeling module for establishing a Petri net model according to the deadlock avoidance rule;

an algorithm calculation module for obtaining a local processing strategy, and calculating the processing strategy in the Petri net model to obtain an optimal scheduling algorithm for the single-arm combination device when multiple varieties of wafers are simultaneously processed;

A scheduling control module, configured to control the single-arm combined equipment to perform processing scheduling according to the optimal scheduling algorithm.

Further, the analysis module is also used for:

When the robot in the single-arm combination equipment unloads the wafer from the manufacturing unit MU _i (i∈N _n ) and moves to the next processing step Si _-next , one of the following conditions must be met:

When the number of wafers to be processed in the manufacturing unit MU _i (i=0) is not less than 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _n+1 .

Further, the modeling module is also used for:

Obtain the operating characteristics of the system and the action sequence of the manipulator when the single-arm combination device simultaneously processes multiple varieties of wafers stored in the deadlock avoidance rule;

To establish the Petri net model according to the operating characteristics and the action sequence of the manipulator;

i∈N_ζ ⁺，x_j ⁱ∈N_n ⁺，m_i≤n。Among them, the single-arm combination equipment processes multiple types of wafers at the same time, and the wafer flow of the i-th type of wafers

i∈N _ζ ⁺ , x _j ⁱ ∈N _n ⁺ , and m _i ≤n.

Another object of the embodiments of the present invention is to provide a mobile terminal, including a storage device and a processor, where the storage device is used to store a computer program, and the processor runs the computer program to make the mobile terminal execute the above-mentioned Single-arm combined equipment scheduling method.

Another object of the embodiments of the present invention is to provide a storage medium, which stores the above-mentioned computer program used in the mobile terminal, and when the computer program is executed by the processor, implements the steps of the above-mentioned single-arm combination equipment scheduling method.

The embodiment of the present invention can avoid the system deadlock problem caused by the simultaneous processing of multi-variety wafers, reduce the wafer quality and damage the SACT equipment. The scheduling algorithm in the single-arm combined equipment scheduling method has a computational complexity of O(n ² ), can efficiently deal with the scheduling problem of simultaneous processing of multi-variety wafers, reducing the production time wasted due to system debugging.

Description of drawings

FIG. 1 is a flowchart of a method for scheduling a single-arm combined equipment provided by a first embodiment of the present invention;

2 is a flowchart of a method for scheduling a single-arm combination device provided by a second embodiment of the present invention;

3 is a schematic structural diagram of a single-arm assembly device provided by a second embodiment of the present invention;

4 is a schematic diagram of a wafer processing path provided by a second embodiment of the present invention;

5 is a schematic diagram of a Petri net model of two types of wafers simultaneously processed in SACT according to the second embodiment of the present invention;

6 is a schematic structural diagram of a single-arm combined equipment scheduling system provided by a third embodiment of the present invention;

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

In order to illustrate the technical solutions of the present invention, the following specific embodiments are used for description.

Example 1

Please refer to FIG. 1, which is a flowchart of a method for scheduling a single-arm combined equipment provided by the first embodiment of the present invention, including the steps:

Step S10, analyzing the schedulability of the single-arm assembly equipment when multiple varieties of wafers are simultaneously processed, and proposing deadlock avoidance rules according to the schedulability;

Among them, by analyzing the design of the schedulability of the single-arm combination equipment when multiple types of wafers are processed at the same time, the wafer flow and deadlock situation of multiple types of wafers in SACT can be analyzed;

Step S20, establishes a Petri net model according to the deadlock avoidance rule;

Wherein, through the establishment of the Petri net model, the analysis of wafer processing on the single-arm combination equipment is effectively facilitated;

Step S30, obtaining a local processing strategy, and calculating the processing strategy in the Petri net model, so as to obtain an optimal scheduling algorithm for the single-arm assembly equipment when multiple varieties of wafers are processed simultaneously;

Wherein, the processing strategy is that when a plurality of processing modules in the single-arm combined equipment process wafers at the same time, the robot on the single-arm combined equipment moves to the target module that processes the wafers fastest, and converts the target wafer unloading on module;

Step S40, controlling the single-arm combined equipment to perform processing scheduling according to the optimal scheduling algorithm;

This embodiment can avoid the system deadlock problem caused by the simultaneous processing of multi-variety wafers, reduce the wafer quality and damage the SACT equipment. The scheduling algorithm in the single-arm combined equipment scheduling method has a computational complexity of O(n ² ), which can efficiently deal with the scheduling problem of simultaneous processing of multi-variety wafers, reducing the production time wasted due to system debugging.

Embodiment 2

Please refer to FIG. 2 to FIG. 4 , which are flowcharts of a method for scheduling single-arm combined equipment provided by the second embodiment of the present invention, including the steps:

Step S11, analyzing the schedulability of the single-arm assembly equipment when multiple varieties of wafers are processed simultaneously, and propose deadlock avoidance rules according to the schedulability;

i∈N_ζ ⁺，

x_j ⁱ∈N_n ⁺，m_i≤n。SACT processes multiple varieties of wafers at the same time, and the wafer flow of the i-th wafer is

i∈N _ζ ⁺ ,

x _j ⁱ ∈N _n ⁺ , and m _i ≤n.

N _n ⁺ = {1, 2..., n};

n represents the total number of manufacturing units MU in the system;

m _i represents the total number of i-th wafer processing operations;

S _{i, j} represents the jth process of the i-th wafer processing;

表示第i种晶圆的第j道工序对应的制造单元。

Indicates the manufacturing unit corresponding to the jth process of the ith wafer.

Specifically, in this step, when SACT processes multiple types of wafers at the same time, only a single-arm manipulator is used in the system for loading and unloading wafers. The resource competition problem can easily lead to system deadlock, reduce productivity and even damage equipment. However, combined equipment is very expensive, so deadlock is a key issue for SACT to process a wide variety of wafers. In the SACT of n MUs, if the robot unloads wafers from MU _i (i∈N _n ⁺ ), it should detect in advance whether there are wafers in MU _i . If MU _i has wafer processing, the manipulator can execute this command, otherwise the manipulator will be prohibited from executing this command in order to avoid system deadlock. Similarly, if the robot unloads wafers from MU ₀ , in order to avoid system deadlock, it is necessary to ensure that there are wafers to be processed in MU ₀ .

Preferably, the step of proposing deadlock avoidance rules according to the schedulability includes:

When the robot in the single-arm combination equipment unloads the wafer from the manufacturing unit MU _i (i∈N _n ) and moves to the next processing step Si _-next , one of the following conditions must be met:

When the number of wafers to be processed in the manufacturing unit MU _i (i=0) is not less than 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _n+1 ;

Step S21, obtaining the operating characteristics of the system and the action sequence of the manipulator when the single-arm combination device stored in the deadlock avoidance rule simultaneously processes multiple varieties of wafers;

Step S31, to establish the Petri net model according to the operating characteristics and the action sequence of the manipulator;

i∈N_ζ ⁺，x_j ⁱ∈N_n ⁺，m_i≤n；Among them, the single-arm combination equipment processes multiple types of wafers at the same time, and the wafer flow of the i-th type of wafers

i∈N _ζ ⁺ , x _j ⁱ ∈N _n ⁺ , m _i ≤n;

表示SACT加工多品种晶圆的Petri网模型，其中库所集

变迁集

初始标识

According to the operating characteristics and the action sequence of the manipulator, step 31 establishes a general Petri net model to describe the simultaneous processing of multi-variety wafers in SACT,

Represents a Petri net model for SACT processing multi-variety wafers, where the library sets

transition set

initial identification

Specifically, the functional relationship F between the locations and transitions of the single-arm combination device is as follows:

u₀ ^(i)·＝{d₀₁ ⁽ⁱ⁾}，

u _j ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , w _j ⁽ⁱ⁾ },

u ₀ ⁽ⁱ⁾ = {d ₀₁ ⁽ⁱ⁾ },

u ₀ ′ ⁽ⁱ⁾ = {p ₀ ⁽ⁱ⁾ , d ₀ ⁽ⁱ⁾ } ^, u _j ′ ⁽ⁱ⁾ = {p _j ′ ⁽ⁱ⁾ }, u ₀ ′ ⁽ⁱ⁾ = {d ₀₁ ⁽ⁱ⁾ },

l_j ^(i)·＝{p_j ⁽ⁱ⁾，r}，

^·l_n+1＝{p_n+1′}，l_n+1 ^·＝{p_n+1，r}；l _j ⁽ⁱ⁾ = {d _(j-1)j ⁽ⁱ⁾ },

l _j ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , r},

^· l _n+1 = {p _n+1 ′}, l _n+1 ^· = {p _n+1 , r};

l_j′^(i)·＝{p_j′⁽ⁱ⁾}，

l_n+1′^(i)·＝{p₀ ⁽ⁱ⁾，d₀ ⁽ⁱ⁾，p_n+1}；

l _j ′ ⁽ⁱ⁾ ＝{p _j ′ ⁽ⁱ⁾ },

l _n+1 ′ ^(i)· ={p ₀ ⁽ⁱ⁾ , d ₀ ⁽ⁱ⁾ , p _n+1 };

v_rj ^(i)·＝{p_j ⁽ⁱ⁾，w_j ⁽ⁱ⁾}，

v _rj ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , w _j ⁽ⁱ⁾ },

r represents a single-arm manipulator;

对应的资源库所，

x_j ⁱ∈N_n ⁺； Indicates the manufacturing unit when the wafer is processed in the jth process

the corresponding repository,

x _j ⁱ ∈N _n ⁺ ;

p ₀ ⁽ⁱ⁾ means that the single-arm combination device places the i-th wafer to be processed in the input;

p _j ⁽ⁱ⁾ indicates that the i-th type of wafer is processed in the j-th process,

p _j ′ ⁽ⁱ⁾ indicates that the i-th type of wafer is processed in the j-th process,

p _n+ ¹⁽ⁱ⁾ represents the i-th finished wafer placed in the output of the single-arm combination device;

p _n+1 ' indicates that the robot moves to the output end and is ready to load the finished wafer to the output end;

用于连接与p_n+1′，无实意；

for connection and p _n+1 ′, meaningless;

j＜k；d _jk ⁽ⁱ⁾ means that the robot moves the i-th wafer from the j-th process to the k-th process,

j <k;

w _j ⁽ⁱ⁾ represents the waiting time before the machine unloads the i-th wafer from the j-th process;

v _rj ⁽ⁱ⁾ means that the unloaded manipulator moves to the jth process,

u _j ⁽ⁱ⁾ means that the robot unloads the i-th wafer from the j-th process,

u _j ′ ⁽ⁱ⁾ means that the robot unloads the i-th wafer from the j-th process,

l _j ⁽ⁱ⁾ means that the robot loads the i-th type of wafer to the j-th process,

l _j ′ ⁽ⁱ⁾ means that the robot loads the i-th type of wafer to the j-th process,

表示第i种晶圆在某批量加工的总数量；

Indicates the total number of i-th wafers processed in a batch;

Step S41, obtaining a local processing strategy, and calculating the processing strategy in the Petri net model, so as to obtain an optimal scheduling algorithm for the single-arm combination device when multiple varieties of wafers are processed simultaneously;

Wherein, the processing strategy is that when a plurality of processing modules in the single-arm combined equipment process wafers at the same time, the robot on the single-arm combined equipment moves to the target module that processes the wafers fastest, and converts the target wafer unloading on module;

Preferably, the Petri net model defines a Petri net model for two kinds of wafers to be processed simultaneously in SACT, wherein the two wafer flows are WFP ₁ =(PM ₁ , PM ₃ ), WFP ₂ =(PM ₂ , PM ₃ , respectively );

In this step, the algorithm is: when the Petri net model is in any state marked as M _k (k≥1), select the enabling transition t according to the following rules, so that the system reaches a new state M _k+1 , and the real-time scheduling and control system Process a variety of wafers.

Specifically, the specific implementation procedure in this step is:

E _r represents the set;

R(p) represents the residence time of the token in place p,

R(t) represents the time required to trigger the transition,

M _i represents the sign that the vector corresponding to the library reaches after the i-th trigger transition;

表示第i次触发变迁对应的向量；

Represents the vector corresponding to the i-th trigger transition;

表示系统的Petri网模型对应的关联矩阵；

Represents the correlation matrix corresponding to the Petri net model of the system;

χ _i (p) represents the moment when the token enters the place p,

λ _i represents the moment when the system reaches the mark _Mi ;

formula:

m_i≤n，和x_j ⁱ∈N_n ⁺，

M₀(p)＝0，

λ₀＝0；Note: If χ _i (p)=0, it means that when the system reaches the mark _Mi , no token enters the place p. In the initial state, SACT is in an idle state, and the identification can be obtained

m _i ≤n, and x _j ⁱ ∈N _n ⁺ ,

M ₀ (p)=0,

λ ₀ =0;

Step S51, controlling the single-arm combined equipment to perform processing scheduling according to the optimal scheduling algorithm;

This embodiment can avoid the system deadlock problem caused by the simultaneous processing of multi-variety wafers, reduce the wafer quality and damage the SACT equipment. The scheduling algorithm in the single-arm combined equipment scheduling method has a computational complexity of O(n ² ), which can efficiently deal with the scheduling problem of simultaneous processing of multi-variety wafers, reducing the production time wasted due to system debugging.

Embodiment 3

Please refer to FIG. 6, which is a schematic structural diagram of a single-arm combined equipment scheduling system 100 provided by the third embodiment of the present invention, including: an analysis module 10, a modeling module 11, an algorithm calculation module 12, and a scheduling control module 13, wherein:

The analysis module 10 is used to analyze the schedulability of the single-arm combination equipment when multiple varieties of wafers are processed simultaneously, and propose deadlock avoidance rules according to the schedulability.

The modeling module 11 is used for establishing a Petri net model according to the deadlock avoidance rule.

The algorithm calculation module 12 is used to obtain a local processing strategy, and calculate the processing strategy in the Petri net model, so as to obtain the optimal scheduling algorithm of the single-arm combination device when multiple varieties of wafers are processed simultaneously, wherein , the processing strategy is that when multiple processing modules process wafers simultaneously in the single-arm combination device, the robot on the single-arm combination device moves to the target module that processes the wafer fastest, and moves the target module to the target module. on the wafer unloading.

The scheduling control module 13 is configured to control the single-arm combined equipment to perform processing scheduling according to the optimal scheduling algorithm.

Preferably, the analysis module 10 is also used for:

When the robot in the single-arm combination equipment unloads the wafer from the manufacturing unit MU _i (i∈N _n ) and moves to the next processing step Si _-next , one of the following conditions must be met:

When the number of wafers to be processed in the manufacturing unit MU _i (i=0) is not less than 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _i-next is in an idle state;

When the number of processed wafers in the manufacturing unit MU _i (i∈N _n ⁺ ) is 1, Si _-next =MU _n+1 .

In this embodiment, the modeling module 11 is also used for:

Obtain the operating characteristics of the system and the action sequence of the manipulator when the single-arm combination device simultaneously processes multiple varieties of wafers stored in the deadlock avoidance rule;

To establish the Petri net model according to the operating characteristics and the action sequence of the manipulator;

i∈N_ζ ⁺，

x_j ⁱ∈N_n ⁺，m_i≤n；Among them, the single-arm combination equipment processes multiple types of wafers at the same time, and the wafer flow of the i-th type of wafers

i∈N _ζ ⁺ ,

x _j ⁱ ∈N _n ⁺ , m _i ≤n;

Specifically, the functional relationship between the location and transition of the single-arm combination device is as follows:

u₀ ^(i)·＝{d₀₁ ⁽ⁱ⁾}，

u _j ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , w _j ⁽ⁱ⁾ },

u ₀ ⁽ⁱ⁾ = {d ₀₁ ⁽ⁱ⁾ },

u₀′^(i)·＝{d₀₁ ⁽ⁱ⁾}，

u ₀ ′ ⁽ⁱ⁾ = {p ₀ ⁽ⁱ⁾ , d ₀ ⁽ⁱ⁾ } ^, u _j ′ ⁽ⁱ⁾ = {p _j ′ ⁽ⁱ⁾ },

u ₀ ′ ⁽ⁱ⁾ = {d ₀₁ ⁽ⁱ⁾ },

l_j ^(i)·＝{p_j ⁽ⁱ⁾，r}，

^·l_n+1＝{p_n+1′}，l_n+1 ^·＝{p_n+1，r}；l _j ⁽ⁱ⁾ = {d _(j-1)j ⁽ⁱ⁾ },

l _j ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , r},

^· l _n+1 = {p _n+1 ′}, l _n+1 ^· = {p _n+1 , r};

l _j ′ ⁽ⁱ⁾ ＝{p _j ′ ⁽ⁱ⁾ }, l _n+1 ′ ⁽ⁱ⁾ ·={p ₀ ⁽ⁱ⁾ , d ₀ ⁽ⁱ⁾ , p _n+1 };

v_rj ^(i)·＝{p_j ⁽ⁱ⁾，w_j ⁽ⁱ⁾}，

v _rj ⁽ⁱ⁾ = {p _j ⁽ⁱ⁾ , w _j ⁽ⁱ⁾ },

r represents a single-arm manipulator;

表示晶圆在第j道工序加工时制造单元

对应的资源库所，

x_j ⁱ∈_n ⁺；

Indicates the manufacturing unit when the wafer is processed in the jth process

the corresponding repository,

x _j ⁱ ∈ _n ⁺ ;

p ₀ ⁽ⁱ⁾ means that the single-arm combination device places the i-th wafer to be processed in the input;

p _j ⁽ⁱ⁾ indicates that the i-th type of wafer is processed in the j-th process,

p _j ′ ⁽ⁱ⁾ indicates that the i-th type of wafer is processed in the j-th process,

p _n+1 ⁽ⁱ⁾ represents the i-th finished wafer placed in the output of the single-arm combination device;

p _n+1 ′ indicates that the robot moves to the output end and is ready to load the finished wafer to the output end;

用于连接与p_n+1′，无实意；

for connection and p _n+1 ′, meaningless;

j＜k；d _jk ⁽ⁱ⁾ means that the robot moves the i-th wafer from the j-th process to the k-th process,

j <k;

w _j ⁽ⁱ⁾ represents the waiting time before the machine unloads the i-th wafer from the j-th process;

v _rj ⁽ⁱ⁾ means that the unloaded manipulator moves to the jth process,

u _j ⁽ⁱ⁾ means that the robot unloads the i-th wafer from the j-th process,

u _j ′ ⁽ⁱ⁾ means that the robot unloads the i-th wafer from the j-th process,

l _j ⁽ⁱ⁾ means that the robot loads the i-th type of wafer to the j-th process,

l _j ′ ⁽ⁱ⁾ means that the robot loads the i-th type of wafer to the j-th process,

This embodiment can avoid the system deadlock problem caused by the simultaneous processing of multi-variety wafers, reduce the wafer quality and damage the SACT equipment. The scheduling algorithm in the single-arm combined equipment scheduling method has a computational complexity of O(n ² ), which can efficiently deal with the scheduling problem of simultaneous processing of multi-variety wafers, reducing the production time wasted due to system debugging.

This embodiment also provides a mobile terminal, including a storage device and a processor, where the storage device is used to store a computer program, and the processor runs the computer program to make the mobile terminal perform the above-mentioned scheduling of the single-arm combination device method.

This embodiment also provides a storage medium on which the computer program used in the above-mentioned mobile terminal is stored, and when the program is executed, the program includes the following steps:

Analyze the schedulability of single-arm combined equipment when multiple varieties of wafers are processed simultaneously, and propose deadlock avoidance rules according to the schedulability;

Establish a Petri net model according to the deadlock avoidance rule;

Obtaining a local processing strategy, and calculating the processing strategy in the Petri net model, so as to obtain the optimal scheduling algorithm of the single-arm combination device when multiple varieties of wafers are processed simultaneously;

The single-arm combined equipment is controlled to perform processing scheduling according to the optimal scheduling algorithm. The storage medium, such as: ROM/RAM, magnetic disk, optical disk, etc.

Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. The module is completed, that is, the internal structure of the storage device is divided into different functional units or modules, so as to complete all or part of the functions described above. Each functional unit and module in the implementation manner may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit, and the above-mentioned integrated units may adopt hardware. It can also be realized in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application.

Those skilled in the art can understand that the composition shown in FIG. 6 does not constitute a limitation to the single-arm combined equipment scheduling system of the present invention, and may include more or less components than those shown in the figure, or combine certain components, or Different components are arranged, and the single-arm combined equipment scheduling method in FIG. 1 and FIG. 2 is also realized by using more or less components shown in FIG. 6 , or combining some components, or different component arrangements. The units, modules, etc. mentioned in the present invention refer to a series of computer programs that can be executed by the processor (not shown in the figure) in the scheduling system of the target single-arm combined equipment and can perform specific functions. It is stored in the storage device (not shown) of the target single-arm combined equipment scheduling system.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. A method for scheduling single-arm combined equipment, the method comprising:

the schedulability of single-arm combination equipment for simultaneously processing multiple varieties of wafers is analyzed, and a deadlock avoidance rule is proposed according to the schedulability;

establishing a Petri network model according to the deadlock avoidance rule;

acquiring a local processing strategy, and calculating the processing strategy in the Petri network model to obtain an optimal scheduling algorithm of the single-arm combination equipment when multiple varieties of wafers are processed simultaneously;

and controlling the single-arm combined equipment to process and schedule according to the optimal scheduling algorithm.

2. The single-arm combined equipment scheduling method of claim 1, wherein said step of proposing deadlock avoidance rules according to said schedulability comprises:

when the robot in the single arm cluster tool is MU from manufacturing_i(i∈N_n) Unloading the wafer and moving to the next processing step S_i-nextOne of the following conditions is satisfied:

when manufacturing the unit MU_i(i-0) when the number of wafers to be processed is not less than 1, S_i-next＝MU_i-nextIs in an idle state;

when manufacturing the unit MU_i(i∈N_n ⁺) When the number of the middle processing wafers is 1, S_i-next＝MU_i-nextIs in an idle state;

when manufacturing the unit MU_i(i∈N_n ⁺) When the number of the middle processing wafers is 1, S_i-next＝MU_n+1。

3. The single-arm combination equipment scheduling method of claim 1, wherein the step of building a Petri Net model according to the deadlock avoidance rule comprises:

acquiring the operation characteristics of the system and the action sequence of the manipulator when the single-arm combined equipment simultaneously processes a plurality of kinds of wafers, which are stored in the deadlock avoidance rule;

establishing the Petri network model according to the operation characteristics and the action sequence of the manipulator;

wherein, the single-arm combination equipment simultaneously processes the wafer flow of a plurality of varieties of wafers and the ith wafer

i∈Nζ⁺，

x_j ⁱ∈N_n ⁺，m_i≤n。

4. The method for scheduling a single-arm combination device according to claim 3, wherein the functional relationship between the library and the transition of the single-arm combination device is as follows:

^·u_j ⁽ⁱ⁾＝{p_j ⁽ⁱ⁾，w_j ⁽ⁱ⁾}，

u₀ ^(i)·＝{d₀₁ ⁽ⁱ⁾}，

^·u₀′⁽ⁱ⁾＝{p₀ ⁽ⁱ⁾，d₀ ⁽ⁱ⁾}，^·u_j′⁽ⁱ⁾＝{p_j′⁽ⁱ⁾}，u₀′^(i)·＝{d₀₁ ⁽ⁱ⁾}，

^·l_j ⁽ⁱ⁾＝{d_(j-1)j ⁽ⁱ⁾}，l_j ^(i)·＝{p_j ⁽ⁱ⁾，r}，

^·l_n+1＝{p_n+1′}，l_n+1·＝{p_n+1，r}；

l_j′^(i)·＝{p_j′⁽ⁱ⁾}，

l_n+1′⁽ⁱ⁾·＝{p₀ ⁽ⁱ⁾，d₀ ⁽ⁱ⁾，p_n+1}；

v_rj ^(i)·＝{p_j ⁽ⁱ⁾，w_j ⁽ⁱ⁾}，

r represents a single-arm manipulator;

indicating that the wafer is processed in the jth process

The corresponding resource pool is provided with a plurality of resource pools,

p₀ ⁽ⁱ⁾showing the single-arm combined equipment placing the ith wafer to be processed in the input end;

p_j ⁽ⁱ⁾indicating that the ith type wafer is processed in the jth procedure,

p_j′⁽ⁱ⁾indicating that the ith type wafer is processed in the jth procedure,

p_n+1 ⁽ⁱ⁾showing the i-th product wafer placed in the output end of the single-arm combined equipment;

p_n+1' indicating the robot moves to the output and is ready to load a finished wafer to the output;

for connecting

And p_n+1', no sense;

d_jk ⁽ⁱ⁾showing the robot moving the ith wafer from the jth process to the kth process,

j＜k；

w_j ⁽ⁱ⁾indicating a wait before the machine unloads the ith wafer from the jth process;

v_rj ⁽ⁱ⁾the empty manipulator is shown to move to the j-th procedure,

u_j ⁽ⁱ⁾indicating that the robot unloads the ith wafer from the jth process,

u_j′⁽ⁱ⁾indicating that the robot unloads the ith wafer from the jth process,

l_j ⁽ⁱ⁾showing the robot loading the ith type of wafer into the jth process,

l_j′⁽ⁱ⁾showing the robot loading the ith type of wafer into the jth process,

5. the method as claimed in claim 1, wherein the processing strategy is that when a plurality of processing modules process wafers simultaneously in the single-arm assembly, the robot on the single-arm assembly moves to a target module that processes the wafer most quickly and unloads the wafer on the target module.

6. A single-armed cluster device dispatch system, the system comprising:

the analysis module is used for analyzing the schedulability of the single-arm combination equipment when multiple varieties of wafers are processed simultaneously and providing a deadlock avoidance rule according to the schedulability;

the modeling module is used for establishing a Petri network model according to the deadlock avoidance rule;

the algorithm calculation module is used for acquiring a local processing strategy and calculating the processing strategy in the Petri network model so as to obtain an optimal scheduling algorithm of the single-arm combination equipment when multiple varieties of wafers are processed simultaneously;

and the scheduling control module is used for controlling the single-arm combination equipment to perform processing scheduling according to the optimal scheduling algorithm.

7. The single-arm cluster tool scheduling system of claim 6, wherein the analysis module is further configured to:

when the robot in the single arm cluster tool is MU from manufacturing_i(i∈N_n) Unloading the wafer and moving to the next processing step S_i-nextOne of the following conditions is satisfied:

when manufacturing the unit MU_i(i-0) when the number of wafers to be processed is not less than 1, S_i-next＝MU_i-nextIs in an idle state;

when manufacturing the unit MU_i(i∈N_n ⁺) When the number of the middle processing wafers is 1, S_i-next＝MU_i-nextIs in an idle state;

when manufacturing the unit MU_i(i∈N_n ⁺) When the number of the middle processing wafers is 1, S_i-next＝MU_n+1。

8. The single-arm cluster tool scheduling system of claim 6, wherein the modeling module is further configured to:

acquiring the operation characteristics of the system and the action sequence of the manipulator when the single-arm combined equipment simultaneously processes a plurality of kinds of wafers, which are stored in the deadlock avoidance rule;

establishing the Petri network model according to the operation characteristics and the action sequence of the manipulator;

wherein, the single-arm combination equipment simultaneously processes the wafer flow of a plurality of varieties of wafers and the ith wafer

i∈N_ζ ⁺，x_j ⁱ∈N_n ⁺，m_i≤n。

9. A mobile terminal, characterized by comprising a storage device for storing a computer program and a processor for executing the computer program to cause the mobile terminal to execute the single-arm combination device scheduling method according to any one of claims 1 to 5.

10. A storage medium, characterized in that it stores a computer program for use in a mobile terminal according to claim 9, which computer program, when executed by a processor, implements the steps of the single-arm combination device scheduling method according to any one of claims 1 to 5.

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