CN110838472B - Chip package structure with six-face protection layer and manufacturing method thereof - Google Patents
Chip package structure with six-face protection layer and manufacturing method thereof Download PDFInfo
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Abstract
本发明提供一种具有六面式保护层的晶片封装结构及其制造方法，其利用第一、第二、第三保护层分别遮覆在一矩形晶片的第一、第二表面及四个侧表面上，矩形晶片是由一晶圆凭借分割道分割形成，晶圆的第一面上设有第一保护层、多个矩形晶片及多条凹槽，该多条凹槽可利用第一保护层的绝缘材同时填满以形成各分割道；该晶圆是由其第二面进行研磨以显露出各矩形晶片的第二表面及各分割道的底面供用以形成第二保护层；其中各分割道的宽度是大于分割耗损宽度，使各分割道在分割之后能在二相邻的矩形晶片的二相对的侧表面上分别保留一剩余宽度供作为第三保护层。
The present invention provides a chip packaging structure with a six-sided protective layer and a manufacturing method thereof, wherein the first, second and third protective layers are used to cover the first, second and four side surfaces of a rectangular chip respectively, wherein the rectangular chip is formed by dividing a wafer by dividing lanes, wherein a first protective layer, a plurality of rectangular chips and a plurality of grooves are provided on the first surface of the wafer, wherein the plurality of grooves can be simultaneously filled with the insulating material of the first protective layer to form each dividing lane; the wafer is ground by its second surface to expose the second surface of each rectangular chip and the bottom surface of each dividing lane for forming a second protective layer; wherein the width of each dividing lane is greater than the dividing loss width, so that after dividing, each dividing lane can retain a residual width on two opposite side surfaces of two adjacent rectangular chips for use as a third protective layer.
Description
技术领域Technical Field
本发明涉及一种晶片封装结构及其制造方法，尤指一种各利用一保护层以分别包覆在一矩形晶片的第一、第二表面及四个侧表面上而形成一具有六面式保护层的晶片封装结构。The present invention relates to a chip packaging structure and a manufacturing method thereof, in particular to a chip packaging structure with six-sided protective layers formed by respectively covering the first surface, the second surface and four side surfaces of a rectangular chip with a protective layer.
背景技术Background Art
现有的晶片封装制程中都会进行一封胶(molding)程序来使晶粒与外界隔离以避免其上的电性连结用金线被破坏或防止湿气进入晶粒以避免腐蚀或信号破坏。现有的封胶(molding)程序是将完成焊线的导线架放置于治具框架上并加以预热，再将该框架放入压模机的封装模具中，并将半熔融状态的绝缘材如环氧树脂(epoxy)注入封装模具中以包覆在晶片的各表面上，待冷却硬化后即可取出，如此晶片的各表面会被以封胶(molding)方式模塑成型的外壳所包覆；由上可知，现有晶片的封胶(molding)程序须配合压模机及封装模具才能完成，相对会增加压模机的设备成本及封装模具的制作成本。此外，一般的WLCSP晶片(WLCSP，Wafer Level Chip Scale Package，晶圆级晶片尺寸封装)只会在晶片的上、下表面(即本案所称的第一、二表面)设置保护层，但延伸在上、下层之间的四个侧表面则未设置保护层；由于高阶的WLCSP晶片在制程中都是凭借机械手臂来准确操作，故晶片的四个侧表面在制程中不致发生碰撞而甚至造成毁损的问题；然而，中低阶的WLCSP晶片一般是不利用机械手臂来操作，以致该WLCSP晶片的四个侧表面在制程中相对会发生碰撞或毁损的问题，故针对中低阶的WLCSP晶片而言，在该晶片的六面上，包含上表面(即本案所称的第一表面)、下表面(即本案所称的第二表面)及四个侧表面等共六个表面，都有设置至少一保护层的需要。然而，若采用现有的封胶(molding)程序模塑成型一外壳的方式来制作一具有六面式保护层的晶片封装结构，在实际制作上不但存有相当的困难度，而且至少会增加压模机的设备成本及封装模具的制作成本，不利于降低中低阶的WLCSP晶片的制作成本。本发明即是针对上述需要而提供一种有效率的解决方案。In the existing chip packaging process, a molding process is performed to isolate the die from the outside world to prevent the gold wires used for electrical connection from being damaged or to prevent moisture from entering the die to prevent corrosion or signal damage. The existing molding process is to place the wire frame with completed bonding wires on the fixture frame and preheat it, then put the frame into the packaging mold of the molding machine, and inject semi-molten insulating materials such as epoxy into the packaging mold to cover the surfaces of the chip. After cooling and hardening, it can be taken out, so that the surfaces of the chip will be covered by the shell molded by molding. As can be seen from the above, the molding process of the existing chip must be completed in conjunction with the molding machine and the packaging mold, which will relatively increase the equipment cost of the molding machine and the production cost of the packaging mold. In addition, a general WLCSP chip (WLCSP, Wafer Level Chip Scale Package) only has a protective layer on the upper and lower surfaces (i.e., the first and second surfaces in this case) of the chip, but no protective layer is provided on the four side surfaces extending between the upper and lower layers; since high-end WLCSP chips are accurately operated by a robot during the manufacturing process, the four side surfaces of the chip will not collide or even be damaged during the manufacturing process; however, medium and low-end WLCSP chips are generally not operated by a robot, so that the four side surfaces of the WLCSP chip are relatively likely to collide or be damaged during the manufacturing process. Therefore, for medium and low-end WLCSP chips, it is necessary to provide at least one protective layer on the six surfaces of the chip, including the upper surface (i.e., the first surface in this case), the lower surface (i.e., the second surface in this case) and the four side surfaces, a total of six surfaces. However, if a chip package structure with a six-sided protective layer is manufactured by molding a shell using an existing molding procedure, it is not only quite difficult to manufacture, but also increases the equipment cost of the molding machine and the manufacturing cost of the packaging mold, which is not conducive to reducing the manufacturing cost of low-end and medium-end WLCSP chips. The present invention provides an efficient solution to the above needs.
发明内容Summary of the invention
本发明的主要目的在于提供一种具有六面式保护层的晶片封装结构及其制造方法，其系利用一第一保护层、一第二保护层及一第三保护层以分别对应遮覆在一矩形晶片的第一表面、第二表面及四个侧表面上，其中该矩形晶片是由一晶圆凭借多条分割道所分割形成，该晶圆的第一面上设有该第一保护层、多个矩形晶片及多条凹槽，在封装制程中可利用该第一保护层的绝缘材同时填满各凹槽以形成各分割道；其中该晶圆是由其第二面进行研磨以显露出各矩形晶片的第二表面及各分割道的底面并位于同一平面上，供可在该同一平面上制作并形成该第二保护层；其中各分割道的宽度是大于分割刀具所产生的分割耗损宽度，使各分割道在分割之后能在二相邻的矩形晶片的二相对的侧表面上分别保留一剩余宽度供作为该第三保护层，如此提供一种有效的具有六面式保护层的晶片封装结构及其制造方法，并同时解决现有封胶(molding)程序模塑成型方式不适用于中低阶的WLCSP晶片封装结构的问题。The main purpose of the present invention is to provide a chip packaging structure with a six-sided protective layer and a manufacturing method thereof, wherein a first protective layer, a second protective layer and a third protective layer are used to cover the first surface, the second surface and four side surfaces of a rectangular chip respectively, wherein the rectangular chip is formed by dividing a wafer by a plurality of dividing roads, and the first surface of the wafer is provided with the first protective layer, a plurality of rectangular chips and a plurality of grooves, and the insulating material of the first protective layer can be used to fill the grooves at the same time to form the dividing roads in the packaging process; wherein the wafer is ground from its second surface to reveal the rectangular chips. The second surface of the rectangular chip and the bottom surface of each dividing road are located on the same plane, so that the second protective layer can be made and formed on the same plane; wherein the width of each dividing road is greater than the dividing consumption width generated by the dividing tool, so that each dividing road can retain a residual width on two opposite side surfaces of two adjacent rectangular chips after dividing to serve as the third protective layer, thereby providing an effective chip packaging structure with a six-sided protective layer and a manufacturing method thereof, and at the same time solving the problem that the existing molding process molding method is not suitable for medium and low-level WLCSP chip packaging structures.
为达成上述目的，本发明提供：一种具有六面式保护层的晶片封装结构，其特征是包含：To achieve the above object, the present invention provides: a chip packaging structure with a six-sided protective layer, which is characterized by comprising:
一矩形晶片，其具有六表面包含：一第一表面其上设有多个焊垫、一相对该第一表面的第二表面、及四个侧表面分别环绕设在该矩形晶片的侧边上且分别延伸在该第一表面与该第二表面之间；其中在该第一表面的各焊垫上分别对应设有一具有适当高度的凸块；该矩形晶片由一晶圆分割形成，该晶圆的第一面上成型设有多个形成阵列排列的矩形晶片及多条分割道，并使二相邻的矩形晶片之间各设有一分割道；其中各矩形晶片的厚度与各分割道的深度约略相等且都小于该晶圆的厚度；A rectangular chip having six surfaces including: a first surface on which a plurality of pads are arranged, a second surface opposite to the first surface, and four side surfaces respectively arranged around the side edges of the rectangular chip and respectively extending between the first surface and the second surface; wherein a bump with an appropriate height is respectively arranged on each pad on the first surface; the rectangular chip is formed by dividing a wafer, wherein a plurality of rectangular chips arranged in an array and a plurality of dividing lanes are formed on the first surface of the wafer, and a dividing lane is respectively arranged between two adjacent rectangular chips; wherein the thickness of each rectangular chip and the depth of each dividing lane are approximately equal and are both smaller than the thickness of the wafer;
一第一保护层，其设在该矩形晶片的第一表面上，且该第一保护层上设有多个开口供分别对应显露各凸块；A first protective layer is disposed on the first surface of the rectangular wafer, and the first protective layer is provided with a plurality of openings for respectively correspondingly exposing the bumps;
一第二保护层，其设在各矩形晶片的第二表面上；及a second protective layer disposed on the second surface of each rectangular wafer; and
一第三保护层，其一体地设在该四个侧表面上，使该第三保护层能与该第一保护层及该第二保护层结合构成一体的六面式保护层供用来包覆并保护该矩形晶片所具有的六个表面；a third protective layer integrally disposed on the four side surfaces, so that the third protective layer can be combined with the first protective layer and the second protective layer to form an integrated six-sided protective layer for covering and protecting the six surfaces of the rectangular wafer;
其中各分割道的形成是先在该晶圆的第一面上预设多条对应于各分割道的凹槽，各凹槽的深度小于该晶圆的厚度而约等于各矩形晶片的厚度，再利用绝缘材填满各凹槽以形成各分割道；The formation of each dividing street is to firstly preset a plurality of grooves corresponding to each dividing street on the first surface of the wafer, the depth of each groove is less than the thickness of the wafer and approximately equal to the thickness of each rectangular chip, and then fill each groove with an insulating material to form each dividing street;
其中该晶圆的厚度大于各矩形晶片的厚度或各分割道的深度，因此该晶圆的厚度与各矩形晶片的厚度或各分割道的深度之间会产生一厚度差，其中该晶圆是由该晶圆的第二面进行研磨以去除该厚度差以显露出各矩形晶片的第二表面及各分割道的底面且位于同一平面上，之后再在该晶圆的研磨后的同一平面上形成该第二保护层，如此使该第二保护层形成于各矩形晶片的第二表面上，且各分割道是位于该第一保护层与该第二保护层之间并与该第一保护层及该第二保护层连结成一体；The thickness of the wafer is greater than the thickness of each rectangular wafer or the depth of each dividing road, so there is a thickness difference between the thickness of the wafer and the thickness of each rectangular wafer or the depth of each dividing road, wherein the wafer is ground from the second surface of the wafer to remove the thickness difference so as to expose the second surface of each rectangular wafer and the bottom surface of each dividing road and to be located on the same plane, and then the second protective layer is formed on the same plane after the grinding of the wafer, so that the second protective layer is formed on the second surface of each rectangular wafer, and each dividing road is located between the first protective layer and the second protective layer and connected to the first protective layer and the second protective layer as a whole;
其中各分割道的宽度大于分割时的分割耗损宽度，并使该分割耗损宽度位于或靠近于该分割道宽度的中间处，如此在分割完成时，各分割道的宽度在减除各分割耗损宽度之后，能在二相邻的矩形晶片的二相对的侧表面上分别保留一剩余宽度供作为各侧表面的第三保护层，如此使分割后的各矩形晶片具有一由该第三保护层、该第一保护层及该第二保护层所结合构成的一体的六面式保护层供用来包覆并保护各矩形晶片所具有的六个表面。The width of each dividing road is larger than the dividing consumption width during dividing, and the dividing consumption width is located at or close to the middle of the dividing road width. Thus, when dividing is completed, after deducting the dividing consumption width, the width of each dividing road can retain a remaining width on two opposite side surfaces of two adjacent rectangular chips to serve as a third protective layer for each side surface. In this way, each rectangular chip after dividing has an integrated six-sided protective layer composed of the third protective layer, the first protective layer and the second protective layer to cover and protect the six surfaces of each rectangular chip.
所述的具有六面式保护层的晶片封装结构，其中：当在该晶圆的第一面上制作形成该第一保护层时，其是在同一制作步骤中同时利用该第一保护层的绝缘材填满于设在该晶圆的第一面上各凹槽内部以制作形成各分割道。The chip packaging structure with a six-sided protective layer, wherein: when the first protective layer is formed on the first surface of the wafer, the insulating material of the first protective layer is used to fill the inside of each groove arranged on the first surface of the wafer in the same production step to form each dividing lane.
所述的具有六面式保护层的晶片封装结构，其中：该第一保护层、第二保护层、或第三保护层所采用的绝缘材包含环氧树脂。The chip packaging structure with six-sided protective layers, wherein: the insulating material used in the first protective layer, the second protective layer, or the third protective layer includes epoxy resin.
所述的具有六面式保护层的晶片封装结构，其中：该第一保护层、第二保护层、或第三保护层是采用旋转涂布或印刷方式形成。The chip packaging structure with six-sided protective layers, wherein: the first protective layer, the second protective layer, or the third protective layer is formed by spin coating or printing.
所述的具有六面式保护层的晶片封装结构，其中：该第二保护层进一步是利用一两层式胶带来制作形成，其中该两层式胶带是由一在内层的绝缘材层及一在外层的分割用胶带层所构成，其中在制作时，该两层式胶带是先贴附在该晶圆的研磨后的同一平面上，其中该树脂材层对应于各分割耗损宽度的部分是在分割作业时随着该分割耗损宽度一起被切除，使该树脂材层未被切除的其余部分及分割用胶带层保留在该晶圆的研磨后的同一平面上，之后再除去该分割用胶带层，使保留在该晶圆的研磨后的同一平面上的该树脂材层的其余部分形成该第二保护层。The chip packaging structure with six-sided protective layers, wherein: the second protective layer is further formed by using a two-layer tape, wherein the two-layer tape is composed of an inner insulating material layer and an outer dividing tape layer, wherein during the production, the two-layer tape is first attached to the same plane of the wafer after grinding, wherein the portion of the resin material layer corresponding to each dividing loss width is cut off along with the dividing loss width during the dividing operation, so that the remaining portion of the resin material layer that is not cut off and the dividing tape layer remain on the same plane of the wafer after grinding, and then the dividing tape layer is removed, so that the remaining portion of the resin material layer remaining on the same plane of the wafer after grinding forms the second protective layer.
一种具有六面式保护层的晶片封装结构的制造方法，其特征是包含下列步骤：A method for manufacturing a chip packaging structure with a six-sided protective layer, characterized by comprising the following steps:
步骤1：提供一晶圆，该晶圆上设有多个形成阵列排列的矩形晶片且各矩形晶片的厚度是小于该晶圆的厚度；在该晶圆的第一面上设有多条凹槽以使二相邻的矩形晶片之间设有一凹槽，且各凹槽的深度是小于该晶圆的厚度而约等于各矩形晶片的厚度；又各矩形晶片的第一表面上设有多个焊垫；Step 1: providing a wafer, on which a plurality of rectangular chips arranged in an array are disposed, and the thickness of each rectangular chip is less than the thickness of the wafer; a plurality of grooves are disposed on a first surface of the wafer so that a groove is disposed between two adjacent rectangular chips, and the depth of each groove is less than the thickness of the wafer and approximately equal to the thickness of each rectangular chip; and a plurality of pads are disposed on the first surface of each rectangular chip;
步骤2：在该晶圆的第一面上形成一第一保护层，该第一保护层的绝缘材是遮覆各矩形晶片的第一表面且设有多个开口供分别对应显露各矩形晶片的第一表面上所设的多个焊垫；Step 2: forming a first protective layer on the first surface of the wafer, wherein the insulating material of the first protective layer covers the first surface of each rectangular chip and has a plurality of openings for respectively correspondingly exposing a plurality of solder pads disposed on the first surface of each rectangular chip;
步骤3：利用绝缘材以填满该晶圆的第一面上所设的各凹槽以使二相邻的矩形晶片之间形成一分割道，其中各分割道的宽度大于分割作业时的分割耗损宽度；Step 3: Filling each groove on the first surface of the wafer with an insulating material to form a dividing street between two adjacent rectangular wafers, wherein the width of each dividing street is greater than the dividing loss width during the dividing operation;
步骤4：在该第一保护层所设的各开口中各形成设有一具有适当高度的凸块供分别对应连结至各矩形晶片的第一表面上所设的多个焊垫；Step 4: forming a bump with a proper height in each opening of the first protective layer for correspondingly connecting to a plurality of pads provided on the first surface of each rectangular wafer;
步骤5：针对该晶圆的厚度大于该矩形晶片或该分割道的厚度所产生的厚度差部分，利用研磨作业以由该晶圆相对于该第一面的第二面来研磨去除该厚度差部分，以使各矩形晶片的第二表面及各分割道的底面显露于该晶圆的研磨后的同一平面上；Step 5: For a portion of the wafer whose thickness is greater than that of the rectangular wafer or the dividing street, grinding the second surface of the wafer relative to the first surface to remove the portion of the thickness difference, so that the second surface of each rectangular wafer and the bottom surface of each dividing street are exposed on the same plane of the wafer after grinding;
步骤6：在该晶圆的研磨后的同一平面上形成一第二保护层，使该第二保护层遮覆在各矩形晶片的第二表面及各分割道的底面上；Step 6: forming a second protective layer on the same plane of the wafer after grinding, so that the second protective layer covers the second surface of each rectangular wafer and the bottom surface of each dividing road;
步骤7：对该晶圆进行分割作业，其中各分割道的宽度大于分割时的分割耗损宽度，且使各分割耗损宽度位于或靠近于各分割道宽度的中间处，以在分割完成时，各分割道的宽度在减除分割时的各分割耗损宽度之后，仍能在二相邻的矩形晶片的相对应的侧表面上分别保留一剩余宽度供作为各矩形晶片的各侧表面的第三保护层，如此使分割后的各矩形晶片各具有一由该第一保护层、该第二保护层及该第三保护层所结合构成的六面式保护层供用来遮覆并保护各矩形晶片所具有的六个表面。Step 7: The wafer is divided, wherein the width of each dividing road is larger than the dividing consumption width during division, and each dividing consumption width is located at or close to the middle of the dividing road width, so that when the division is completed, the width of each dividing road, after deducting the dividing consumption width during division, can still retain a remaining width on the corresponding side surfaces of two adjacent rectangular chips to serve as a third protective layer for each side surface of each rectangular chip. In this way, each rectangular chip after division has a six-sided protective layer composed of the first protective layer, the second protective layer and the third protective layer to cover and protect the six surfaces of each rectangular chip.
所述的具有六面式保护层的晶片封装结构的制造方法，其中：在步骤2的制程中当在该晶圆的第一面上形成该第一保护层时，能同时进行并完成在步骤中利用该第一保护层所用的绝缘材以填满该晶圆的第一面上所设的各凹槽以使二相邻的矩形晶片之间形成一分割道的制程。The manufacturing method of the chip packaging structure with a six-sided protective layer, wherein: in the process of step 2, when the first protective layer is formed on the first surface of the wafer, the process of using the insulating material used in the first protective layer in the step to fill the grooves set on the first surface of the wafer to form a dividing street between two adjacent rectangular chips can be simultaneously carried out and completed.
如此使分割后的各矩形晶片具有一由该第三保护层、该第一保护层及该第二保护层所结合构成的一体的六面式保护层供用来包覆并保护各矩形晶片所具有的六个表面。Thus, each rectangular wafer after being divided has an integrated six-sided protective layer composed of the third protective layer, the first protective layer and the second protective layer, which is used to cover and protect the six surfaces of each rectangular wafer.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本发明一实施例在晶圆上形成第一保护层时的侧面剖视示意图。FIG. 1 is a side cross-sectional schematic diagram of forming a first protective layer on a wafer according to an embodiment of the present invention.
图2是图1中在晶圆的各焊垫上形成凸块时的侧面剖视示意图。FIG. 2 is a side cross-sectional schematic diagram of the process of forming bumps on each pad of the wafer in FIG. 1 .
图3是图2中由晶圆的第二面研磨去除一厚度差部分的侧面剖视示意图。FIG. 3 is a side cross-sectional schematic diagram of FIG. 2 showing a portion with a thickness difference removed by grinding the second surface of the wafer.
图4是图3中在研磨后的平面上制作形成第二保护层的侧面剖视示意图。FIG. 4 is a side cross-sectional schematic diagram of the second protective layer formed on the ground plane in FIG. 3 .
图5是图4在分割作业后的侧面剖视图。FIG. 5 is a side cross-sectional view of FIG. 4 after the segmentation operation.
图6是图3中在研磨后的平面上贴附一两层式胶带的侧面剖视示意图。FIG. 6 is a side cross-sectional schematic diagram of a two-layer adhesive tape attached to the ground plane in FIG. 3 .
图7是图6中在分割作业后的侧面剖视图。FIG. 7 is a side cross-sectional view of FIG. 6 after the segmentation operation.
图8是图7中在分离分割用胶带层后的侧面剖视图。FIG. 8 is a side cross-sectional view of FIG. 7 after the separating tape layer is separated.
附图标记说明：1晶片封装结构；10矩形晶片；11第一表面；12焊垫；13第二表面；14侧表面；15凸块；20第一保护层；21开口；30第二保护层；31分割用胶带层；40第三保护层；40第三保护层；2晶圆；2a厚度差；201第一面；202分割道；202a分割耗损宽度；202b剩余宽度；203凹槽；204第二面；205底面。Explanation of the reference numerals: 1 chip packaging structure; 10 rectangular chip; 11 first surface; 12 solder pad; 13 second surface; 14 side surface; 15 bump; 20 first protective layer; 21 opening; 30 second protective layer; 31 tape layer for dividing; 40 third protective layer; 40 third protective layer; 2 wafer; 2a thickness difference; 201 first surface; 202 dividing road; 202a dividing consumption width; 202b remaining width; 203 groove; 204 second surface; 205 bottom surface.
具体实施方式DETAILED DESCRIPTION
配合图示，将本发明的结构及其技术特征详述如后，其中各图示只用以说明本发明的结构关系及相关功能，因此各元件的尺寸并非依实际比例设置且非用以限制本发明。With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each component is not set according to the actual proportion and is not used to limit the present invention.
参考图1至图5，本发明提供一种具有六面式保护层的晶片封装结构1，其主要包含：一矩形晶片10、一第一保护层20、一第二保护层30、及一第三保护层40。1 to 5 , the present invention provides a chip packaging structure 1 with six-sided protection layers, which mainly includes: a rectangular chip 10 , a first protection layer 20 , a second protection layer 30 , and a third protection layer 40 .
参考图1至图5，该矩形晶片10具有六表面，该六表面包含：一第一表面11其上设有多个焊垫12、一相对该第一表面11的第二表面13、及四个侧表面14分别环绕设在该矩形晶片10的侧边上且分别延伸位于该第一表面11与该第二表面13之间。在该第一表面11的各焊垫12上分别对应设有一具适当高度的凸块(bump)15。该矩形晶片10由一晶圆2分割形成，该晶圆2的第一面201上成型设有多个形成阵列排列的矩形晶片10及多条分割道202，并使二相邻的矩形晶片10之间各设有一分割道202。各矩形晶片10的厚度与各分割道202的深度约略相等且都是小于该晶圆2的厚度。Referring to FIGS. 1 to 5 , the rectangular chip 10 has six surfaces, including a first surface 11 on which a plurality of pads 12 are disposed, a second surface 13 opposite to the first surface 11, and four side surfaces 14 respectively disposed around the side edges of the rectangular chip 10 and extending between the first surface 11 and the second surface 13. A bump 15 having an appropriate height is disposed on each pad 12 of the first surface 11. The rectangular chip 10 is formed by dividing a wafer 2, and a plurality of rectangular chips 10 and a plurality of dividing lanes 202 are formed on a first surface 201 of the wafer 2 in an array arrangement, and a dividing lane 202 is disposed between each of two adjacent rectangular chips 10. The thickness of each rectangular chip 10 and the depth of each dividing lane 202 are approximately equal and are both smaller than the thickness of the wafer 2.
参考图1至图5，该第一保护层20设在该矩形晶片10的第一表面11上，且该第一保护层20上设有多个开口21供分别对应显露各凸块(bump)15。1 to 5 , the first protection layer 20 is disposed on the first surface 11 of the rectangular wafer 10 , and a plurality of openings 21 are disposed on the first protection layer 20 for respectively exposing the bumps 15 .
参考图4、图5，该第二保护层30设在各矩形晶片10的第二表面13上如图5所示。4 and 5 , the second protection layer 30 is disposed on the second surface 13 of each rectangular wafer 10 as shown in FIG. 5 .
参考图4、图5，该第三保护层40一体地设在该四个侧表面14上，使该第三保护层40能与该第一保护层20及该第二保护层30结合构成一体的六面式保护层供用来包覆并保护该矩形晶片10所具有的六个表面(11、13、14)。4 and 5 , the third protective layer 40 is integrally disposed on the four side surfaces 14 , so that the third protective layer 40 can be combined with the first protective layer 20 and the second protective layer 30 to form an integrated six-sided protective layer for covering and protecting the six surfaces ( 11 , 13 , 14 ) of the rectangular wafer 10 .
参考图1至图5，各分割道202的形成是先在该晶圆2的第一面201上预设多条对应于各分割道202的凹槽203，各凹槽203的深度是小于该晶圆2的厚度而约等于各矩形晶片10的厚度，再利用绝缘材填满各凹槽203以形成各分割道202。1 to 5 , each dividing lane 202 is formed by first presetting a plurality of grooves 203 corresponding to each dividing lane 202 on the first surface 201 of the wafer 2, wherein the depth of each groove 203 is less than the thickness of the wafer 2 and approximately equal to the thickness of each rectangular chip 10, and then filling each groove 203 with insulating material to form each dividing lane 202.
参考图1至图5，该晶圆2的厚度是大于各矩形晶片10的厚度或各分割道202的深度，因此该晶圆2的厚度与各矩形晶片10的厚度或各分割道202的深度之间会产生一厚度差2a如图1、2所示，其中该晶圆2是由该晶圆2的第二面204进行研磨以去除该厚度差2a以显露出各矩形晶片10的第二表面13及各分割道202的底面205且位于同一平面13、205上，之后再于该晶圆2的研磨后的同一平面13、205上形成该第二保护层30，如此使该第二保护层30形成于各矩形晶片10的第二表面13上，且各分割道202是位于该第一保护层20与该第二保护层30之间并与该第一保护层20及该第二保护层30连结成一体。Referring to Figures 1 to 5, the thickness of the wafer 2 is greater than the thickness of each rectangular chip 10 or the depth of each dividing road 202, so a thickness difference 2a will be generated between the thickness of the wafer 2 and the thickness of each rectangular chip 10 or the depth of each dividing road 202 as shown in Figures 1 and 2, wherein the wafer 2 is ground by the second surface 204 of the wafer 2 to remove the thickness difference 2a to reveal the second surface 13 of each rectangular chip 10 and the bottom surface 205 of each dividing road 202 and located on the same plane 13, 205, and then the second protective layer 30 is formed on the same plane 13, 205 after the wafer 2 is ground, so that the second protective layer 30 is formed on the second surface 13 of each rectangular chip 10, and each dividing road 202 is located between the first protective layer 20 and the second protective layer 30 and connected to the first protective layer 20 and the second protective layer 30 as a whole.
参考图1至图5，各分割道202的宽度是大于分割时的分割耗损宽度202a，并使该分割耗损宽度202a位于或靠近于该分割道202宽度的中间处，如此在分割完成时如图5所示，各分割道202的宽度在减除各分割耗损宽度202a之后，仍然可在二相邻的矩形晶片10的二相对的侧表面14上分别保留一剩余宽度202b供作为各侧表面14的第三保护层40，如此使分割后的各矩形晶片10具有一由该第三保护层40、该第一保护层20及该第二保护层30所结合构成的一体的六面式保护层供用来包覆并保护各矩形晶片10所具有的六个表面(11、13、14)如图5所示。Referring to Figures 1 to 5, the width of each dividing road 202 is greater than the dividing loss width 202a during dividing, and the dividing loss width 202a is located at or close to the middle of the width of the dividing road 202. In this way, when the dividing is completed, as shown in Figure 5, after deducting the dividing loss width 202a, the width of each dividing road 202 can still retain a remaining width 202b on the two opposite side surfaces 14 of two adjacent rectangular chips 10 to serve as the third protective layer 40 for each side surface 14. In this way, each rectangular chip 10 after dividing has an integrated six-sided protective layer composed of the third protective layer 40, the first protective layer 20 and the second protective layer 30 for covering and protecting the six surfaces (11, 13, 14) of each rectangular chip 10 as shown in Figure 5.
参考图1，当在该晶圆2的第一面201上制作形成该第一保护层20时，其是在同一制作步骤中同时利用该第一保护层20的绝缘材填满于设在该晶圆2的第一面201上各凹槽203内部以制作形成各分割道202。1 , when the first protective layer 20 is formed on the first surface 201 of the wafer 2 , the insulating material of the first protective layer 20 is simultaneously used to fill the inside of each groove 203 on the first surface 201 of the wafer 2 in the same manufacturing step to form each dividing lane 202 .
在本实施例中，该第一保护层20、第二保护层30、或第三保护层30所采用的绝缘材系环氧树脂(epoxyresin)但非用以限制本发明。此外，该第一保护层20、第二保护层30、或第三保护层30可以采用旋转涂布(spincoating)、印刷方式形成但非用以限制本发明。In this embodiment, the insulating material used for the first protective layer 20, the second protective layer 30, or the third protective layer 30 is epoxy resin, but it is not intended to limit the present invention. In addition, the first protective layer 20, the second protective layer 30, or the third protective layer 30 can be formed by spin coating or printing, but it is not intended to limit the present invention.
参考图3及图6至图8所示，图6至图8所示的实施例与图4、5所示的实施例比较，二者之间的主要差异处只在于该第二保护层30的制作形成方式不同而己。在图6至图8所示实施例中，该第二保护层30进一步是利用一两层式胶带(30，31)来制作形成，该两层式胶带(30，31)是由一在内层的绝缘材层(30)及一在外层的分割用胶带层(saw tape)31所构成，其中该分割用胶带层(saw tape)31乃本技术领域的现有物品，故在此可视为现有技艺。在制作时，该两层式胶带(30，31)是先贴附在该晶圆2的研磨后的同一平面13、205上如图3、6所示，其中该树脂材层(30)对应于各分割耗损宽度202a的部分是在分割作业时随着该分割耗损宽度202a一起被切除如图7所示，使该树脂材层(30)未被切除的其余部分及分割用胶带层(saw tape)31仍然保留在该晶圆2的研磨后的同一平面13、205上如图7所示，之后再除去或分离该分割用胶带层(saw tape)31如图8所示，其中除去或分离该分割用胶带层(sawtape)31的方法并不限制，如使用UV光来破坏该树脂材层(30)未被切除的其余部分与分割用胶带层(saw tape)31之间的粘着剂即可轻易除去或分离该分割用胶带层(saw tape)31。如此，保留在该晶圆2的研磨后的同一平面13、205上的该树脂材层30的其余部分即可形成该第二保护层30如图8所示。Referring to FIG. 3 and FIG. 6 to FIG. 8, the embodiment shown in FIG. 6 to FIG. 8 is compared with the embodiment shown in FIG. 4 and FIG. 5, and the main difference between the two is that the second protective layer 30 is made in a different way. In the embodiment shown in FIG. 6 to FIG. 8, the second protective layer 30 is further made by a two-layer adhesive tape (30, 31), and the two-layer adhesive tape (30, 31) is composed of an inner insulating material layer (30) and an outer saw tape layer 31, wherein the saw tape layer 31 is an existing article in the technical field, and thus can be regarded as the prior art. During the manufacturing process, the two-layer tape (30, 31) is first attached to the same plane 13, 205 of the wafer 2 after grinding as shown in Figures 3 and 6, wherein the portion of the resin material layer (30) corresponding to each splitting loss width 202a is cut off together with the splitting loss width 202a during the splitting operation as shown in Figure 7, so that the remaining portion of the resin material layer (30) that is not cut off and the splitting tape layer (saw tape) 31 are still retained on the same plane 13, 205 of the wafer 2 after grinding as shown in Figure 7, and then the splitting tape layer (saw tape) 31 is removed or separated as shown in Figure 8, wherein the method of removing or separating the splitting tape layer (saw tape) 31 is not limited, such as using UV light to destroy the adhesive between the remaining portion of the resin material layer (30) that is not cut off and the splitting tape layer (saw tape) 31, the splitting tape layer (saw tape) 31 can be easily removed or separated. In this way, the remaining portion of the resin material layer 30 remaining on the same plane 13 , 205 of the wafer 2 after grinding can form the second protection layer 30 as shown in FIG. 8 .
本发明进一步提供一种具有六面式保护层的晶片封装结构1的制造方法，其包含下列步骤：The present invention further provides a method for manufacturing a chip package structure 1 with a six-sided protection layer, which comprises the following steps:
步骤1：如图1所示，提供一晶圆2，该晶圆2上设有多个形成阵列排列的矩形晶片10且各矩形晶片10的厚度是小于该晶圆2的厚度；在该晶圆2的第一面201上设有多条凹槽203以使二相邻的矩形晶片10之间设有一凹槽203，且各凹槽203的深度是小于该晶圆2的厚度而约等于各矩形晶片10的厚度；又各矩形晶片10的第一表面11上设有多个焊垫12。Step 1: As shown in FIG. 1 , a wafer 2 is provided, on which a plurality of rectangular chips 10 arranged in an array are provided, and the thickness of each rectangular chip 10 is less than the thickness of the wafer 2; a plurality of grooves 203 are provided on a first surface 201 of the wafer 2 so that a groove 203 is provided between two adjacent rectangular chips 10, and the depth of each groove 203 is less than the thickness of the wafer 2 and approximately equal to the thickness of each rectangular chip 10; and a plurality of solder pads 12 are provided on the first surface 11 of each rectangular chip 10.
步骤2：如图1所示，在该晶圆2的第一面201上形成一第一保护层20，该第一保护层20的绝缘材是遮覆各矩形晶片10的第一表面11且设有多个开口21供分别对应显露各矩形晶片10的第一表面11上所设的多个焊垫12。Step 2: As shown in FIG. 1 , a first protective layer 20 is formed on the first surface 201 of the wafer 2. The insulating material of the first protective layer 20 covers the first surface 11 of each rectangular chip 10 and is provided with a plurality of openings 21 for respectively exposing a plurality of solder pads 12 provided on the first surface 11 of each rectangular chip 10.
步骤3：如图1所示，利用绝缘材以填满该晶圆2的第一面201上所设的各凹槽203以使二相邻的矩形晶片10之间形成一分割道202，其中各分割道202的宽度是大于分割作业时的分割耗损宽度202a。Step 3: As shown in FIG. 1 , insulating material is used to fill the grooves 203 on the first surface 201 of the wafer 2 so as to form a dividing lane 202 between two adjacent rectangular chips 10 , wherein the width of each dividing lane 202 is greater than the dividing loss width 202a during the dividing operation.
步骤4：如图2所示，在该第一保护层20所设的各开口21中各形成设有一具适当高度的凸块(bump)15供分别对应连结至各矩形晶片10的第一表面11上所设的多个焊垫12。Step 4: As shown in FIG. 2 , a bump 15 with a proper height is formed in each opening 21 of the first protection layer 20 for correspondingly connecting to a plurality of pads 12 disposed on the first surface 11 of each rectangular chip 10 .
步骤5：如图3所示，针对该晶圆2的厚度大于该矩形晶片10或该分割道202的厚度所产生的厚度差2a部分，利用研磨作业以由该晶圆2相对于该第一面201的第二面204来研磨去除该厚度差2a部分，以使各矩形晶片10的第二表面13及各分割道202的底面205显露于该晶圆2的研磨后的同一平面13、205上。Step 5: As shown in Figure 3, for the thickness difference 2a portion of the wafer 2 that is greater than the thickness of the rectangular chip 10 or the dividing road 202, a grinding operation is used to grind and remove the thickness difference 2a portion from the second surface 204 of the wafer 2 relative to the first surface 201, so that the second surface 13 of each rectangular chip 10 and the bottom surface 205 of each dividing road 202 are exposed on the same plane 13, 205 of the wafer 2 after grinding.
步骤6：如图4所示，在该晶圆2的研磨后的同一平面13、205上形成一第二保护层30，使该第二保护层30遮覆在各矩形晶片10的第二表面13及各分割道21的底面205上。Step 6: As shown in FIG. 4 , a second protective layer 30 is formed on the same plane 13 , 205 of the wafer 2 after grinding, so that the second protective layer 30 covers the second surface 13 of each rectangular chip 10 and the bottom surface 205 of each dividing street 21 .
步骤7：如图5或图8所示，对经过步骤6后的该晶圆2进行分割作业，其中各分割道202的宽度是大于分割时的分割耗损宽度202a，且使各分割耗损宽度202a位于或靠近于各分割道202宽度的中间处(如图4、5所示)，故在分割完成后，各分割道202的宽度在减除分割时的各分割耗损宽度202a之后，仍能在二相邻的矩形晶片10的相对应的侧表面14上分别保留一剩余宽度202b供作为各矩形晶片10的各侧表面14的第三保护层40，如此使分割后的各矩形晶片10具有一由该第一保护层20、该第二保护层30及该第三保护层40所结合构成的六面式保护层供用来遮覆并保护各矩形晶片10所具有的六个表面(11、13、14)。Step 7: As shown in FIG. 5 or 8, the wafer 2 after step 6 is divided, wherein the width of each dividing lane 202 is greater than the dividing loss width 202a during division, and each dividing loss width 202a is located at or close to the middle of the width of each dividing lane 202 (as shown in FIGS. 4 and 5). Therefore, after the division is completed, the width of each dividing lane 202, after deducting the dividing loss width 202a during division, can still retain a remaining width 202b on the corresponding side surfaces 14 of two adjacent rectangular chips 10 to serve as the third protective layer 40 for each side surface 14 of each rectangular chip 10. In this way, each rectangular chip 10 after division has a six-sided protective layer composed of the first protective layer 20, the second protective layer 30 and the third protective layer 40 for covering and protecting the six surfaces (11, 13, 14) of each rectangular chip 10.
此外，如图1所示，在上述步骤2的制程中，当在该晶圆2的第一面201上形成该第一保护层20时，能同时进行并完成在步骤3的制程，即利用该第一保护层20所用的绝缘材以填满该晶圆2的第一面201上所设的各凹槽203以使二相邻的矩形晶片10之间形成一分割道202。In addition, as shown in FIG. 1 , in the process of step 2, when the first protective layer 20 is formed on the first surface 201 of the wafer 2, the process of step 3 can be simultaneously performed and completed, that is, the insulating material used for the first protective layer 20 is used to fill the grooves 203 provided on the first surface 201 of the wafer 2 so that a dividing street 202 is formed between two adjacent rectangular chips 10.
凭借上述结构及其制造方法，本发明的具有六面式保护层的晶片封装结构的制造方法，具有以下优点：With the above structure and manufacturing method thereof, the manufacturing method of the chip packaging structure with a six-sided protective layer of the present invention has the following advantages:
1、本发明的晶片封装结构具有六面式保护层，可以避免晶片(如WLCSP晶片)在制程中发生碰撞或毁损的问题，如此可提升晶片的制作合格率。1. The chip packaging structure of the present invention has a six-sided protection layer, which can prevent the chip (such as WLCSP chip) from being collided or damaged during the manufacturing process, thereby improving the manufacturing qualification rate of the chip.
2、在本发明的晶片封装结构1的制程中，当在该晶圆2的第一面201上形成该第一保护层20时，能同时利用该第一保护层20所用的绝缘材以填满该晶圆2的第一面201上所设的各凹槽203，以使二相邻的矩形晶片10之间形成一分割道202，如此可简化晶片封装结构1的制程并相对降低制作成本。2. In the manufacturing process of the chip packaging structure 1 of the present invention, when the first protective layer 20 is formed on the first surface 201 of the wafer 2, the insulating material used for the first protective layer 20 can be used to fill the grooves 203 provided on the first surface 201 of the wafer 2, so that a dividing street 202 is formed between two adjacent rectangular chips 10. This can simplify the manufacturing process of the chip packaging structure 1 and relatively reduce the manufacturing cost.
3、本发明的各分割道202的宽度是设计成大于分割时的分割耗损宽度202a，使各分割道202在切割完成后能在二相邻的矩形晶片10的相对应的侧表面14上分别保留一剩余宽度202b供作为各矩形晶片10的各侧表面14的第三保护层40，如此可简化第三保护层40的形成制程。3. The width of each dividing lane 202 of the present invention is designed to be larger than the dividing loss width 202a during dividing, so that each dividing lane 202 can retain a remaining width 202b on the corresponding side surfaces 14 of two adjacent rectangular chips 10 after cutting is completed to serve as the third protective layer 40 of each side surface 14 of each rectangular chip 10, thereby simplifying the formation process of the third protective layer 40.
以上说明对本发明而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离权利要求所限定的精神和范围的情况下，可作出许多修改、变化或等效，但都将落入本发明的保护范围之内。The above description is only illustrative rather than restrictive of the present invention. Those skilled in the art will understand that many modifications, changes or equivalents may be made without departing from the spirit and scope defined by the claims, but all will fall within the scope of protection of the present invention.
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