CN110837339B - Data integration method, memory storage device and memory control circuit unit - Google Patents

Abstract

The invention provides a data merging method, which is used for a memory storage device. The method comprises the following steps: a data consolidation operation is performed to store valid data collected from the source node to the reclamation node. The data merging operation includes: reading first data from the first entity unit via a first read operation; performing a first-stage programming operation on the second entity unit according to the first data; reading the first data from the first entity unit again via a second read operation; and performing a second-stage programming operation on the second physical unit according to the first data read by the second reading operation. In addition, the invention also provides a memory storage device and a memory control circuit unit.

Description

Data integration method, memory storage device and memory control circuit unit

technical field

The invention relates to a memory management technology, in particular to a data integration method, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for built-in Among the various portable multimedia devices listed above.

The rewritable non-volatile memory module can be a triple level cell (Triple Level Cell, TLC) NAND flash memory module (that is, a flash memory module that can store 3 bits in a storage unit) or a fourth-level Storage unit (Quad Level Cell, QLC) NAND flash memory module (that is, a flash memory module that can store 4 bits in one storage unit). In a TLC NAND type flash memory module or a QLC NAND type flash memory module, a physical unit can be programmed multiple times based on the same write data to fully store the write data. In addition, multiple programmed operations on different physical units can be interleaved. Therefore, it is often necessary to configure a buffer memory with sufficient storage space in the memory storage device to simultaneously store the written data for different physical units.

Contents of the invention

The invention provides a data integration method, a memory storage device and a memory control circuit unit, which can save the use space of the buffer memory in the data integration operation.

Exemplary embodiments of the present invention provide a data integration method for a memory storage device including a plurality of physical units, and the data integration method includes: performing a data integration operation to combine valid data collected from a source node Data is stored to the recycling node. The source node includes at least a first physical unit of the physical units, the recycling node includes a second physical unit of the physical units, and the data integration operation includes: via a first read operation from The first physical unit reads the first data; performs a first-stage programming operation on the second physical unit according to the first data; after performing the first-stage programming operation, via the second reading operations to read the first data from the first physical unit again; and perform a second stage programming operation on the second physical unit based on the first data read via the second read operation.

In an exemplary embodiment of the present invention, the source node further includes at least one third physical unit among the physical units, the recycling node further includes a fourth physical unit among the physical units, and the The data integration operation further includes: reading second data from the third entity unit; and programming according to the second data between the first-stage programming operation and the second-stage programming operation The fourth entity unit.

In an exemplary embodiment of the present invention, the data consolidation operation further includes: temporarily storing the first data read through the first read operation in a buffer memory, so as to provide data for the first The first data of the phase programming operation; temporarily storing the second data in the buffer memory, and the second data overwrites the first read through the first read operation in the buffer memory at least a portion of data; and temporarily storing the first data read through the second read operation in the buffer memory to provide the first data for the second stage programming operation data.

In an exemplary embodiment of the present invention, the data integration method further includes: recording read information in a management table, wherein the read information reflects whether the first physical unit has passed the first read reading at least one of the operation and the second reading operation; and erasing the first physical unit according to the read information.

In an exemplary embodiment of the present invention, the data integration method further includes: temporarily storing the first data read through the first read operation or the second read operation in a buffer memory . The second physical unit has a basic capacity, and the available capacity of the buffer memory is less than twice the basic capacity.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for performing a data integration operation, so as to store valid data collected from the source node into the recovery node. The source node includes at least one first physical unit among the physical units, the recycling node includes a second physical unit among the physical units, and the data consolidation operation includes: sending a first read instruction sequence Instructing to read first data from the first physical unit via a first read operation; sending a first write instruction sequence to instruct to perform a first-stage programming operation on the second physical unit according to the first data ; after performing the first-stage programming operation, sending a second read instruction sequence to indicate that the first data is read from the first physical unit again via a second read operation; and sending a second write The instruction sequence is to instruct to perform a second-stage programming operation on the second physical unit according to the first data read through the second read operation.

In an exemplary embodiment of the present invention, the data consolidation operation further includes: temporarily storing the first data read through the first read operation in a buffer memory, so as to provide data for the first The first data of the phase programming operation; temporarily storing the second data in the buffer memory, and the second data overwrites the first read through the first read operation in the buffer memory data; and temporarily storing the first data read through the second read operation in the buffer memory to provide the first data for the second stage programming operation.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to record read information in a management table and erase the first entity unit according to the read information. The read information reflects whether the first physical unit is read through at least one of the first read operation and the second read operation.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to temporarily store the first data read through the first read operation or the second read operation in a buffer memory. The second physical unit has a basic capacity, and the available capacity of the buffer memory is less than twice the basic capacity.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit includes a host interface, a memory interface and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used for performing a data consolidation operation, so as to store valid data collected from the source node into the recovery node. The source node includes at least one first physical unit among the physical units, the recycling node includes a second physical unit among the physical units, and the data consolidation operation includes: sending a first read instruction sequence Instructing to read first data from the first physical unit via a first read operation; sending a first write instruction sequence to instruct to perform a first-stage programming operation on the second physical unit according to the first data ; after performing the first-stage programming operation, sending a second read instruction sequence to indicate that the first data is read from the first physical unit again via a second read operation; and sending a second write The instruction sequence is to instruct to perform a second-stage programming operation on the second physical unit according to the first data read through the second read operation.

In an exemplary embodiment of the present invention, the source node further includes at least one third physical unit among the physical units, the recycling node further includes a fourth physical unit among the physical units, and the The data integration operation further includes: sending a third read instruction sequence to instruct to read second data from the third physical unit; and between the first-stage programming operation and the second-stage programming operation , sending a third write instruction sequence to instruct to program the fourth physical unit according to the second data.

In an exemplary embodiment of the present invention, the memory control circuit unit further includes a buffer memory. The buffer memory is connected to the memory management circuit, and the data integration operation further includes: temporarily storing the first data read through the first read operation in the buffer memory to provide The first data in the first stage programming operation; temporarily storing the second data in the buffer memory, and the second data in the buffer memory overwrites the data read by the first read operation fetching the first data; and temporarily storing the first data read through the second read operation in the buffer memory, so as to provide the first data for the second stage programming operation a data.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to record read information in a management table and erase the first entity unit according to the read information, wherein the read information reflects the Whether the first physical unit is read through at least one of the first read operation and the second read operation.

In an exemplary embodiment of the present invention, the second entity unit stores the first data by sequentially programming the first-stage programming operation and the second-stage programming operation.

In an exemplary embodiment of the present invention, the first-stage programming operation and the second-stage programming operation belong to a multi-stage programming operation, and the second physical unit undergoes the multi-stage programming operation A programmed storage unit stores no less than 3 bits.

In an exemplary embodiment of the present invention, the memory control circuit unit further includes a buffer memory. The buffer memory is connected to the memory management circuit, and the memory management circuit is also used to temporarily store the first data read through the first read operation or the second read operation in the memory management circuit. the buffer memory. The second physical unit has a basic capacity, and the available capacity of the buffer memory is less than twice the basic capacity.

Based on the above, in the data integration operation, the same data in the first physical unit can be read at least twice, so as to complete the multi-stage programming of the second physical unit according to the data read through different read operations operate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention;

2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5A is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention;

5B is a schematic diagram of a memory cell array according to another exemplary embodiment of the present invention;

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 7 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

Fig. 8 is a schematic diagram of a programmed entity unit according to an exemplary embodiment of the present invention;

Fig. 9 is a schematic diagram of a programmed entity unit according to an exemplary embodiment of the present invention;

Fig. 10 is a schematic diagram of a programmatic entity unit according to an exemplary embodiment of the present invention;

Fig. 11 is a schematic diagram of programming multiple entity units in a certain entity management unit according to an exemplary embodiment of the present invention;

Fig. 12 is a schematic diagram of a data integration operation according to an exemplary embodiment of the present invention;

13 to 17 are schematic diagrams of data integration operations according to an exemplary embodiment of the present invention;

FIG. 18 is a flow chart of a data consolidation method according to an exemplary embodiment of the present invention.

Explanation of reference numbers:

10, 30: memory storage device

11, 31: host system

110: System bus

111: Processor

112: random access memory

113: ROM

114: data transmission interface

12: Input/Output (I/O) device

20: Motherboard

201: Pen drive

202: memory card

203: SSD

204: Wireless memory storage device

205: Global Positioning System Module

206: Network interface card

207: Wireless transmission device

208: Keyboard

209: screen

210: Horn

32: SD card

33: CF card

34: Embedded storage device

341: Embedded multimedia card

342: Embedded multi-chip package storage device

402: Connect the interface unit

404: memory control circuit unit

406: Rewritable non-volatile memory module

502, 522: storage unit

504: bit line

506: word line

508: Shared source line

510, 520: memory cell array

512: Select Gate-Drain Transistor

514: select gate source transistor

524: bit line

524(1)～524(4): bytes

526(1)～526(8): word line layer:

602: memory management circuit

604: host interface

606: memory interface

608: Error Checking and Correction Circuit

610: buffer memory

612: Power management circuit

701: storage area

702: Replacement area

710(0)～710(B), 1110(0)～1110(D), 1210(0)～1210(E), 1220(0)～1220(F), 1310(0)～1310(G), 1320(0)～1320(H), 1610(0)～1610(I): entity unit

712(0)～712(C): logic unit

801, 802, 811~814, 821~828, 901~908, 911~926, 1001~1016, 1021~1036: Status

1110: Entity snap-in

1210, 1310, 1320, 1610: source nodes

1220: Recycle node

1300, 1400, 1600: data

1301, 1401, 1501, 1601, 1701: Read operation

1302, 1402, 1602: The first stage of programmatic operation

1502, 1702: The second stage of programmatic operation

S1810: Step (Start data consolidation operation)

S1820: Steps

S1821: Step (reading the first data from the first physical unit via the first read operation)

S1822: Step (executing the first stage programming operation on the second entity unit according to the first data)

S1823: step (reading the first data from the first physical unit again via the second read operation)

S1824: Step (perform a second-stage programming operation on the second physical unit according to the first data read via the second read operation)

S1830: step (end data consolidation operation)

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , random access memory 112 , ROM 113 and data transmission interface 114 are all connected to a system bus 110 .

In this exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114 . In addition, the host system 11 is connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be connected to the memory storage device 10 via wire or wirelessly. The memory storage device 10 may be, for example, a flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy storage device (for example, iBeacon ) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 3 , in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. Various non-volatile memory storage devices such as a secure digital (Secure Digital, SD) card 32 , a compact flash (Compact Flash, CF) card 33 or an embedded storage device 34 . The embedded storage device 34 includes various types such as an embedded multimedia card (embedded Multi MediaCard, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342, etc., which directly connect the memory module to the substrate of the host system on the embedded storage device.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11 . In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a device conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 Standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard , Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MemoryStick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware and write data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11, Operations such as reading and erasing.

The rewritable non-volatile memory module 406 is connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level storage unit (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in a storage unit), multiple Multi Level Cell (MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in one storage unit), triple level cell (Triple Level Cell, TLC) NAND flash memory module Flash memory module (that is, a flash memory module that can store 3 bits in a storage unit), a fourth-order storage unit (Quad Level Cell, QLC) NAND flash memory module (that is, a storage unit that can store 4 One-bit flash memory modules) other flash memory modules or other memory modules with the same characteristics.

The storage units in the rewritable non-volatile memory module 406 are arranged in an array. The memory cell arrays in different exemplary embodiments are described below with two-dimensional arrays and three-dimensional arrays respectively. It should be noted that the following exemplary embodiments are just some examples of memory cell arrays, and in other exemplary embodiments, the configuration of the memory cell arrays can be adjusted to meet practical requirements.

FIG. 5A is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, the memory cell array 510 includes a plurality of memory cells 502 for storing data, a plurality of select gate drain (SGD) transistors 512 and a plurality of select gate source (SGS) The transistor 514 , a plurality of bit lines 504 , a plurality of word lines 506 , and a common source line 508 are connected to the memory cells 502 . The memory cells 502 are arranged in an array at intersections of bit lines 504 and word lines 506 , as shown in FIG. 5A .

FIG. 5B is a schematic diagram of a memory cell array according to another exemplary embodiment of the present invention.

Referring to FIG. 5B, the memory cell array 520 includes a plurality of memory cells 522 for storing data, a plurality of bytes 524(1)-524(4), and a plurality of word line layers 526(1)-526(8). Bytes 524(1)-524(4) are independent of each other (eg, separated from each other) and are arranged along a first direction (eg, X-axis). Each of bytes 524(1)-524(4) includes a plurality of bit lines 524 that are independent of each other (eg, separated from each other). The bit lines 524 included in each byte are arranged along a second direction (eg, Y axis) and extend toward a third direction (eg, Z axis). The word line layers 526(1)˜526(8) are independent from each other (eg, separated from each other) and are stacked along a third direction. In this exemplary embodiment, each of the word line layers 526 ( 1 )˜ 526 ( 8 ) can also be regarded as a plane (also referred to as a word line plane). Each memory cell 522 is configured at each intersection between each bit line 524 in bytes 524(1)-524(4) and word line layers 526(1)-526(8). However, in another example embodiment, a byte may include more or fewer bit lines, and a word line layer may pass through more or fewer bytes.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (also referred to as threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a writing voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. The operation of changing the threshold voltage of the memory cell is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple storage states. Which storage state a memory cell belongs to can be determined by applying a read voltage, thereby obtaining one or more bits stored in the memory cell.

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , the memory control circuit unit 404 includes a memory management circuit 602 , a host interface 604 and a memory interface 606 .

The memory management circuit 602 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 602 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 602 below, it is equivalent to describing the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 602 are implemented in the form of firmware. For example, the memory management circuit 602 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 602 may also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program code (for example, a system area in the memory module dedicated to storing system data) middle. In addition, the memory management circuit 602 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instructions in 406 are loaded into the random access memory of the memory management circuit 602 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 602 may also be implemented in a hardware form. For example, the memory management circuit 602 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used for managing the storage units or groups thereof of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasing circuit is used for issuing an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 602 can also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 604 is connected to the memory management circuit 602 and is used for receiving and identifying commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 602 through the host interface 604 . In this exemplary embodiment, the host interface 604 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 604 may also be compatible with PATA standard, IEEE 1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 606 is connected to the memory management circuit 602 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable nonvolatile memory module 406 will be converted into a format acceptable to the rewritable nonvolatile memory module 406 via the memory interface 606 . Specifically, if the memory management circuit 602 wants to access the rewritable non-volatile memory module 406, the memory interface 606 will transmit the corresponding instruction sequence. For example, these command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and instructions for various memory operations such as changing the read Get the corresponding instruction sequence of the voltage level, etc.). These instruction sequences are, for example, generated by the memory management circuit 602 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 606 . These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program codes. For example, in the read command sequence, information such as read identification code and memory address will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 608 , a buffer memory 610 and a power management circuit 612 .

The error checking and correction circuit 608 is connected to the memory management circuit 602 and configured to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 602 receives a write command from the host system 11, the error checking and correction circuit 608 will generate a corresponding error correcting code (error correcting code, ECC) and /or error checking code (error detecting code, EDC), and the memory management circuit 602 will write the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable non-volatile memory In module 406. Afterwards, when the memory management circuit 602 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 608 will be based on The error correcting code and/or error checking code performs error checking and correcting operations on the read data.

The buffer memory 610 is connected to the memory management circuit 602 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 612 is connected to the memory management circuit 602 and used to control the power of the memory storage device 10 .

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also called a flash memory module, and the memory control circuit unit 404 is also called a flash memory for controlling the flash memory module. The controller, and/or the memory management circuit of FIG. 6 is also referred to as a flash memory management circuit.

FIG. 7 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

Referring to FIG. 7 , the memory management circuit 602 logically groups the physical units 710 ( 0 )˜710 (B) of the rewritable non-volatile memory module 406 into a storage area 701 and a replacement area 702 . The physical units 710(0)-710(A) in the storage area 701 are used to store data, and the physical units 710(A+1)-710(B) in the replacement area 702 are used to replace the data in the storage area 701 Damaged solid elements. For example, if the data read from a certain physical unit contains too many errors to be corrected, the physical unit will be regarded as a damaged physical unit. It should be noted that if there is no available physical unit in the replacement area 702 , the memory management circuit 602 may declare the entire memory storage device 10 as a write protect state, and data cannot be written any more.

The memory management circuit 602 programs memory cells on a physical unit basis. That is, storage units belonging to the same physical unit can be programmed simultaneously. For example, a physical unit may include storage units on N word lines, and N may be 4 or other integers (such as 2, 8 or 16, etc.). In other words, a physical cell may include or consist of memory cells on N word lines. However, in another exemplary embodiment, a physical unit may also include more or less storage units, which is not limited by the present invention. In an exemplary embodiment, a physical unit may also be called a layer (or memory layer).

The memory management circuit 602 configures the logic units 712 ( 0 )˜ 712 (C) to map the physical units 710 ( 0 )˜ 710 (A) in the storage area 701 . In this exemplary embodiment, a logical unit refers to a logical address. However, in another exemplary embodiment, a logical unit may also refer to a logical layer or consist of multiple consecutive or discontinuous logical addresses. Furthermore, each of logical units 712(0)-712(C) may be mapped to one or more physical units.

The memory management circuit 602 records the mapping relationship between logical units and physical units (also referred to as logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 intends to read data from or write data to the memory storage device 10 , the memory management circuit 602 can perform a data access operation to the memory storage device 10 according to the logical-physical address mapping table.

In an exemplary embodiment, the memory management circuit 602 performs a multi-stage programming operation on a physical unit to store data (also referred to as writing data) into the physical unit. For example, the multi-stage programming operation may at least include a first-stage programming operation and a second-stage programming operation, and the second-stage programming operation will be performed after the first-stage programming operation. In addition, between performing the first-stage programming operation and the second-stage programming operation on this physical unit, a programming operation on another physical unit may be performed.

FIG. 8 is a schematic diagram of a programmatic entity unit according to an exemplary embodiment of the present invention. Taking the TLCNAND flash memory module as an example, the multi-stage programming operation for a certain physical unit can program each storage unit belonging to the physical unit to a state of storing 3 bits.

Please refer to FIG. 8 , before a certain physical unit is programmed, the storage units of the physical unit belong to the state ERA. For example, after erasing the physical unit, the erased memory units all belong to the state ERA. The threshold voltages of the memory cells belonging to the state ERA are all within a predetermined voltage range (also called the erase voltage range). After a programming operation is performed on this physical unit, the programmed memory unit can belong to state 801 and state 802 . Memory cells belonging to different states have different threshold voltages. For example, the threshold voltage of memory cells belonging to state 802 is greater than the threshold voltage of memory cells belonging to state 801 . Then, after the next programming operation is performed on this physical cell, the programmed memory cells will belong to the states 811-814 and the threshold voltage of the memory cells will change accordingly. For example, memory cells belonging to state 811 have the lowest threshold voltage, while memory cells belonging to state 814 have the highest threshold voltage. Then, after the next programming operation is performed on this physical cell, the programmed memory cells will belong to states 821-828 and the threshold voltage of the memory cells will change accordingly. For example, memory cells belonging to state 821 have the lowest threshold voltage, while memory cells belonging to state 828 have the highest threshold voltage. Each memory cell belonging to states 821-828 stores 3 bits.

FIG. 9 is a schematic diagram of a programmatic entity unit according to an exemplary embodiment of the present invention. Taking the QLCNAND flash memory module as an example, the multi-stage programming operation for a certain physical unit can program each storage unit belonging to the physical unit to a state of storing 4 bits.

Please refer to FIG. 9 , taking the QLC NAND type flash memory module as an example, before programming a certain physical unit, the memory cells of this physical unit all belong to the state ERA. After a programming operation is performed on the physical unit, the programmed storage unit will belong to states 901-908. For example, the threshold voltage of memory cells belonging to state 908 is greater than the threshold voltage of memory cells belonging to state 901 . Then, after the next programming operation is performed on this physical cell, the programmed memory cells will belong to the states 911-926 and the threshold voltages of the memory cells will change accordingly. For example, the threshold voltage of memory cells belonging to state 926 is greater than the threshold voltage of memory cells belonging to state 911 . Each memory cell belonging to states 911-926 stores 4 bits.

In the exemplary embodiments of FIG. 8 and FIG. 9 , the programming operation executed first may be regarded as the first-stage programming operation, and the programming operation executed later may be regarded as the second-stage programming operation. For example, in an exemplary embodiment of FIG. 8, the first-stage programming operation programs the memory cells to belong to states 801 and 802 (or 811-814), and the second-stage programming operation programs the memory cells to It belongs to states 811-814 (or 821-828). In an exemplary embodiment of FIG. 9 , the first-stage programming operation programs the memory cells to belong to states 901 - 908 , and the second-stage programming operation programs the memory cells to belong to states 911 - 926 . It should be noted that the present invention does not limit the programming procedure of the memory cells in different programming stages in the multi-stage programming operation.

FIG. 10 is a schematic diagram of a programmatic entity unit according to an exemplary embodiment of the present invention. This exemplary embodiment also takes the programming of the QLC NAND flash memory module as an example.

Please refer to FIG. 10 , before a certain physical unit is programmed, the storage units of this physical unit all belong to the state ERA. After a programming operation is performed on the physical unit, the programmed storage unit will belong to states 1001-1016. Then, after the next programming operation is performed on this physical unit, the programmed memory unit will belong to the states 1021-1036. Each memory cell belonging to states 1021-1036 stores 4 bits. It should be noted that in the exemplary embodiment of FIG. 10 , the first-stage programming operation roughly adjusts the threshold voltage of the memory cell. Then, in the second stage of programming operation, the threshold voltage of the memory cell is more precisely adjusted to the voltage position corresponding to the states 1021-1036.

Fig. 11 is a schematic diagram of programming multiple entity units in a certain entity management unit according to an exemplary embodiment of the present invention.

Referring to FIG. 11 , an entity management unit 1110 includes a plurality of entity units 1110 ( 0 )˜1110 (D). For example, D can be a positive integer such as 8, 16, 32, etc., which is not limited in the present invention. In an exemplary embodiment, the physical units 1110(0)˜1110(D) belonging to the physical management unit 1110 can be erased synchronously. In addition, the physical units 1110(0)˜1110(D) are programmed alternately.

In an exemplary embodiment, when storing data into the physical management unit 1110 , the physical units 1110 ( 0 )˜1110 (D) may sequentially execute multi-stage programming operations according to the numbers marked in FIG. 11 . For example, certain write data (also referred to as first data) may be temporarily stored in the buffer memory 610 in FIG. 6 . According to the first data in the buffer memory 610, the first-stage programming operation of the physical unit 1110(0) can be executed (corresponding to number 1 in FIG. 11 ). After performing the first-stage programming operation of the physical unit 1110 ( 0 ), another write data (also referred to as second data) may be temporarily stored in the buffer memory 610 . According to the second data in the buffer memory 610, the first-stage programming operation of the physical unit 1110(1) can be executed (corresponding to number 2 in FIG. 11 ). After executing the first-stage programming operation of the physical unit 1110(1), according to the first data in the buffer memory 610, the second-stage programming operation of the physical unit 1110(0) can be executed (corresponding to the label in FIG. 11 3). It should be noted that after the second-stage programming operation of the physical unit 1110(0) is completed, it can be determined that the multi-stage programming operation for the physical unit 1110(0) has been completed and the first data has been stored in the physical unit 1110 (0).

After performing the second-stage programming operation of the physical unit 1110(0), another write data (also referred to as third data) may be temporarily stored in the buffer memory 610 of FIG. 6 . Then, according to the third data in the buffer memory 610, the first-stage programming operation of the physical unit 1110(2) can be executed (corresponding to number 4 in FIG. 11 ). After performing the first-stage programming operation of the physical unit 1110(2), the second data may be temporarily stored in the buffer memory 610 of FIG. 6 again. Then, according to the second data in the buffer memory 610, the second-stage programming operation of the physical unit 1110(1) can be executed (corresponding to number 5 in FIG. 11 ). It should be noted that after the second-stage programming operation of the physical unit 1110(1) is completed, it can be determined that the multi-stage programming operation for the physical unit 1110(1) has been completed and the second data has been stored in the physical unit 1110 (1). By analogy, the rest of the entity units in the entity management unit 1110 can be interleavedly programmed to store other data.

In an exemplary embodiment, the available capacity of the buffer memory 610 may be limited by the equipment construction cost. For example, the designer may reduce the available capacity of the buffer memory 610 to reduce the equipment construction cost. Therefore, in an exemplary embodiment, the available space of the buffer memory 610 in FIG. 6 may not be enough to store the first data and the second data at the same time. Or, from another point of view, assuming that each physical unit has a basic capacity, the available capacity of the buffer memory 610 may be less than twice the basic capacity. If the available capacity of the buffer memory 610 is less than twice the basic capacity, the available space of the buffer memory 610 is also not enough to store the first data and the second data at the same time.

According to the exemplary embodiment of FIG. 11 , the first data is used to perform multi-stage programming operations (corresponding to labels 1 and 3) for the physical unit 1110(0), and the second data is used to perform the multi-stage programming operation for the physical unit 1110( 1) Multi-stage programmatic operation (corresponding to labels 2 and 5). If the available space of the buffer memory 610 is not enough to store the first data and the second data at the same time, when programming the physical units 1110(0) and 1110(1), they are temporarily stored in the buffer memory 610 for execution At least a part of the first data of the first-stage programming operation (corresponding to label 1 in FIG. 11 ) for the physical unit 1110(0) may be used to perform the first-stage programming for the physical unit 1110(1). The second data overwriting of operation (corresponding to reference numeral 2 of FIG. 11 ). Therefore, after executing the first-stage programming operation (corresponding to label 2 in FIG. 11 ) for the physical unit 1110(1), the buffer memory 610 may not have complete first data for the physical unit 1110(0) The second stage of the programming operation (corresponding to the label 3 in FIG. 11 ) is used.

In an exemplary embodiment of FIG. 11 , after executing the first-stage programming operation (corresponding to label 2 in FIG. 11 ) of the physical unit 1110(1), the first data can be read again and temporarily stored in the buffer memory 610. For example, if the first data is immediate data from the host system 11 of FIG. 1 , the first data may be received from the host system 11 again. Alternatively, if the first data is data read from a certain physical unit in the storage area 710 in FIG. 7 , the first data may be read from the physical unit again. After re-temporarily storing the first data in the buffer memory 610, according to the first data in the buffer memory 610, the second-stage programming operation of the physical unit 1110(0) can be executed (corresponding to label 3 in FIG. 11 ). Similarly, after the re-read first data is temporarily stored in the buffer memory 610, at least a part of the second data in the buffer memory 610 may be overwritten. Therefore, in an exemplary embodiment of FIG. 11 , before performing the second-stage programming operation (corresponding to reference number 5 of FIG. 11 ) on the physical unit 1110(1), the second data may be received again from the host system 11 ( or re-read from a certain physical unit) and temporarily stored in the buffer memory 610 for use in the second-stage programming operation on the physical unit 1110(1).

FIG. 12 is a schematic diagram of a data consolidation operation according to an exemplary embodiment of the present invention.

Referring to FIG. 12 , at a specific time point, the memory management circuit 602 may perform a data consolidation operation. For example, this specific time point may be when the idle physical units in the storage area 701 in FIG. 7 are insufficient, when the memory storage device 10 in FIG. 1 is in an idle state, or any time point that meets the set conditions. In an exemplary embodiment, the data consolidation operation is also called a garbage collection operation. After starting the data integration operation, the memory management circuit 602 can send a read command sequence to the rewritable non-volatile memory module 406 of FIG. ) to read valid data. The read valid data (also referred to as collected valid data) can be temporarily stored in the buffer memory 610 . Then, the memory management circuit 602 can send a write command sequence to the rewritable non-volatile memory module 406 of FIG. Entity elements 1220(0)-1220(F) of target node) 1220. After the valid data of a certain entity unit as the source node 1210 is completely stored in the source node 1220, the entity unit (or the entity management unit including the entity unit) can be erased. For example, assuming that according to the valid data from the entity unit 1210(0), the entity unit 1210(0) (or the entities containing the entity unit 1210(0) snap-in) can be erased. The erased physical unit (or physical management unit) can become a new idle physical unit (or idle physical management unit). In other words, through the data consolidation operation, new idle physical units can be released. In addition, if certain conditions are met (for example, sufficient idle physical units are generated), the data consolidation operation can be stopped.

13 to 17 are schematic diagrams showing data consolidation operations according to an exemplary embodiment of the present invention.

Referring to FIG. 13 , it is assumed that in the data consolidation operation, valid data is collected from source nodes 1310 and 1320 and written to the entity management unit 1110 as a recycling node. After starting the data consolidation operation, via the read operation 1301 , the data 1300 is read from at least one of the physical units 1310( 0 )˜1310(G) in the source node 1310 and temporarily stored in the buffer memory 610 . According to the data 1300 read through the read operation 1301 in the buffer memory 610, the first-stage programming operation 1302 can be executed to program the entity unit 1110(0) in the entity management unit 1110 (corresponding to the label 1 in FIG. 13 ).

Referring to FIG. 14 , the entity unit 1110 ( 0 ) programmed by the first-stage programming operation 1302 is marked with a slash. After executing the first-stage programming operation 1302, via the read operation 1401, the data 1400 is read from at least one of the physical units 1320(0)-1320(H) in the source node 1320 and temporarily stored in the buffer memory 610. For example, the data 1400 may overwrite at least a part of data of the data 1300 originally stored in the buffer memory 610 . According to the data 1400 read in the buffer memory 610 via the read operation 1401 , the first-stage programming operation 1402 may be performed to program the physical unit 1110 ( 1 ) (corresponding to label 2 in FIG. 14 ).

Referring to FIG. 15 , the entity unit 1110 ( 1 ) programmed by the first-stage programming operation 1402 is marked with a slash. After executing the first-stage programming operation 1402, via the read operation 1501, the data 1300 is read from at least one of the physical units 1310(0)-1310(G) in the source node 1310 again and temporarily stored in buffer memory 610 . For example, the data 1300 may overwrite at least a part of data of the data 1400 originally stored in the buffer memory 610 . According to the data 1300 read in the buffer memory 610 through the read operation 1501 , the second-stage programming operation 1502 may be performed to reprogram the physical unit 1110 ( 0 ) (corresponding to reference numeral 3 in FIG. 15 ).

It should be noted that the read operation 1301 in FIG. 13 and the read operation 1501 in FIG. 15 read the data 1300 from the same physical unit. For example, if the read operation 1301 reads the data 1300 from the physical unit 1310(0), then the read operation 1501 also reads the data 1300 from the physical unit 1310(0). In other words, the read operations 1301 and 1501 read the data 1300 stored at the same physical address. Or, viewed from another perspective, the data 1300 repeatedly read from the same physical unit via the read operations 1301 and 1501 can be used to perform a multi-stage programming operation on the physical unit 1110(0).

Referring to FIG. 16 , the entity unit 1110 ( 0 ) programmed by the second-stage programming operation 1502 is marked with the bottom of the grid. After performing the second-stage programming operation 1502, via the read operation 1601, the data 1600 is read from at least one of the entity units 1610(0)˜1610(1) in another source node 1610 and temporarily stored to buffer memory 610. For example, the data 1600 may overwrite at least a part of data of the data 1300 originally stored in the buffer memory 610 . According to the data 1600 read in the buffer memory 610 through the read operation 1601 , the first-stage programming operation 1602 may be performed to program the physical unit 1110(2) (corresponding to the reference numeral 4 in FIG. 16 ).

Referring to FIG. 17 , the entity unit 1110 ( 2 ) programmed by the first-stage programming operation 1602 is marked with a slash. After performing the first-stage programming operation 1602, via the read operation 1701, the data 1400 is read from at least one of the physical units 1320(0)-1320(H) in the source node 1320 again and temporarily stored in buffer memory 610 . For example, the data 1400 may overwrite at least a part of data of the data 1600 originally stored in the buffer memory 610 . According to the data 1400 read through the read operation 1701 in the buffer memory 610, the second-stage programming operation 1702 may be performed to reprogram the physical unit 1110(1) (corresponding to the reference numeral 5 in FIG. 17 ).

It should be noted that the read operation 1401 in FIG. 14 and the read operation 1701 in FIG. 17 read the data 1400 from the same physical unit. For example, if the read operation 1401 reads the data 1400 from the physical unit 1320(0), then the read operation 1701 also reads the data 1400 from the physical unit 1320(0). In other words, the read operations 1401 and 1701 read the data 1400 stored at the same physical address. Or, viewed from another perspective, data 1400 repeatedly read from the same physical unit via read operations 1401 and 1701 may be used to perform a multi-stage programming operation on physical unit 1110(1). By analogy, more valid data can be collected from the source node and stored in the entity management unit 1110 as a recycling node. In addition, the use of the entity management unit 1110 in the exemplary embodiments of FIG. 13 to FIG. 17 is the same or similar to the use of the entity management unit 1110 in the exemplary embodiment of FIG. 11 .

In an exemplary embodiment, the memory management circuit 602 also records read information related to the read of the physical unit in a management table. The read information may reflect whether a physical unit serving as the source node has been read for one or more read operations (or a preset number of times).

Taking the exemplary embodiment of FIG. 13 as an example, assume that when the data integration operation is first performed, the read information corresponding to the entity unit 1310(0) in the management table is an initial read flag (for example, a value of 0). After the data 1300 is read from the physical unit 1310(0) via the read operation 1301, the read information corresponding to the physical unit 1310(0) may be updated. For example, the read information corresponding to entity unit 1310(0) may be updated in the management table as the first read flag (for example, a value of 1), to reflect that entity unit 1310(0) has passed Read operation 1301 reads. In the exemplary embodiment of FIG. 15 , after the data 1300 is read again from the physical unit 1310 ( 0 ) via the read operation 1501 , the read information corresponding to the physical unit 1310 ( 0 ) may be updated again. For example, the read information corresponding to entity unit 1310(0) may be updated in the management table to a second read flag (for example, a value of 2) to reflect that entity unit 1310(0) has passed A read operation 1501 reads. Or, from another point of view, the initial read flag corresponding to the entity unit 1310(0) may reflect that the entity unit 1310(0) has not been read in the data integration operation; ) may reflect that the physical unit 1310(0) was read once in the data consolidation operation; and/or the second read flag corresponding to the physical unit 1310(0) may reflect that the physical unit 1310(0) was read twice in the data consolidation operation. In addition, in an exemplary embodiment, the read information corresponding to the physical unit 1310(0) may only include an initial read flag and a second read flag to reflect whether the physical unit 1310(0) is in the data And the operation is read twice.

In an exemplary embodiment, the memory management circuit 602 may determine whether to erase the physical unit according to the read information corresponding to the physical unit. For example, after performing the data consolidation operation, the memory management circuit 602 may determine whether the read information corresponding to a certain physical unit is the second read flag. If the read information corresponding to the physical unit is the second read flag, it means that the physical unit has been read twice in the data consolidation operation, so the memory management circuit 602 can instruct to erase the physical unit. On the contrary, if the read information corresponding to this physical unit is not the second read flag, it means that this physical unit has not been read twice in the data integration operation, so the memory management circuit 602 may not instruct to erase this physical unit unit. For example, in the exemplary embodiment of FIG. 13, the physical unit 1310(0) is only read once to provide the data 1300 for the first-stage programming operation 1302, and the memory management circuit 602 may correspond to the physical unit 1310( 0) without erasing the physical unit 1310(0). In the exemplary embodiment of FIG. 15 , the physical unit 1310(0) is read a second time to provide the data 1300 for the second-stage programming operation 1502, so the memory management circuit 602 can operate according to the data corresponding to the physical unit 1310(0) ) to erase the physical unit 1310(0).

It should be noted that, in the aforementioned exemplary embodiments, a certain memory cell that has undergone multi-stage programming operations can store 3 or 4 bits. However, in another exemplary embodiment, a certain memory cell that has undergone the multi-stage programming operation may store more or less bits (for example, 2 or 8 bits), which is not limited by the present invention. In addition, a multi-stage programming operation may include more stages of programming operations, not limited to the first-stage programming operation and the second-stage programming operation. For example, in an exemplary embodiment of FIG. 8 , it can be considered that the executed multi-stage programming operation includes a first-stage programming operation, a second-stage programming operation, and a third-stage programming operation. The first phase programming operation is used to program memory cells to belong to states 801 and 802 . The second phase programming operation is used to program the memory cells to belong to the states 811 - 814 . The third-stage programming operation is used to program the memory cells to belong to the states 821-828. In an exemplary embodiment, a physical unit may also be read more times (for example, 3 times or 4 times) to perform the third-stage programming operation or the fourth-stage programming operation.

FIG. 18 is a flow chart of a data consolidation method according to an exemplary embodiment of the present invention.

Referring to FIG. 18 , in step S1810 , the data integration operation is started. In step S1820, a data integration operation is performed. Step S1820 includes steps S1821-S1824. In step S1821, the first data is read from the first physical unit via a first read operation. In step S1822, a first-stage programming operation is performed on the second entity unit according to the first data. In step S1823, the first data is read from the first physical unit again via the second read operation. In step S1824, a second-stage programming operation is performed on the second physical unit according to the first data read through the second read operation. In step S1830, the data integration operation ends.

However, each step in FIG. 18 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 18 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method in FIG. 18 can be used in combination with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

To sum up, in the data consolidation operation, the same data in the first physical unit can be read at least twice, so as to complete the multi-stage for the second physical unit according to the data read through different read operations Programmatic operation. Thereby, even if the available space of the buffer memory in the memory storage device is reduced due to cost considerations, the multi-stage programming operation for a single physical unit can be successfully completed without additionally increasing the capacity of the buffer memory. In an exemplary embodiment, the above-mentioned mechanism of performing multiple data read operations on the same physical unit to complete the multi-stage programming operation can also effectively improve the performance of the memory storage device for a memory controller with a small buffer memory capacity (or control chip) compatibility.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention is defined by the claims.

Claims (21)

1. A data consolidation method for a memory storage device comprising a plurality of physical units, and the data consolidation method comprising:

performing a data merge operation to store valid data collected from the source node to the reclamation node,

wherein the source node comprises at least a first entity unit of the plurality of entity units, the recovery node comprises a second entity unit of the plurality of entity units, and

the data merging operation includes:

reading first data from the at least one first physical unit via a first read operation;

performing a first-stage programming operation on the second entity unit according to the first data;

after the first-stage programming operation is executed, the first data is read from the at least one first entity unit again through a second reading operation; and

and performing a second-stage programming operation on the second entity unit according to the first data read through the second reading operation.

2. The data consolidation method of claim 1, wherein the source node further comprises at least a third entity unit of the plurality of entity units, the reclamation node further comprises a fourth entity unit of the plurality of entity units, and the data consolidation operation further comprises:

reading second data from the at least one third entity unit; and

and programming the fourth entity unit according to the second data between the first-stage programming operation and the second-stage programming operation.

3. The data consolidation method of claim 1, wherein the data consolidation operation further comprises:

temporarily storing the first data read through the first read operation in a buffer memory to provide the first data for the first stage programming operation;

temporarily storing second data in the buffer memory, and the second data overwrites at least a portion of the first data read via the first read operation in the buffer memory; and

the first data read via the second read operation is suspended in the buffer memory to provide the first data for the second stage programming operation.

4. The data consolidation method of claim 1, further comprising:

recording read information in a management table, wherein the read information reflects whether the at least one first physical unit is read by at least one of the first read operation and the second read operation; and

and erasing the at least one first entity unit according to the read information.

5. The data consolidation method according to claim 1, wherein the second entity unit is programmed to store the first data via the first stage programming operation and the second stage programming operation in sequence.

6. The data consolidation method according to claim 1, wherein the first stage programming operation and the second stage programming operation belong to a multi-stage programming operation, and one memory cell of the second entity unit programmed by the multi-stage programming operation stores not less than 3 bits.

7. The data consolidation method of claim 1, further comprising:

temporarily storing the first data read by the first reading operation or the second reading operation in a buffer memory,

wherein the second entity unit has a basic capacity and the available capacity of the buffer memory is less than twice the basic capacity.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module including a plurality of physical units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to perform a data merging operation to store valid data collected from the source node to the reclamation node,

the source node includes at least one first entity unit of the plurality of entity units, the recovery node includes a second entity unit of the plurality of entity units, and

the data merging operation includes:

sending a first read instruction sequence to instruct to read first data from the at least one first entity unit via a first read operation;

transmitting a first write instruction sequence to instruct the second entity unit to execute a first stage programming operation according to the first data;

after the first-stage programming operation is performed, sending a second read instruction sequence to instruct to read the first data from the at least one first entity unit again through a second read operation; and

A second sequence of write instructions is sent to instruct a second-stage programming operation to be performed on the second physical unit in accordance with the first data read via the second read operation.

9. The memory storage device of claim 8, wherein the source node further comprises at least a third entity of the plurality of entity units, the reclamation node further comprises a fourth entity of the plurality of entity units, and the data consolidation operation further comprises:

sending a third read instruction sequence to instruct to read second data from the at least one third entity unit; and

a third sequence of write instructions is sent between the first phase programming operation and the second phase programming operation to instruct programming of the fourth entity unit according to the second data.

10. The memory storage device of claim 8, wherein the data merge operation further comprises:

temporarily storing the first data read through the first read operation in a buffer memory to provide the first data for the first stage programming operation;

temporarily storing second data in the buffer memory, and the second data overwrites at least a portion of the first data read via the first read operation in the buffer memory; and

The first data read via the second read operation is suspended in the buffer memory to provide the first data for the second stage programming operation.

11. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to record read information in a management table and erase the at least one first physical unit according to the read information, wherein the read information reflects whether the at least one first physical unit is read by at least one of the first read operation and the second read operation.

12. The memory storage device of claim 8, wherein the second entity unit is programmed to store the first data via the first phase programming operation and the second phase programming operation in sequence.

13. The memory storage device of claim 8, wherein the first-stage programming operation and the second-stage programming operation belong to a multi-stage programming operation, and one memory cell of the second physical unit programmed by the multi-stage programming operation stores not less than 3 bits.

14. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to temporarily store the first data read via the first read operation or the second read operation in a buffer memory,

wherein the second entity unit has a basic capacity and the available capacity of the buffer memory is less than twice the basic capacity.

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, wherein the memory control circuit unit comprises:

a host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to perform a data merge operation to store valid data collected from the source node to the reclamation node,

the source node includes at least one first entity unit of the plurality of entity units, the recovery node includes a second entity unit of the plurality of entity units, and

The data merging operation includes:

sending a first read instruction sequence to instruct to read first data from the at least one first entity unit via a first read operation;

transmitting a first write instruction sequence to instruct the second entity unit to execute a first stage programming operation according to the first data;

after the first-stage programming operation is performed, sending a second read instruction sequence to instruct to read the first data from the at least one first entity unit again through a second read operation; and

a second sequence of write instructions is sent to instruct a second-stage programming operation to be performed on the second physical unit in accordance with the first data read via the second read operation.

16. The memory control circuit unit of claim 15, wherein the source node further comprises at least a third entity unit of the plurality of entity units, the reclamation node further comprises a fourth entity unit of the plurality of entity units, and the data merge operation further comprises:

sending a third read instruction sequence to instruct to read second data from the at least one third entity unit; and

a third sequence of write instructions is sent between the first phase programming operation and the second phase programming operation to instruct programming of the fourth entity unit according to the second data.

17. The memory control circuit unit of claim 15, further comprising a buffer memory, wherein the buffer memory is connected to the memory management circuit, and the data merge operation further comprises:

temporarily storing the first data read via the first read operation in the buffer memory to provide the first data for the first stage programming operation;

temporarily storing second data in the buffer memory, and the second data overwrites at least a portion of the first data read via the first read operation in the buffer memory; and

the first data read via the second read operation is suspended in the buffer memory to provide the first data for the second stage programming operation.

18. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to record read information in a management table and erase the at least one first physical unit according to the read information, wherein the read information reflects whether the at least one first physical unit is read by at least one of the first read operation and the second read operation.

19. The memory control circuit unit of claim 15, wherein the second entity unit is programmed to store the first data via the first phase programming operation and the second phase programming operation in sequence.

20. The memory control circuit unit of claim 15, wherein the first-stage programming operation and the second-stage programming operation belong to a multi-stage programming operation, and one memory cell of the second physical unit programmed by the multi-stage programming operation stores not less than 3 bits.

21. The memory control circuit unit of claim 15, further comprising a buffer memory, wherein the buffer memory is connected to the memory management circuit, and the memory management circuit is further configured to store the first data read via the first read operation or the second read operation temporarily in the buffer memory,

wherein the second entity unit has a basic capacity and the available capacity of the buffer memory is less than twice the basic capacity.

Images