CN110828577A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, in particular to a method for reducing contact resistance of N-type FinFET using Sb+ implantation technology and an N-type FinFET device with low contact resistance. The invention forms a semiconductor region on a substrate structure After Sb+ is implanted and activated, metal deposition is performed over the semiconductor region; a peak annealing process is used to form a metal silicide and at the same time make Sb+ segregated, and the concentration peak of the Sb+ segregation is located in the metal silicide and the The concentration in the semiconductor region and the metal silicide decreases sequentially at the interface of the semiconductor region and in a direction away from the interface. The Sb+ and subsequent segregation of the present invention can effectively reduce the height of the Schottky potential barrier, reduce the thickness of the potential barrier, and reduce the contact resistance.

Description

Semiconductor device and method of manufacturing the same

technical field

The present invention relates to the field of semiconductor technology, in particular, to a semiconductor device and a manufacturing method thereof, and more particularly to a method for reducing contact resistance of N-type FinFET using Sb+ injection technology and a FinFET structure with low contact resistance.

Background technique

The semiconductor integrated circuit industry has experienced rapid development. As the integration of integrated circuits continues to increase, the critical dimensions related to semiconductor devices continue to decrease. In order to meet the needs of interconnect lines after the critical dimensions have been reduced, different metal layers are currently Or the conduction between the metal layer and the semiconductor device structure is achieved through the interconnect structure. The interconnect structure includes interconnect lines and contact hole plugs located in the contact holes for connecting semiconductor devices, and the interconnect lines connect plugs on different semiconductor devices to form a circuit.

With the continuous shrinking of integrated circuit process nodes and the reduction of device size, the surface resistance and contact resistance of the source/drain regions of the Fin Field-Effect Transistor (FinFET, Fin Field-Effect Transistor) device are correspondingly increased, resulting in a corresponding increase in the entire FinFET device. The parasitic resistance increases, as shown in Figure 1, which is a typical FinFET layout, and Figure 2 is a schematic diagram of the parasitic resistance of the device. Due to the existence of parasitic resistance in the FinFET structure, the corresponding speed of the device is reduced, and the signal A delay occurs. At present, in order to reduce the contact resistance between the contact hole plug and the doped epitaxial layer, a metal silicide process has been introduced. Metal silicide (such as Mo, Ta, Ti, Ni metal silicide) Reduce contact resistance, thereby increasing drive current.

However, the reduction of contact resistance by metal silicide is limited, and it is necessary to further reduce the contact resistance.

SUMMARY OF THE INVENTION

In view of this, the present invention provides a semiconductor device and a method for manufacturing the same, the method for reducing the contact resistance of an N-type FinFET using Sb+ implantation technology, and the semiconductor device has a smaller contact resistance.

The technical scheme provided by the present invention is as follows:

A method of manufacturing a semiconductor device, comprising the steps of:

Step S1: forming a semiconductor region on the substrate structure;

Step S2: performing antimony ion (Sb+) implantation in the semiconductor region and activating it;

Step S3: metal deposition is performed on the semiconductor region;

Step S4: adopting a peak annealing process to form a metal silicide and at the same time make Sb+ segregated. the concentration in the semiconductor region and the metal silicide sequentially decreases in a direction;

Step S5: forming a metal nitride barrier layer on the metal silicide;

Step S6: forming metal plugs on the metal nitride barrier layer.

Further, the semiconductor region in the step S2 is an N-type source/drain region formed by an epitaxial semiconductor layer and an N-type heavy doping implantation process, and also has a gate structure between the N-type source/drain regions .

Further, the implantation energy of the Sb+ implantation in the step S2 is 10-20 kiloelectron volts (KeV), and the implantation dose is 1E12-2E14 atoms/square centimeter (atoms/cm ² ).

Further, within this implant dose range, the larger the implant dose of Sb+, the more obvious reduction in the height and width of the Schottky barrier compared to the Sb+ implant with a small implant dose;

Further, within this implant dose range, the increase of the Sb+ doping concentration can reduce the resistance of the metal silicide.

Further, within this implant dose range, the saturation current (Idsat) of the semiconductor device can be increased by 4-12% compared to the undoped Sb+.

Further, the activation process in the step S2 is an annealing process at 800-1200°C for 40-60 seconds (s); the temperature of the peak annealing is 400-600°C, and the annealing time is 20-50 seconds (s). ) to form 15-25 nanometer (nm) metal silicides.

Further, between the step S2 and the step S3, there are also the following steps: depositing an interlayer dielectric layer covering the substrate and the surface structure, and forming a contact exposing the semiconductor region through photolithography and etching processes holes, and then the metal deposition is performed over the exposed semiconductor regions.

Further, the metal is Ti, Ni, Pt, Ta or Co, the metal barrier layer is TiN, and the metal plug is a tungsten plug.

Further, the specific process of forming the metal plug is to deposit the metal covering the interlayer dielectric layer and fill the contact hole, and then use a chemical mechanical polishing (CMP, Chemical Mechanical Polishing) process to remove the interlayer. The metal on the surface of the dielectric layer forms a metal plug.

Meanwhile, the present invention also discloses a semiconductor device, which specifically includes the following structures:

A semiconductor region over the substrate structure, the semiconductor region being Sb+ implanted and activated, having a metal silicide over the surface of the semiconductor region, at the interface between the metal silicide and the semiconductor region has a concentration peak of Sb+ segregation and successively decreasing said concentration in said semiconductor region and said metal silicide in a direction away from said interface; has metal nitride barrier over said metal silicide surface layer; having a metal plug over the metal nitride barrier layer.

Further, the semiconductor region is an N-type source/drain region formed by an epitaxial semiconductor layer and an N-type heavy doping implantation process, and also has a gate structure between the N-type source/drain regions.

Further, the semiconductor structure further includes an interlayer dielectric layer, the metal plug is formed in a contact hole in the interlayer dielectric layer, the metal nitride barrier layer is TiN, and the metal plug is Tungsten plug.

Further, the Sb+ implantation dose is 1E12-2E14 atoms/cm ² .

Further, within this implant dose range, the greater the implant dose of Sb+, the more obvious reduction in the height and width of the Schottky barrier compared to the Sb+ implant with a small implant dose.

Further, within this implant dose range, the increase of the Sb+ doping concentration can reduce the resistance of the metal silicide.

Further, within this implant dose range, the saturation current (Idsat) of the semiconductor device can be increased by 4-12% compared to the undoped Sb+.

Segregation in the present invention refers to a phenomenon in which the concentration peak of impurities is located at the interface between the metal silicide and the semiconductor region.

Since the Sb+ implantation is after the N-type heavily doped source/drain doping step, and the implanted ions of the N-type source/drain implantation are phosphorus or arsenic, the previous N-type doping implantation is close to the solid solution limit, and phosphorus ions (P+) It is not easy to achieve doping and segregation with arsenic ions (As+), so Sb, a metal element that is compatible with the existing preparation process and will not change the shape of the existing film layer, is selected as the element for implantation and segregation. The Sb+ implantation and subsequent segregation of the present invention can effectively reduce the height of the Schottky potential barrier, reduce the thickness of the potential barrier, and reduce the contact resistance.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

Figure 1 shows a typical FinFET layout.

FIG. 2 is a schematic diagram of parasitic resistance of a conventional device.

Figure 3 shows the Schottky diode current transfer mechanism.

Figure 4 shows the ohmic contact current transfer mechanism.

5-12 are cross-sectional views of the fabrication of the semiconductor device shown in the present invention.

Figure 13 shows the segregation distribution of Sb+ with different doping concentrations when forming Sb+ segregation.

Figure 14 shows the effect of doping with different Sb concentrations in the depletion region on the height and width of the Schottky barrier.

Figure 15 shows the Fermi level as a function of donor and acceptor concentrations.

Figure 16 shows the effect of different doping concentrations of Sb on the resistance of metal silicides.

Reference signs: 1-substrate structure; 2-epitaxial semiconductor layer; 01-N-type heavy doping implantation; 3-gate structure; 02-Sb+ ion implantation; 4-interlayer dielectric layer; 5-contact hole; 6 - metal silicide layer; 7 - metal nitride barrier layer; 8 - metal layer; 9 - metal plug.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present invention.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

The inventors have found through research that, as mentioned above, the existing integrated circuit process nodes continue to shrink and the device size decreases, and the surface resistance and contact resistance of the source/drain regions of the FinFET device are correspondingly increased, resulting in the entire FinFET device. The parasitic resistance increases, as shown in the schematic diagram of the parasitic resistance composition of the device shown in FIG. 2 , as the contact resistance Rc increases, the entire parasitic resistance will increase.

According to the two current transfer mechanisms shown in Figure 3-4 (Figure 3 is the Schottky diode current transfer mechanism, Figure 4 is the ohmic contact current transfer mechanism), it can be seen that in the case of lightly doped Schottky diodes, the consumption The exhaust area is wider, and the n-Si electrons gain energy to climb above the Schottky barrier height to form current transport, in this case, increasing the ability of current transport, reducing current obstruction (reducing contact resistance) The method is to reduce the height of the potential barrier; in addition, in the case of heavily doped ohmic contacts, the depletion region is narrow, and electrons may tunnel through the potential barrier to form current transmission. In this case, the ability of current transmission is increased, A way to increase the probability of electron tunneling (ie, reduce contact resistance) is to "shrink" the barrier width.

Fig. 5-12 is a cross-sectional view of the structure in the fabrication process of the semiconductor device in the present invention, wherein the cross-sectional direction of the FinFET shown in Fig. 5-12 is the cross-section cut along the direction of the fin in the FinFET layout shown in Fig. 1 picture.

As shown in FIG. 5 , a substrate structure 1 is first provided, and the substrate structure 1 is a silicon substrate. In other embodiments, the material of the substrate structure may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate structure may also be a silicon-on-insulator substrate Or other types of substrates such as germanium-on-insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.

A semiconductor region 2 is formed on the substrate structure 1. The specific formation process of the semiconductor region 2 is as follows: forming a groove structure on the substrate structure 1, and then forming a semiconductor material layer in the groove structure through a selective epitaxy process, In this embodiment, the semiconductor material layer is SiP, and in other embodiments, a similar material such as Si or SiC can also be selected. Then, an N-type heavy doping implantation process 01 is performed on the epitaxially formed semiconductor material layer to form an N-type source/drain structure (semiconductor region). The impurity implanted in the N-type source/drain is phosphorus or arsenic, and the implantation process adopts a common implantation process in the art, which is not further limited here. Before the N-type source/drain structure is formed, a gate structure 3 is further formed on the substrate structure 1. The gate structure 3 includes a gate stack structure and sidewall spacers. The gate stack structure may include a polysilicon gate or a metal gate. and the gate dielectric layer under the gate, the gate dielectric layer may be a high-K dielectric layer material common in the art.

After the N-type source/drain structure is formed, as shown in FIG. 6 , an antimony ion Sb+ ion implantation process 02 is performed over the semiconductor region, the implantation energy of Sb+ is 10-20KeV, and the implantation dose is 1E12-2E14 atoms/cm ² , After the Sb+ implantation process, ion activation (activation) is performed, and the ion activation process is an annealing process at 800-1200° C. for 40-60s. This activation process follows the Sb+ implantation process. It also has an annealing process, but the subsequent metal silicidation annealing process has a lower temperature (below 600 ° C), and the activation rate of the ions is lower at a lower temperature, and the subsequent high temperature annealing process after the antimony ion Sb+ implantation process can be efficient. of activated Sb+ ions.

Since the Sb+ implantation is after the N-type source/drain doping step, and the implanted ions of the N-type source/drain implantation are phosphorus or arsenic, the previous N-type heavy doping implantation is close to the solid solution limit, and phosphorus ions (P+) and arsenic are implanted. It is not easy to achieve doping and segregation of ions (As+), so Sb, a metal element that is compatible with the existing preparation process and will not change the shape of the existing film layer, is selected as the element for implantation and segregation.

As a comparative example, the present invention compares the implanted Sb+ with different doses, namely light doping (doping concentration 1E12-9E12 atoms/cm ² ), medium doping (doping concentration 1E13-9E13 atoms/cm ² ) and heavy doping Doping (1.1E14-2E14atoms/cm ² ), the effect of different concentrations of Sb+ implantation on device performance will be further described later.

Then, as shown in FIG. 7 , an interlayer dielectric layer 4 covering the entire surface of the substrate structure 1 is formed above the substrate structure 1. The material of the interlayer dielectric layer can be selected from common insulating materials in the field, and the formation process can be For the coating or deposition process, no further limitation is made here.

As shown in FIG. 8 , a photolithography and etching process are then used to form a contact hole 5 in the interlayer dielectric layer 4 exposing the upper part of the semiconductor region. The specific process steps are to first coat a layer of photoresist, then cure, after exposure and development, an opening corresponding to the contact hole pattern is formed on the photoresist to expose the interlayer dielectric layer, and then a dry or wet etching process is used. The exposed interlayer dielectric layer is etched to form contact holes 5, and then the remaining photoresist is removed by ashing. Then, the inside of the contact hole structure is cleaned to remove residues inside the contact hole, and the top of the exposed semiconductor region is dried by blowing to facilitate subsequent deposition steps.

Then, a metal layer is deposited on the surface of the exposed semiconductor region, and a chemical vapor deposition or physical vapor deposition process can be used. The deposited metal layer can be Ti, Ni, Pt, Ta or Co, and then a spike annealing process (Spikeanneal) is used. At the same time of metal silicide, Sb+ is segregated. The annealing temperature of the peak annealing process is 400-600° C., the annealing time is 20-50S, and the thickness of the metal silicide is 15-25 nm. As shown in FIG. 9, the metal silicide 6 is formed on the surface of the semiconductor region structure. The mechanism of Sb+ coagulation and contact resistance reduction will be further elaborated in the follow-up. Segregation in this scheme refers to a phenomenon in which the concentration peak of impurities is located at the interface between the metal silicide and the semiconductor region.

As shown in FIG. 10 , after the metal silicide is formed, a metal nitride barrier layer 7 is formed on the surface of the metal silicide 6 . On the one hand, the function of the metal nitride barrier layer can prevent the reactant used in the subsequent formation of the metal plug in the contact hole 5 from reacting with the semiconductor material in the semiconductor region, and can also prevent the metal plug material used from reacting with the semiconductor material in the semiconductor region. The formed metal silicide layer 6 reacts; on the other hand, the metal nitride barrier layer 7 is used to improve the adhesion of the metal material in the contact hole 5 when the contact hole plug is subsequently formed. In this embodiment, the material of the metal nitride barrier layer 7 is TiN.

Then, metal is deposited in the contact hole 5 and on the surface of the interlayer dielectric layer 4, as shown in FIG. 11 . The deposition process may be chemical vapor deposition or physical vapor deposition, and the metal selected in this embodiment is tungsten. Then, as shown in FIG. 12 , a grinding process is used to remove excess metal on the surface of the interlayer dielectric layer 4 to form a FinFET structure with a contact structure. The grinding process used is chemical mechanical grinding process.

In the present invention, the Sb implanted with different doses is compared, and there are light doping (doping concentration 1E12-9E12 atoms/cm ² ), medium doping (doping concentration 1E13-9E13 atoms/cm ² ) and heavy doping (1.1 E14-2E14 atoms/cm ² ), the Sb distribution after partial condensation is shown in Fig. 13 . The concentration peak of the Sb+ segregation is located at the interface of the metal silicide and the semiconductor region, and the concentrations in the semiconductor region and the metal silicide in a direction away from the interface are sequentially decreases, and the concentration of Sb+ segregation decreases faster in metal silicides than in semiconductor regions (the curve is steeper in metal silicides), Sb+ segregation helps reduce Schottky Barrier. Specifically, as shown in Figure 14, combined with the current transfer mechanism shown in Figures 3-4, in the depletion region, the corresponding solid line or dotted line in the figure corresponds to no Sb doping, light doping, medium doping and heavy doping, respectively. The conduction band in the four cases of doping, the conduction band becomes steeper and lower with the increase of doping concentration, that is, the height and width of the corresponding Schottky barrier decrease. Combined with the current transport mechanism It can be seen that the reduction of the height of the Schottky barrier can make the energy required for the electron transition less and less, and the electrons are more and more likely to "climb" the height of the barrier; and the steepness increases, which means that the barrier "changes" Thinner, which increases the possibility of tunneling and increases the number of electrons to tunnel. Either a reduction in the barrier height or a thinning of the barrier width can increase the probability of electrons "flowing" and reduce the obstruction of current flow (reduce contact resistance).

And the relationship between the Fermi level and the concentration of the donor and the acceptor shown in Figure 15 can also explain the change of the potential barrier. Sb is a group V n-type element. With the partial condensation of Sb+, at the interface and at the interface There are many n-type impurities nearby. When the n-type impurities increase, the Fermi level moves to the conduction band and the distance between Ef and Ec decreases. As shown in Figure 14, the conduction band bends downward, that is, the relative barrier height. The reduction of , and the narrowing (thinning) of the barrier width at the same time make it easier for electrons to transition.

And according to the formula for the Fermi level:

where n ₀ is the number of electrons in a certain energy state, N _c is the total number of electrons, k is the Boltzmann constant, and T is the temperature. It can be seen from this formula that as the distance from Ef to Ec decreases, in a certain energy state The number of electrons in the energy state increases, the number of electrons increases, the probability of electron transition and electron tunneling is greater, and the contact resistance is reduced.

At the same time, with the implantation of Sb, since there is a certain concentration of Sb element in the metal silicide when Sb+ is segregated, by comparing the four elements of undoped Sb, lightly doped Sb, medium doped Sb and heavily doped Sb The effect on the resistance of metal silicide in the embodiment can be seen, as shown in FIG. 16 , with the increase of Sb doping concentration, the resistance of metal silicide can be slightly reduced, and the contact resistance Rc can be further reduced. to reduce parasitic resistance.

And by comparing the saturation current (Idsat) of the FinFET transistor, as shown in the table below, it can also be seen that with the increase of the Sb impurity concentration, the Idsat increases by 12% when Sb is heavily doped compared to when there is no Sb doping. It is reflected from one side that the contact resistance can be reduced.

Undoped Sb Lightly doped Sb Medium doped Sb heavily doped Sb Idsat Idsat+4% Idsat+8% Idsat+12%

It can be seen from this that in the Sb+ doping and segregation process, compared with the embodiments with different doping concentrations, Sb with different doping concentrations can reduce the height of the Schottky barrier, and can make the Schottky barrier "change". This can effectively reduce the contact resistance of FinFET, and the higher the doping concentration, the more obvious the reduction in the height and width of the Schottky barrier, and the more obvious the effect of reducing the contact resistance. At the same time, Sb doping can also reduce metal silicidation. The resistance of the metal silicide decreases with increasing Sb doping concentration, and by comparing the saturation current (Idsat) of the FinFET transistor, the heavily doped (1.1E14-2E14 atoms/cm ² ) Sb relative to the undoped Sb can be improved by 12%. From the above, it can be seen that the method for forming the semiconductor device as a whole can reduce the contact resistance and further reduce the parasitic resistance.

Meanwhile, the present invention also provides a semiconductor structure as shown in FIG. 12, which includes the following structures:

The semiconductor region 2 located above the substrate structure 1, the semiconductor region 2 has undergone Sb+ implantation and activation treatment, and has a metal silicide 6 above the surface of the semiconductor region 2, and the metal silicide 6 and the semiconductor are The interface between regions 2 has a concentration peak of Sb+ segregation, and the concentration in the semiconductor region and the metal silicide decreases sequentially in the direction away from the interface; in the metal silicide 6 with a metal nitride barrier layer 7 above the surface; with a metal plug 9 above the metal nitride barrier layer 7; when the implantation dose of Sb+ is in the range of 1.1E14-2E14 atoms/cm ² , the Schottky barrier height and The width is more obviously reduced compared to the Sb+ implantation with a small implant dose; and the semiconductor region 2 is an N-type source/drain region formed by an epitaxial semiconductor layer and implanted by N-type heavy doping, and the N-type source/drain region is located in the N-type source/drain region. There is a gate structure 3 therebetween; the semiconductor structure further includes an interlayer dielectric layer 4, the metal plug 9 is formed in the contact hole in the interlayer dielectric layer 4, and the metal nitride barrier layer is TiN, the metal plug is a tungsten plug; at the same time, the increase of the Sb+ doping concentration can reduce the resistance of the metal silicide, and when the implantation dose is 1.1E14-2E14 atoms/cm ² , the semiconductor device has a The saturation current (Idsat) can be increased by 12% compared to the undoped Sb+.

To sum up, in the present invention, the N-type heavily doped source/drain doping step is followed by a Sb+ implantation step, since the Sb+ implantation is after the N-type source/drain doping step, and the N-type source/drain doping step The implanted ions are phosphorus or arsenic. The previous N-type heavy doping implantation is close to the solid solution limit. It is not easy to achieve doping and partial condensation of phosphorus ions (P+) and arsenic ions (As+). Compatible with the process, the metal element Sb that will not change the morphology of the existing film layer is used as the element for implantation and segregation. In the Sb+ doping and segregation process, compared with the embodiments with different doping concentrations, Sb+ with different doping concentrations can reduce the height of the Schottky barrier, and can make the Schottky barrier "thinner", so that It can effectively reduce the contact resistance of FinFET, and the higher the doping concentration, the more obvious the reduction of Schottky barrier height and width, and the more obvious the effect of reducing contact resistance. At the same time, Sb+ doping can also reduce the resistance of metal silicide, And with the increase of Sb+ doping concentration, the resistance of metal silicide decreases, and by comparing the saturation current (Idsat) of FinFET transistors, heavily doped (1.1E14-2E14 atoms/cm ² ) Sb can be improved relative to undoped Sb 12%. Therefore, the semiconductor device formed by this method can reduce the contact resistance of the device and further reduce the parasitic resistance.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (17)

1. a manufacturing method of a semiconductor device, is characterized in that, comprises the following steps: Step S1: forming a semiconductor region on the substrate structure; Step S2: performing antimony ion Sb+ implantation in the semiconductor region and activating it; Step S3: metal deposition is performed on the semiconductor region; Step S4: adopting a peak annealing process to form a metal silicide and at the same time make Sb+ segregated. the concentration in the semiconductor region and the metal silicide sequentially decreases in a direction; Step S5: forming a metal nitride barrier layer on the metal silicide; Step S6: forming metal plugs on the metal nitride barrier layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor region in the step S2 is an N-type source/drain region formed by an epitaxial semiconductor layer and an N-type heavy doping implantation process, and There is also a gate structure between the N-type source/drain regions. 3 . The method for manufacturing a semiconductor device according to claim 1 , wherein the Sb+ injection in the step S2 has an injection energy of 10-20 keV, and an injection dose of 1E12-2E14 atoms/square. 4 . centimeter. 4 . The method for manufacturing a semiconductor device according to claim 3 , wherein, within the implant dose range, the larger the implant dose of Sb+ is, the lower the Schottky barrier height and width are compared to the Sb+ implant with a small implant dose. 5 . more obvious. 5 . The method for manufacturing a semiconductor device according to claim 3 , wherein, within the implant dose range, the resistance of the metal silicide can be reduced with the increase of the Sb+ doping concentration. 6 . 6 . The method for manufacturing a semiconductor device according to claim 3 , wherein, within the implant dose range, the saturation current Idsat of the semiconductor device is increased by 4-12% compared to the undoped Sb+. 7 . 7 . The method for manufacturing a semiconductor device according to claim 1 , wherein the activation process in the step S2 is an annealing process at 800-1200° C. for 40-60 seconds; the temperature of the peak annealing is 400° C. 8 . -600°C with annealing time of 20-50 seconds to form a metal silicide of 15-25 nm. 8 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the following steps between the step S2 and the step S3 : depositing an interlayer dielectric layer covering the substrate and the surface structure, and A contact hole exposing the semiconductor region is formed through a photolithography and etching process, and then the metal deposition is performed on the exposed semiconductor region. 9 . The method for manufacturing a semiconductor device according to claim 8 , wherein the metal is Ti, Ni, Pt, Ta or Co, the metal barrier layer is TiN, and the metal plug is a tungsten plug. 10 . . 10 . The method for manufacturing a semiconductor device according to claim 1 , wherein the specific process of forming the metal plug is to deposit a metal covering the interlayer dielectric layer and fill the contact hole, and then using The chemical mechanical polishing process CMP removes the metal on the surface of the interlayer dielectric layer to form metal plugs. 11. A semiconductor device, characterized in that it comprises the following structures: A semiconductor region over the substrate structure, the semiconductor region being Sb+ implanted and activated, having a metal silicide over the surface of the semiconductor region, at the interface between the metal silicide and the semiconductor region has a concentration peak of Sb+ segregation and successively decreasing said concentration in said semiconductor region and said metal silicide in a direction away from said interface; has metal nitride barrier over said metal silicide surface layer; having a metal plug over the metal nitride barrier layer. 12. The semiconductor device according to claim 11, wherein the semiconductor region is an N-type source/drain region formed by an epitaxial semiconductor layer and an N-type heavy doping implantation process, and the N-type source/drain region is formed in the N-type source/drain region. There is also a gate structure between the drain regions. 13 . The semiconductor device according to claim 11 , wherein the semiconductor structure further comprises an interlayer dielectric layer, the metal plug is formed in a contact hole in the interlayer dielectric layer, and the metal plug is formed in the contact hole. 14 . The nitride barrier layer is TiN, and the metal plug is a tungsten plug. 14 . The semiconductor device according to claim 11 , wherein the Sb+ implantation dose ranges from 1E12 to 2E14 atoms/cm 2 . 15 . 15 . The semiconductor device according to claim 14 , wherein, within the implant dose range, the larger the implant dose of Sb+ is, the greater the reduction in Schottky barrier height and width relative to the Sb+ implant with a small implant dose. 16 . 16 . The semiconductor device of claim 14 , wherein, within the implant dose range, an increase in the Sb+ doping concentration can reduce the resistance of the metal silicide. 17 . 17 . The semiconductor device according to claim 14 , wherein, within the implant dose range, the saturation current Idsat of the semiconductor device is increased by 4-12% compared to the undoped Sb+. 18 .

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