CN110828485A - A display substrate, its preparation method, and display device - Google Patents

Abstract

The invention discloses a display substrate, a preparation method thereof, and a display device. The display substrate comprises: a base; The first insulating layer on the source layer, the gate and gate signal wirings arranged on the first insulating layer, and the second insulating layer arranged on the gate and gate signal wirings, arranged on the The source-drain electrodes and the auxiliary cathode on the second insulating layer, wherein at least one of the following is satisfied: the thickness of the gate signal trace is greater than the thickness of the gate, and the thickness of the auxiliary cathode is greater than the source-drain extremely thick. In the solution provided in this embodiment, by changing the thickness difference between the gate signal trace and the gate, and the thickness difference between the auxiliary cathode and the source-drain electrode, the drop is reduced, and the depth of the subsequent via holes is reduced, which is beneficial to realize overlap. Improve product quality.

Description

A display substrate, its preparation method, and display device

technical field

The present invention relates to display technology, in particular to a display substrate, a preparation method thereof, and a display device.

Background technique

The top-gate TFT (Thin Film Transistor, thin film transistor) has the characteristics of a short channel, so the on-state current Ion can be effectively increased, so the display effect can be significantly improved and the power consumption can be effectively reduced. In addition, the overlapping area between the gate and the source and drain of the top-gate TFT is small, so the parasitic capacitance generated is small, so the possibility of occurrence of defects such as GDS (Gate Data Short, that is, the short circuit between the gate line and the data line) is also reduced. . Since the top-gate TFT has the above-mentioned remarkable advantages, it has attracted more and more attention.

In recent years, large-scale AMOLED (Active-matrix Organic Light-Emitting Diode) display products have been widely used in TV and other fields due to the advantages of high color gamut, high contrast, and self-illumination. In the production process of large-sized, high-resolution AMOLED display panels such as 8K, due to the extremely high pixel density of 8K display, if the traditional evaporation method combined with bottom emission is still used, the pixel aperture ratio will be too low to meet the brightness requirements, etc. , so the current products mainly use the technology of top emission combined with printing primary color luminescent materials. In order to make the primary color light-emitting material printed on the TFT of the array substrate more uniform and the different colors do not interfere with each other, SOG (Silicon Organic Glass, organosiloxane material) needs to be used to planarize the array substrate. It is difficult for the reflective anode film to overlap with the SD (source and drain), and poor overlap is likely to occur, which seriously affects the display quality of the product.

SUMMARY OF THE INVENTION

At least one embodiment of the present invention provides a display substrate, a method for manufacturing the same, and a display device to improve the display quality of products.

In order to achieve the object of the present invention, at least one embodiment of the present invention provides a display substrate, comprising: a substrate, and a driving structure layer disposed on the corresponding substrate, the driving structure layer comprising: an active layer, a driving structure layer disposed on the active layer the first insulating layer on the layer, the gate and gate signal wirings arranged on the first insulating layer, the second insulating layer arranged on the gate and the gate signal wirings, arranged on the The source-drain electrodes and the auxiliary cathode on the second insulating layer, wherein at least one of the following is satisfied: the thickness of the gate signal trace is larger than the thickness of the gate, and the thickness of the auxiliary cathode is larger than that of the source-drain electrode thickness of.

In one embodiment, the driving structure layer further includes a passivation layer disposed on the source-drain electrodes and the auxiliary cathode, a planarization layer disposed on the passivation layer, and disposed on the planarization layer The reflective anode is connected to the source-drain electrode through a first via hole, and the connection electrode is connected to the auxiliary cathode through a second via hole.

In one embodiment, the planarization layer is made of an organosiloxane material.

In one embodiment, the driving structure layer further includes: a light shielding layer and a buffer layer sequentially disposed between the substrate and the active layer.

In one embodiment, the thickness of the gate is 1/3˜1/2 of the thickness of the gate signal trace.

In one embodiment, the thickness of the source and drain electrodes is 1/3˜1/2 of the thickness of the auxiliary cathode.

At least one embodiment of the present invention provides a display device, and the display device includes the display substrate described in the above embodiment.

At least one embodiment of the present invention provides a method for manufacturing a display substrate, including:

form a base;

forming a driving structure layer disposed on the substrate, the driving structure layer comprising: an active layer, a first insulating layer disposed on the active layer, a gate disposed on the first insulating layer and The gate signal wiring, the second insulating layer arranged on the gate and the gate signal wiring, the source-drain electrode and the auxiliary cathode arranged on the second insulating layer, wherein at least one of the following is satisfied: The thickness of the gate signal trace is greater than that of the gate, and the thickness of the auxiliary cathode is greater than that of the source and drain electrodes.

In one embodiment, the gate and gate signal traces are prepared in the following manner:

depositing a first metal film on the first insulating layer, and patterning to form a pattern at the position corresponding to the gate signal trace;

The first metal thin film is deposited again, and patterned to form a gate pattern and a gate signal wiring pattern.

In one embodiment, the source-drain electrodes and the auxiliary cathode are prepared based on the following methods:

depositing a second metal thin film on the second insulating layer, and patterning to form a pattern at the position corresponding to the auxiliary cathode;

The second metal thin film is deposited again, and patterned to form source-drain electrode patterns and auxiliary cathode patterns.

Compared with the related art, a display substrate provided by an embodiment of the present invention includes: a substrate, and a driving structure layer disposed on the corresponding substrate, the driving structure layer including: an active layer, a first layer disposed on the active layer an insulating layer, the gate and gate signal wirings arranged on the first insulating layer, the second insulating layer arranged on the gate and the gate signal wirings, arranged on the second insulating layer A source-drain electrode and an auxiliary cathode on the top, wherein at least one of the following is satisfied: the thickness of the gate signal trace is greater than the thickness of the gate, and the thickness of the auxiliary cathode is greater than the thickness of the source-drain electrode. In the solution provided in this embodiment, by changing the thickness difference between the gate signal trace and the gate, and the thickness difference between the auxiliary cathode and the source-drain electrode, the drop is reduced, and the depth of the subsequent via holes is reduced, which is beneficial to realize overlap. Improve product quality.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. They are used to explain the technical solutions of the present invention together with the embodiments of the present application, and do not limit the technical solutions of the present invention.

1 to 4 are schematic diagrams of display substrates provided in the related art;

FIG. 5 is a schematic diagram of a display substrate according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a substrate, a light shielding layer and a buffer layer after patterns are formed according to an embodiment of the present application;

7 is a schematic diagram of depositing a first metal film according to an embodiment of the present application;

8 is a schematic diagram of an embodiment of the present application after patterning the first metal film to form a pattern;

9 is a schematic diagram of redepositing a first metal film according to an embodiment of the present application;

FIG. 10 is a schematic diagram after forming a gate pattern and a gate signal wiring pattern according to an embodiment of the present application;

FIG. 11 is a schematic diagram after forming a source electrode pattern, a drain electrode pattern and an auxiliary cathode pattern according to an embodiment of the present application;

FIG. 12 is a schematic diagram after forming a planarization layer according to an embodiment of the present application;

FIG. 13 is a schematic diagram of forming via holes on the planarization layer according to an embodiment of the present application;

14 is a schematic diagram of an embodiment of the application after forming a reflective anode and a connecting electrode;

FIG. 15 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present application.

Explanation of reference numbers:

1—glass carrier plate; 10—substrate; 11a—light shielding layer;

11b—buffer layer; 12—active layer; 13—first insulating layer;

14—gate; 15—gate signal wiring; 16—second insulating layer;

19—source electrode; 20—drain electrode; 21—auxiliary cathode;

22—third insulating layer; 23—planarization layer; 31—anode;

32—connection electrode; 15a—first metal film; 15b—initial pattern.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used in this disclosure, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

As shown in FIG. 1 , it is a display substrate, comprising a substrate 10 , a light shield layer 11 a , a buffer layer 11 b , an active layer 12 , a first insulating layer 13 , a gate electrode 14 and a gate electrode that are sequentially arranged on the substrate 10 . A pole signal trace 15 , a second insulating layer 16 , a source electrode 19 , a drain electrode 20 , an auxiliary cathode 21 , and a third insulating layer 22 . Due to the influence of the TFT patterning process of the array substrate, the film layer in different regions has a large difference, as shown in Figure 1, so a thicker SOG material is required to be well planarized, as shown in Figure 2 , the thickness of the planarization layer 23 is relatively large. Thicker SOG material (the thickness of SOG where the via is required to be formed as shown by h1 and h2 in Figure 2) results in the need to use a very thick PR (photoresist) for protection during via etching and the dry etching time is very short. long, due to the large profile angle (profile) formed by the thick PR glue, and the long dry etching time, the SOG via hole has a large profile (as shown in Figure 3). The profile of the via hole is very large and the via hole of SOG is very deep, which makes it difficult for the subsequent reflective anode 31 and connecting electrode 32 to connect to the SD (source electrode 19 and auxiliary cathode 21), as shown in Figure 4, which is prone to poor overlap. This seriously affects the display quality of the product.

An embodiment of the present invention provides a display substrate, a method for manufacturing the same, and a display device. Using a brand-new TFT metal wiring design, the depth and profile of the SOG via hole can be greatly reduced, thereby greatly improving the overlap of the reflective anode, thereby Improve product display quality. The display substrate provided by the embodiment of the present invention includes: a substrate, a driving structure layer disposed on the corresponding substrate, and the driving structure layer includes: an active layer, a first insulating layer disposed on the active layer, and disposed on the active layer. The gate and gate signal wiring on the first insulating layer, the second insulating layer arranged on the gate and the gate signal wiring, the source-drain electrodes and auxiliary electrodes arranged on the second insulating layer A cathode, wherein at least one of the following is satisfied: the thickness of the gate signal trace is greater than the thickness of the gate, and the thickness of the auxiliary cathode is greater than the thickness of the source and drain electrodes. In the solution provided in this embodiment, by changing at least one of the thickness difference between the gate and the gate signal trace, and the thickness difference between the source-drain electrode and the auxiliary cathode, the disconnection between the TFT area and the non-TFT area is significantly reduced, The thickness of the flattening layer that needs to be coated becomes thinner, so that the depth of the via hole becomes shallower, and then a thinner PR glue and a shorter dry etching time can be used, so the slope angle profile of the formed via hole will also become slower. It is beneficial to the overlap of subsequent reflective anode film layers and improves the display quality of the product.

FIG. 5 is a schematic diagram of a display substrate according to an embodiment of the present invention, illustrating a structure of a display area on a plane perpendicular to the display substrate. As shown in FIG. 5 , on a plane perpendicular to the display substrate, the main structure of the display area includes a driving structure layer disposed on the substrate, and the driving structure layer includes a plurality of thin film transistors. In FIG. 5 , only one thin film transistor is used as an example. signal. The display substrate provided in this embodiment includes: a substrate 10 , a light shielding layer 11 a disposed on the substrate 10 , a buffer layer 11 b covering the light shielding layer 11 a , an active layer 12 disposed on the buffer layer 11 b , and an active layer 12 disposed on the active layer 12 The first insulating layer 13, the gate electrode 14 and the gate signal wiring 15 arranged on the first insulating layer 13, the second insulating layer 16 covering the gate electrode 14 and the gate signal wiring 15, and the second insulating layer 16 arranged on the second insulating layer The source electrode 19, the drain electrode 20 and the auxiliary cathode 21 on the layer 16, the third insulating layer 22 covering the source electrode 19, the drain electrode 20 and the auxiliary cathode 21, and the planarization layer 23 covering the third insulating layer 22 are provided The reflective anode 31 and the connection electrode 32 on the planarization layer 23, the reflective anode 31 is connected to the source electrode 19 through the first via hole, and the connection electrode 32 is connected to the auxiliary cathode 21 through the second via hole. The thickness of the gate signal trace 15 is greater than that of the gate electrode 14 , and the thickness of the auxiliary cathode 21 is greater than that of the source electrode 19 and the drain electrode 20 . In the solution provided in this embodiment, the thickness of the gate 14 is smaller than the thickness of the gate signal trace, and the thickness of the source electrode 19 and the drain electrode 20 is smaller than the thickness of the auxiliary cathode, so that the disconnection between the TFT area and the non-TFT area is significantly reduced , the thickness of the flattening layer that needs to be coated becomes thinner, so that the depth of the SOG via becomes shallower, and a thinner PR glue and a shorter dry etching time can be used, and the slope angle profile of the formed via will also become slower. , which is conducive to the overlap of the subsequent reflective anode film layers and improves the display quality.

The technical solution of the embodiment of the present invention is further described below through the preparation process of the display substrate in this embodiment. Among them, the "patterning process" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes. "Process" includes processes such as coating film layer, mask exposure, development, etc. The evaporation, deposition, coating, coating, etc. mentioned in this embodiment are all mature preparation processes in related technologies.

6 to 14 are schematic diagrams showing the substrate preparation process in this embodiment. The preparation process of the display substrate includes:

(1) Patterns of the substrate, the light shielding layer and the buffer layer are formed. Forming the patterns of the substrate, the light shielding layer and the buffer layer includes: firstly forming the substrate 10 on the glass carrier plate 1 . Subsequently, a light-shielding layer film is deposited on the substrate 10 to form a pattern of the light-shielding layer 11a; a buffer layer film is deposited on the light-shielding layer 11a to form a buffer layer 11b covering the light-shielding layer 11a, as shown in FIG. 6 . The buffer layer 11b is, for example, an inorganic insulating layer.

Wherein, the substrate 10 may include multiple layers, the light shielding layer 11a adopts a single-layer or laminated structure such as Mo, Al/Mo, Mo/Ti, etc., and the buffer layer film may adopt silicon nitride SiNx or silicon oxide SiOx, etc., which may be a single layer, A multi-layer structure of silicon nitride/silicon oxide is also possible.

(2) Forming an active layer pattern (Act pattern), a gate pattern and a gate signal wiring pattern on the buffer layer. Forming the active layer pattern, the gate pattern and the gate signal trace pattern on the buffer layer includes:

On the basis of forming the above structure, a layer of active layer film is deposited, and the active layer film is patterned through a patterning process to form the active layer 12 pattern disposed on the buffer layer 11b;

Subsequently, a first insulating film is deposited to form a first insulating layer 13 covering the active layer 12; wherein, the first insulating layer 13 may also be referred to as a gate insulating layer (GI).

Subsequently, the first metal thin films 15a are sequentially deposited. As shown in Figure 7. Then, exposure patterning and etching process are performed to pattern the first metal film, so that all the metal where the gate needs to be formed is etched away, and the metal where the gate signal trace needs to be formed is left to form the corresponding initial pattern 15b, that is, in the The initial pattern 15b is formed at the position corresponding to the gate signal trace, wherein the width of the initial pattern 15b of the gate signal trace needs to be larger than the width of the final gate trace signal layer pattern, as shown in FIG. 8 .

A first metal film is deposited again, as shown in FIG. 9 , and the first metal film is patterned to form a gate 14 pattern and a gate signal trace 15 pattern, as shown in FIG. 10 . It can be seen that the metal layer of the gate 14 is thinner and the metal layer of the gate signal trace 15 is thicker. Since the gate 14 only plays the role of introducing a voltage to turn on the TFT, it does not need too strong conductivity and the gate signal is not connected. Considering the voltage drop problem, the line 15 needs strong conductivity, so the metal layer of the gate 14 is thinner and the metal layer of the gate signal trace 15 is thicker to meet different requirements. In one embodiment, the thickness of the gate 14 is 1/3˜1/2 of the thickness of the gate signal trace 15 , and the thickness relationship is only an example, and other relationships are also possible. The thickness of the gate signal trace 15 in this embodiment may be the same as the thickness of the gate signal trace in FIG. 4 , and the thickness of the gate 14 is smaller than that of the gate in FIG. 4 . In this way, the height difference between the TFT area (the area where the gate electrode 14 is located) and the non-TFT area (the area where the gate signal traces 14 are located) can be subsequently reduced. Of course, in other embodiments, the thickness of the gate signal trace 15 may be larger than that of the gate signal trace in FIG. 4 .

(3) Forming a second insulating layer pattern, a source electrode pattern, a drain electrode pattern, and an auxiliary cathode pattern.

Forming the second insulating layer pattern, the source electrode pattern, the drain electrode pattern and the auxiliary cathode pattern includes: on the basis of forming the above structure, depositing a second insulating film, patterning the second insulating film through a patterning process, and forming openings in the display area The second insulating layer 16 pattern with the first via hole, the second via hole and the third via hole, the second insulating layer 16 in the first via hole and the second via hole is etched away, exposing the active layer 12 ; The second insulating layer 16 and the buffer layer 11b in the third via hole are etched away, exposing the light shielding layer 11a.

depositing a second metal film, patterning the second metal film through a patterning process, and forming a pattern at the position corresponding to the auxiliary cathode;

A second metal film is deposited again, and the second metal film is patterned through a patterning process to form a pattern of the source electrode 19 , the pattern of the drain electrode 20 and the pattern of the auxiliary cathode 21 , as shown in FIG. 11 .

It can be seen that the metal layers of the source electrode 19 and the drain electrode 20 are thinner and the metal layer of the auxiliary cathode 21 is thicker. In one embodiment, the thickness of the source electrode 19 and the drain electrode 20 is 1/3˜1/2 of the thickness of the auxiliary cathode 21 . It should be noted that the thickness here is only an example, and the two thicknesses may also be in other relationships. In this embodiment, the thickness of the auxiliary cathode 21 can be the same as the thickness of the auxiliary cathode layer in FIG. In this way, the height difference between the TFT area (the area where the gate electrode 14 is located) and the non-TFT area (the area where the gate signal traces 14 are located) can be subsequently reduced. Of course, in other embodiments, the thickness of the auxiliary cathode 21 may be larger than that of the auxiliary cathode layer in FIG. 4 .

The drain electrode 20 and the source electrode 19 are respectively connected with the active layer 12 through the first via hole and the second via hole, the source electrode 19 is also connected with the light shielding layer 11a through the third via hole, and the active layer 12 is connected with the drain electrode 20 and the source electrode 11a. Electrodes 19 are conductive (not shown in FIG. 11 ) where they overlap.

The second insulating layer 16 is also referred to as an interlayer insulating layer (ILD).

(4) Forming a passivation layer pattern and a planarization layer pattern

On the basis of forming the above structure, a third insulating film is coated, and a passivation layer (PVX) 22 pattern covering the source electrode 19, the drain electrode 20 and the auxiliary cathode 21 is formed by a photolithography process of mask exposure and development;

Subsequently, a fourth insulating film is coated, and a pattern of the planarization layer 23 covering the passivation layer 22 is formed by a photolithography process of mask exposure and development, as shown in FIG. 12 . The fourth insulating film is, for example, SOG. The passivation layer 22 is provided with a fourth via hole and a fifth via hole, as shown in FIG. 13 .

Since the Gate (gate) and SD (source and drain) of the TFT area are significantly thinner than those of the traditional process, the difference between the TFT area and the non-TFT area is significantly reduced, so the SOG planarization layer to be coated can be significantly changed. Thin (the thickness of SOG where the via hole needs to be formed is shown as h3 and h4 in Figure 12), it can be seen that the heights of h3 and h4 are significantly smaller than the heights of h1 and h2 in Figure 2, that is, the depth of the via hole to form SOG should be It is obviously shallower, so that thinner PR glue and shorter dry etching time can be used, so the slope angle profile of the formed via hole will also become slower, which is very beneficial to the subsequent overlap of the reflective anode film layer.

(5) Patterns of reflective anodes and connection electrodes are formed.

Forming the reflective anode pattern and the connecting electrode includes: on the basis of forming the above structure, depositing a conductive film, patterning the conductive film through a patterning process, forming a reflective anode 31 pattern and a connecting electrode 32 pattern, and the reflective anode 31 is connected to the reflective anode 31 through the fourth via hole. The source electrode 19 is connected, and the connection electrode 32 is connected to the auxiliary cathode 21 through the fifth via hole. As shown in Figure 14. Materials such as Mo/Al/ITO-T, Al alloy/ITO-T, etc. can be used for the conductive thin film.

By using the TFT metal wiring design provided in this embodiment, the depth and profile of the SOG via hole can be greatly reduced, thereby greatly improving the overlap of the reflective anode, which is beneficial to the improvement of the quality of the display product.

It can be seen from the above preparation process that the display substrate provided in this embodiment reduces the TFT area and the non-TFT area by changing the thickness ratio of the source-drain electrode and the auxiliary cathode, and changing the thickness ratio of the gate electrode and the gate wiring. The fault difference in the area reduces the depth of the via hole and makes the slope angle of the via hole gentler, so that the overlap between the reflective anode and the source electrode is used to improve the display quality of the product, which has practical application value and a good application prospect.

It should be noted that, in another embodiment, only the thickness ratio of the gate electrode and the gate wiring can be changed, while the thickness ratio of the source electrode, the drain electrode and the auxiliary cathode can be kept, or the gate electrode and the gate wiring can be kept. Only the thickness ratio of the source electrode, the drain electrode and the auxiliary cathode is changed.

It should be noted that the structure and the preparation process thereof shown in this embodiment are merely illustrative. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, other electrodes, leads and structural film layers may also be provided in the driving structure layer. The embodiments of the present invention are not specifically limited herein.

It should be noted that, in another embodiment, another preparation method may also be used to form the gate pattern, the gate signal wiring pattern, the source electrode pattern, the drain electrode pattern and the auxiliary cathode pattern.

The formation of the gate pattern and the gate signal wiring pattern is taken as an example for description. After the first insulating layer 13 is formed, a first metal thin film is deposited on the first insulating layer 13, the thickness is equivalent to the thickness of the two layers of the first metal thin films deposited in the foregoing embodiment, patterning is performed, and different etching rates are formed by controlling the etching rate. Thickness of gate pattern and gate signal trace pattern.

As shown in FIG. 15 , based on the technical concept of the embodiment of the present invention, an embodiment of the present invention further provides a method for preparing a display substrate, including:

Step 1501, forming a substrate;

Step 1502 , forming a driving structure layer disposed on the substrate, the driving structure layer comprising: an active layer, a first insulating layer disposed on the active layer, and a first insulating layer disposed on the first insulating layer Gate and gate signal traces, a second insulating layer disposed on the gate and gate signal traces, source-drain electrodes and auxiliary cathodes disposed on the second insulating layer, wherein at least the following One: the thickness of the gate signal trace is greater than the thickness of the gate, and the thickness of the auxiliary cathode is greater than the thickness of the source and drain electrodes.

In one embodiment, in step 1502, the gate and gate signal traces are prepared in the following manner:

depositing a first metal film on the first insulating layer, and patterning to form a pattern at the position corresponding to the gate signal trace;

The first metal thin film is deposited again, and patterned to form a gate pattern and a gate signal wiring pattern.

In one embodiment, in the step 1502, the source-drain electrodes and the auxiliary cathode are prepared based on the following methods:

depositing a second metal thin film on the second insulating layer, and patterning to form a pattern at the position corresponding to the auxiliary cathode;

The second metal thin film is deposited again, and patterned to form source-drain electrode patterns and auxiliary cathode patterns.

In this embodiment, the structures, materials, related parameters and detailed preparation processes of each film layer have been described in detail in the foregoing embodiments, and will not be repeated here.

This embodiment provides a method for fabricating a display substrate. By changing at least one of the thickness difference between the gate electrode and the gate signal trace, and the thickness difference between the source-drain electrode and the auxiliary cathode, the gap between the TFT area and the non-TFT area is changed. The difference of the fracture is significantly reduced, and the thickness of the flattening layer to be coated becomes thinner, so that the depth of the via hole becomes shallower, and then a thinner PR glue and a shorter dry etching time can be used to make the slope angle of the formed via hole. The profile will also slow down, which is conducive to the subsequent overlap of the reflective anode film layer, and improves the display quality of the product.

Based on the technical concept of the embodiments of the present invention, an embodiment of the present invention further provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component that has a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

The following points need to be noted:

(1) The accompanying drawings of the embodiments of the present invention only relate to the structures involved in the embodiments of the present invention, and other structures may refer to general designs.

(2) In the drawings for describing the embodiments of the present invention, the thicknesses of layers or regions are exaggerated or reduced for clarity, ie, the drawings are not drawn on an actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, Or intermediate elements may be present.

(3) The embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments without conflict.

Although the embodiments disclosed in the present invention are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention still needs to be The scope defined by the appended claims shall prevail.

Claims (10)

1. A display substrate, comprising: the substrate, set up the drive structure layer on affiliated substrate, the drive structure layer includes: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

2. The display substrate of claim 1, wherein the driving structure layer further comprises a passivation layer disposed on the source and drain electrodes and the auxiliary cathode, a planarization layer disposed on the passivation layer, and a reflective anode and a connection electrode disposed on the planarization layer, wherein the reflective anode is connected to the source and drain electrodes through a first via, and the connection electrode is connected to the auxiliary cathode through a second via.

3. The display substrate of claim 2, wherein the planarization layer is made of an organosiloxane material.

4. The display substrate of claim 1, wherein the driving structure layer further comprises: and the light shielding layer and the buffer layer are sequentially arranged between the substrate and the active layer.

5. The display substrate according to any one of claims 1 to 4, wherein the thickness of the gate is 1/3-1/2 of the thickness of the gate signal trace.

6. The display substrate according to any one of claims 1 to 4, wherein the thickness of the source and drain electrodes is 1/3-1/2 of the thickness of the auxiliary cathode.

7. A display device comprising the display substrate according to any one of claims 1 to 6.

8. A method for preparing a display substrate is characterized by comprising the following steps:

forming a substrate;

forming a drive structure layer disposed on the substrate, the drive structure layer comprising: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

9. The method of claim 8, wherein the gate and gate signal traces are prepared based on:

depositing a first metal film on the first insulating layer, and forming a pattern at a position corresponding to the gate signal wiring by patterning;

and depositing the first metal film again, and forming a grid pattern and a grid signal wiring pattern by composition.

10. The method for manufacturing a display substrate according to claim 8 or 9, wherein the source-drain electrode and the auxiliary cathode are manufactured based on the following method:

depositing a second metal film on the second insulating layer, and patterning to form a pattern at a position corresponding to the auxiliary cathode;

and depositing the second metal film again, and patterning to form a source and drain electrode pattern and an auxiliary cathode pattern.

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