CN110828441A - Multiplexer - Google Patents

Abstract

The present invention relates to the technical field of communication equipment, in particular to a multiplexer, comprising a first chip and a second chip, the first chip and the second chip are superimposed; the first chip includes a first wafer and a second wafer, A first resonator layout area including a plurality of resonators is arranged on the first wafer; the second chip includes a third wafer and a fourth wafer, and a second resonator including a plurality of resonators is arranged on the third wafer Device layout area. In the technical scheme of the present invention, the chip size is further reduced compared with the prior art, which is beneficial to the miniaturization of the multiplexer.

Description

a multiplexer

technical field

The present invention relates to the technical field of communication equipment, in particular to a multiplexer.

Background technique

With the acceleration of the trend of miniaturization and high performance of communication equipment, the RF front-end has presented higher challenges in size and performance. Due to the gradual increase in frequency bands, more filters occupy larger terminal sizes, which is related to miniaturization. trend is contrary.

In the front-end of radio frequency communication, reducing the chip size is on the one hand to reduce the manufacturing size of the chip itself, and on the other hand, to reduce the spacing of the package, but the reduction of the package spacing will bring about a great test of the process and the impact of yield. Therefore reducing the manufacturing size of the chip itself is crucial. In a traditional duplexer or multiplexer, multiple chips are arranged in a plane, and the size that can be reduced is limited, and the smaller the chip spacing, the greater the mutual coupling, which will seriously deteriorate the overall performance of the chip.

SUMMARY OF THE INVENTION

In view of this, the main purpose of the present invention is to provide a multiplexer, which helps to reduce the plane area occupied by the chip.

In order to achieve the above object, according to an aspect of the present invention, a multiplexer is provided, comprising a first chip and a second chip arranged in a superimposed manner; the first chip includes a first wafer and is used for packaging the first chip. A second wafer of wafers, the first wafer is provided with a first resonator layout area including a plurality of resonators; the second chip includes a third wafer and is used for packaging the third wafer The fourth wafer is provided with a second resonator layout area including a plurality of resonators on the third wafer.

Optionally, the second wafer is adjacently arranged on the third wafer, and the vertical projection of the layout area of the first resonator and the vertical projection of the layout area of the second resonator form an overlapping area. and a non-overlapping area, the first resonator layout area is provided with a plurality of first pins, and the vertical projection of the first pins is located in the non-overlapping area.

Optionally, the thickness of the first wafer, the second wafer, the third wafer and the fourth wafer is 50um˜200um.

Optionally, a metal isolation layer is provided between the second wafer and the third wafer, the metal isolation layer overlaps with the overlapping region, and the metal isolation layer is connected to ground pins.

Optionally, the vertical projections of the metal isolation layer and the overlapping region are coincident.

Optionally, capacitors and/or inductors are integrated outside the first resonator layout area on the first wafer; and/or the third wafer is located in the second resonator layout area Externally integrated set capacitors and/or inductors.

Optionally, the dielectric constants of the second wafer and the third wafer are smaller than the dielectric constants of the first wafer and the fourth wafer.

Optionally, the third wafer is composed of the second resonator layout area and a non-resonator layout area; the vertical projections of the plurality of first pins fall within the non-resonator layout area.

Optionally, the first resonator layout area is covered with the first wafer.

Optionally, the first pins include a plurality of ground pins.

According to the technical solution of the present invention, the first chip and the second chip originally arranged side by side are changed to be stacked, which reduces the area occupied on the plane in structure, and the height can be limited by reducing the thickness of the wafer; the present invention In the technical solution of the invention, the chip size is further reduced compared with the prior art, which is beneficial to the miniaturization of the multiplexer.

Description of drawings

For purposes of illustration and not limitation, the present invention will now be described in accordance with preferred embodiments thereof, particularly with reference to the accompanying drawings, wherein:

Fig. 1 shows the cross-sectional view of the first chip and the second chip of the multiplexer after stacking;

Fig. 2 shows the top view of the superimposed first chip and the second chip of the multiplexer;

3 shows a top view of another superimposed structure of the first chip and the second chip of the multiplexer;

FIG. 4 shows a top view of yet another superimposed structure of the first chip and the second chip of the multiplexer;

Figure 5 shows a top view of adding a metal isolation layer;

Figure 6 shows a comparison diagram of isolation;

Fig. 7 shows the contrast diagram of the isolation degree after adding horizontal isolation;

Fig. 8 shows the contrast diagram of the isolation degree after adding horizontal isolation and longitudinal isolation;

Figure 9 shows a front view of the integrated capacitor;

Figure 10 shows a front view of the integrated inductor;

FIG. 11 shows a cross-sectional view of the first chip and the second chip of the multiplexer with arrows pointing to the stack;

Figure 12 shows a schematic diagram of isolation improvement;

Fig. 13 shows the top view when the resonator is arranged in the spare part;

Figure 14 shows a top view of adding an additional fourth ground pin;

Figure 15 shows a schematic diagram of the relationship between inductance value and roll-off;

Figure 16 shows a schematic diagram of the relationship between inductance value and out-of-band rejection.

In the picture:

1: first wafer; 2: second wafer; 3: third wafer; 4: fourth wafer; 5: metal isolation layer; 11: first resonator layout area; 12: first pin; 13: Integrated capacitor; 14: Integrated inductor; 31: Second resonator layout area; 32: Second pin.

Detailed ways

Referring to FIGS. 1-16 , an embodiment of the present invention provides a multiplexer, including a first chip and a second chip that are superimposed; the first chip includes a first wafer 1 and a multiplexer for packaging the first wafer 1 The second wafer 2 has a first resonator layout area 11 including a plurality of resonators on the first wafer 1 ; the second chip includes a third wafer 3 and a fourth wafer for packaging the third wafer 3 In circle 4, a second resonator layout area 31 including a plurality of resonators is provided on the third wafer 3. As shown in FIG. The first chip is a receiving chip or a sending chip, and the corresponding second chip is a sending chip or a receiving chip.

In the embodiment of the present invention, the improvement in the structure of the multiplexer is to change the first chip and the second chip arranged side by side in the horizontal direction into a superimposed arrangement in the vertical direction. Among them, the superimposed setting will inevitably lead to the reduction of the occupied area of the product and the increase of the height (from the perspective of Figure 1). For the problem of height increase, by changing the thicknesses of the first wafer 1, the second wafer 2, the third wafer 3 and the fourth wafer 4 (thinner wafers are selected), the overall thickness of the product is controlled, so that the In the case of stacking, it can also maintain the same height as the original multiplexer. Preferably, the wafers can be grinded to reduce their thickness, such as the first wafer 1, the second wafer 2, the third wafer The thickness of the wafer 3 and the fourth wafer 4 after grinding is 50um˜200um. This structure can ensure that the overall volume of the product is reduced; in theory, the stacking method can reduce the area by 50%. However, considering the connection relationship between chips and factors such as the different areas of multiple chips, the actual stacking After setting, the area cannot be reduced by 50%, but generally around 30%-40%.

In the technical solution disclosed in the embodiment of the present invention, the superposition of the first chip and the second chip may cause a large coupling, which may deteriorate the product performance. Therefore, the product performance can be further optimized by changing the structure and improving the isolation.

In the technical solution of this embodiment, the second wafer 2 is disposed adjacent to the third wafer 3, and the vertical projection of the first resonator layout area 11 and the vertical projection of the second resonator layout area 31 form an overlapping area and Non-overlapping area; a plurality of first pins 12 are arranged in the first resonator layout area, and a plurality of second pins 32 are arranged in the second resonator layout area 31; wherein, the first pins 12 and the second pins The pins 32 include input pins, output pins, isolation pins, ground pins, and the like. The vertical projections of the plurality of first pins 12 are located in non-overlapping regions. In order to effectively isolate the first chip and the second chip and avoid/reduce the phenomenon of performance deterioration, the first pins 12 need to be arranged in the non-overlapping area in terms of structure, and the first pins 12 are all parallel to the resonator. The layout plane (that is, the plane where the screen or paper is located) or the horizontal direction is arranged away from the layout area 31 of the second resonator, and the first pin 12 will not pass through the layout area of the second resonator when the wiring is set. 31. This structural form realizes the "horizontal isolation" between the first chip and the second chip. Through the isolation structure, the coupling can be reduced, thereby reducing the deterioration of product performance. Wherein, for horizontal isolation, the farther the first pin 12 is from the second resonator layout area 31, the better the isolation effect.

In the first chip, in addition to the first pins 12, other auxiliary structures are provided on the first resonator layout area 11, such as multiple metal layers, vertical metal pillars, etc. In order to improve the isolation, avoid/reduce Deteriorating performance, the vertical projection of the accessory structure is also set in the non-coincident area.

In the embodiment of the present invention, the isolation structure can also be provided with "longitudinal isolation", that is, the up and down direction from the perspective of FIG. The isolation layer 5 overlaps with the overlapping area of the first resonator layout area 11 and the second resonator layout area 31 , and the metal isolation layer 5 is connected to the ground pin. The metal isolation layer 5 needs to be grounded, which can isolate the first chip and the second chip; wherein, the larger the area of the metal isolation layer 5, the better the isolation degree, preferably, the vertical projection of the metal isolation layer 5 and the overlapping area coincide. Wherein, the metal isolation layer 4 may be a layer structure with an isolation effect, such as a plane metal layer, a grid-like metal layer, or the like.

As shown in FIG. 2 , it shows a top view of the first chip and the second chip of the multiplexer after stacking, and the second wafer 2 and the fourth wafer 4 are not shown in the figure, wherein the rectangle acfh represents the first wafer 1 and the overall outline of the third wafer 3; the rectangle bcfg represents the first resonator layout area 11; the rectangle jdei represents the second resonator layout area 31, the rectangle kdel represents the overlapping area, the rectangle bcdk and the rectangle lefg represent the first wafer 1. , the rectangle jkli represents the non-overlapping area on the third wafer 3 . It can be seen from FIG. 2 that the first pins 12 on the first wafer 1 are located away from the layout area 31 of the second resonator. Among them, FIG. 2 is only one of the overlapping forms, and the overlapping forms in this embodiment also include but are not limited to the following forms, as shown in FIG. 3 , the overlapping area is on the left, or, as shown in FIG. 4 , the overlapping The area is in the middle. As shown in FIG. 5 , the figure is a schematic diagram of the structure when the metal isolation layer 5 is provided, that is, the area surrounded by the thick black solid line in the figure, the larger the area of the area, the better the isolation effect.

As shown in Figure 6, this figure is a comparison diagram of isolation, in which the dotted line is the isolation of the side-by-side structure, the solid line is the isolation of the stacked structure, and the solid line is the curve without adding horizontal isolation and vertical isolation, It can be seen that the left side deteriorates by about 5dB, and the right side deteriorates by more than 10dB. As shown in FIG. 7 , the graph is a curve of adding horizontal isolation to the stacked structure, but without adding vertical isolation. It can be seen that the degree of deterioration has a certain improvement compared to the curve in FIG. 5 . As shown in Figure 8, in the stacked structure, adding horizontal isolation and vertical isolation at the same time, the left side is improved by about 3dB, and the right side is improved by more than 10dB.

In a preferred implementation of this embodiment, capacitors and/or inductors are integrated on the first wafer 1 outside the first resonator layout area 11; and/or the third wafer 3 is located in the second resonator layout area 31 Externally integrated set capacitors and/or inductors. As shown in FIG. 9 , a capacitor 13 is integrated on the first wafer 1 outside the layout area 11 of the first resonator. The capacitor can be the interdigital capacitor or plate capacitor or other types of capacitors in the above figure; as shown in FIG. 10 , in the The inductor 14 is integrated in the area outside the first resonator layout area 11 on the first wafer 1 . The integrated capacitor 13 and inductor 14 can eliminate matching components. On the one hand, the reduction of matching components can reduce the number of layers of the substrate, reduce the thickness of the chip and the cost of the substrate. On the other hand, the reduction of off-chip passive components can reduce the size of the entire RF front-end. and cost. At the same time, the integrated inductor or capacitor can improve the roll-off, increase the bandwidth, and increase the out-of-band transmission zero to improve the rejection at specific frequencies.

As shown in FIG. 11, the figure is a cross-sectional view of the first chip and the second chip of the multiplexer after stacking, and the arrows in the figure point to the second wafer 2 and the third wafer 3. In the prior art, a silicon substrate is used. Due to the large dielectric constant of the silicon substrate, the upper and lower two pass through the high dielectric constant medium, and the coupling capacitance is large, so it has a certain impact on the performance of the duplexer. In order to improve this part to improve the isolation, The materials of the second wafer 2 and the third wafer 3 can be replaced, that is, the dielectric constants of the second wafer 2 and the third wafer 3 are smaller than those of the first wafer 1 and the fourth wafer 4 . The second wafer 2 and the third wafer 3 are changed to low dielectric constant materials, which can reduce coupling. As shown in Figure 12, the isolation is improved after using low dielectric constant materials, where the solid line is the improved curve, and the improvement range is about 2-3dB.

In the preferred embodiment of the present invention, the areas of the first wafer 1 and the third wafer 3 can be further utilized to a greater extent. For the first wafer 1, the first resonator layout area 11 is covered with the first wafer. Circle 1; for the third wafer 3, as shown in FIG. 13, the third wafer 3 consists of the second resonator layout area 31 and the non-resonator layout area; the vertical projection of the first pin 12 falls on the non-resonator layout area 31. within the resonator layout area. In this structure, all the spare areas of the first wafer 1 and the third wafer 3 are used for arranging resonators, and the utilization rate of the area is high, so that the area of the wafer can be further reduced.

The embodiment of the present invention is preferably implemented, the first pin 12 includes a plurality of ground pins. In the superimposed structure, the first chip is located at the uppermost end, and the grounding trace needs to pass through the second wafer 2, the third wafer 3 and the fourth wafer 4, and the parasitic inductance of the first wafer 1 will increase, There is some deterioration in roll-off, and the transmission zero of out-of-band rejection will shift, and high-frequency rejection will deteriorate. Therefore, as shown in Figure 14, the inductance is reduced by adding additional ground pins to improve roll-off and far-band rejection.

As shown in Figure 15, the solid line is the corresponding roll-off when the inductance is small, and the dotted line is the corresponding roll-off when the inductance is large. From this figure, it can be seen that the smaller the inductance, the better the roll-off. As shown in Figure 16, the solid line is the corresponding out-of-band suppression when the inductance is small, and the dotted line is the corresponding out-of-band suppression when the inductance is large. From this figure, it can be seen that the smaller the inductance, the better the far-band suppression.

The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A multiplexer is characterized by comprising a first chip and a second chip which are arranged in a superposition mode;

the first chip comprises a first wafer (1) and a second wafer (2) used for packaging the first wafer (1), wherein a first resonator layout area (11) comprising a plurality of resonators is arranged on the first wafer (1);

the second chip comprises a third wafer (3) and a fourth wafer (4) used for packaging the third wafer (3), and a second resonator layout area (31) comprising a plurality of resonators is arranged on the third wafer (3).

2. The multiplexer according to claim 1, wherein the second wafer (2) is adjacently arranged on the third wafer (3) and such that a vertical projection of the first resonator layout area (11) and a vertical projection of the second resonator layout area (31) form an overlapping region and a non-overlapping region;

a plurality of first pins (12) are arranged in the first resonator layout area (11), and the vertical projections of the first pins (12) are located in the non-overlapping area.

3. The multiplexer of claim 1, wherein the first wafer (1), the second wafer (2), the third wafer (3) and the fourth wafer (4) have a thickness of 50-200 um.

4. The multiplexer according to claim 1 or 2, wherein a metal isolation layer (5) is disposed between the second wafer (2) and the third wafer (3), the metal isolation layer (5) overlaps the overlapping region, and the metal isolation layer (5) is connected to a ground pin.

5. Multiplexer according to claim 4, wherein the metal isolation layer (5) coincides with a perpendicular projection of the coinciding zones.

6. The multiplexer of claim 1,

a capacitor (13) and/or an inductor (14) are/is integrated on the first wafer (1) and positioned outside the first resonator layout area (11);

and/or

And a capacitor (13) and/or an inductor (14) are/is integrated on the third wafer (3) and positioned outside the second resonator layout area (31).

7. The multiplexer according to claim 1, wherein the dielectric constant of the second wafer (2) and the third wafer (3) is smaller than the dielectric constant of the first wafer (1) and the fourth wafer (4).

8. The multiplexer of claim 2,

the third wafer (3) is composed of the second resonator layout area (31) and a non-resonator layout area;

the vertical projection of a plurality of said first pins (12) falls within said non-resonator layout area.

9. The multiplexer according to claim 1 or 8, wherein the first resonator layout area (11) is full of the first wafer (1).

10. The multiplexer of claim 1, wherein the first pin (12) comprises a plurality of ground pins.

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