CN110827868B - Write-back circuit and method for improving read stability of sense amplifier - Google Patents
Write-back circuit and method for improving read stability of sense amplifier Download PDFInfo
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Abstract
The invention discloses a write-back circuit and a method for improving the read stability of a sensitive amplifier, wherein the write-back circuit comprises: a first-stage sense amplifier which performs first amplification on data and transfers the amplified data onto an amplification line; the second-stage sensitive amplifier amplifies the amplified data for the second time; the main DQ reading control circuit is connected with the first-stage sensitive amplifier and the second-stage sensitive amplifier and keeps conducting; the second-stage sense amplifier is used for transmitting the amplified data to the first-stage sense amplifier; and writing the secondarily amplified data back to the amplifying line so as to write back to the first-stage sense amplifier, and recovering the voltage peak coupled on the bit line BL or BL _ N of the first-stage sense amplifier. The write-back circuit for improving the read stability of the sense amplifier writes back a signal MA/MA _ N amplified by the second-stage sense amplifier to the first-stage sense amplifier. The read stability of the first-stage sensitive amplifier is improved, and the reliability of read operation is improved.
Description
Technical Field
The invention relates to the field of memory design, in particular to a write-back circuit and a write-back method for improving the read stability of a sensitive amplifier.
Background
The sense amplifier is widely used in the read operation of the memory, and mainly acts to amplify a small signal on a bit line into a digital signal. In the read operation stage of the memory, the first-stage sense amplifier amplifies the small signals read from the array, when the small signals are amplified to be recognizable digital signals, the main DQ (Data I/O is an input/output line or a connection interface of Data) read control circuit transmits the amplified digital signals to the second-stage sense amplifier, and the second-stage sense amplifier amplifies the signals for the second time.
Fig. 1 is a schematic diagram of a conventional memory read operation data amplifying circuit: the working voltage of the first-stage sensitive amplifier is a Bit Line high level voltage VBLH (voltage of Bit Line high), and the NMOS transistor N10 and the transistor N11 are connected with the first-stage sensitive amplifier and the main DQ read control circuit; the pre-charge PMOS transistor P10, the transistor P11 and the equalizing PMOS transistor P12 form a pre-charge circuit of main DQ, the PMOS transistor P0 and the transistor P1 are connected with the main DQ and the second-stage sensitive amplifier, and the voltage domain of the main DQ read control circuit is the power voltage VDD; the working voltage of the second-stage sensitive amplifier is the power supply voltage VDD.
The operation of the conventional read operation data amplifying circuit will now be described with reference to the schematic diagram of the conventional read operation data amplifying circuit of fig. 1 and the waveform diagram of the conventional read operation data amplifying circuit of fig. 4.
In the non-working stage, the first-stage sensitive amplifier and the second-stage sensitive amplifier do not work, the bit line BL/BL _ N is precharged to the bit line precharge voltage, the NMOS tube N10 and the NMOS tube N11 are turned off, the precharge PMOS tube P10, the PMOS tube P11 and the equalizing tube P12 are turned on, the precharge inverse signal MDQ _ PRE _ N of the amplifying line MDQ/MDQ _ N is low, and the MDQ/MDQ _ N is kept at the power supply voltage VDD. The PMOS tube P0 and the PMOS tube P1 are turned off, the PRE-charge PMOS tube P4, the PMOS tube P5 and the equalizing tube P6 are turned on, a PRE-charge inverted signal MA _ PRE _ N of the MA/MA _ N is low, the MA/MA _ N is kept at a power supply voltage VDD, and the sense amplifier enable SAE of the second stage is low.
The work time of the read operation data amplifying circuit is divided into three stages:
firstly, a first-stage sensitive amplifier is used for amplifying;
secondly, a signal transmission stage;
and finally, performing secondary signal amplification.
At the beginning of a read operation, the charge on the memory cell causes the BL to be pulled down or up from the bit line precharge voltage through charge sharing, creating a voltage difference across BL/BL _ N until the voltage difference reaches the offset voltage of the first stage sense amplifier, which operates to amplify the voltage difference across BL/BL _ N to a recognizable digital signal. The master DQ precharge invert signal MDQ _ PRE _ N is high, P10-P12 are off, the precharge invert signal MA _ PRE _ N of MA/MA _ N is high, and P4-P6 are off.
During the signaling phase, the column select line (column select line CSL) is asserted, N10-N11 is turned on, the read enable bar RE _ N is asserted, P0-P1 are turned on, and the low level on BL or BL _ N pulls down the MDQ or MDQ _ N, which bar MDQ _ N or MDQ remains at VDD. The pulled down MDQ or MDQ _ N pulls down MA or MA _ N, whose inverse signal MA _ N or MA remains unchanged at VDD until a certain voltage difference is established between MA and MA _ N until the voltage difference reaches the offset voltage of the second stage sense amplifier.
In the working phase of the second-stage sensitive amplifier, the read enable inverse RE _ N is high, and P0-P1 are turned off; column select line CSL is low, N10-N11 are off; the sense amplifier of the second stage enables SAE to be high, the sense amplifier of the second stage begins to amplify the voltage difference between MA and MA _ N, and when MA or MA _ N continues to discharge until discharging to ground VSS, SAE is low, and the data amplification stage ends.
In the above read data amplifying stage, the working voltage of the first stage sense amplifier is different from that of the main DQ read control circuit, wherein VBLH in the first stage sense amplifier is smaller than VDD of the read control circuit. Since the first stage sense amplifier is driven weakly and the load of MDQ/MDQ _ N is large, the transmission time is long, and the voltage on the column selection line CSL is higher than VBLH for the voltage on BL/BL _ N to be quickly transmitted to MDQ/MDQ _ N, so that the high level VDD on the MDQ/MDQ _ N line can cause an undesirable voltage peak to be coupled out on the low level of BL or BL _ N.
According to the traditional read operation data amplification circuit, an MDQ and a second-stage sense amplifier are connected through a PMOS pipe P0 and a PMOS pipe P1, when data pass through the MDQ from a first-stage sense amplifier and generate voltage difference at two ends of the second-stage sense amplifier, the PMOS pipe P0 and the PMOS pipe P1 are conducted, when the voltage difference established between MA and MA _ N reaches the offset voltage of the second-stage sense amplifier, the PMOS pipe P0 and the PMOS pipe P1 are disconnected, SAE is effective, the second-stage sense amplifier amplifies the voltage difference on the MA and MA _ N, and the second-stage sense amplifier is isolated from the first-stage sense amplifier.
As shown in fig. 5, a waveform diagram of the lost data of the amplifier of the conventional memory read operation data amplifying circuit, when the voltage peak is too high, the voltage difference on BL/BL _ N is destroyed, and the data on the first-stage sense amplifier is disturbed and lost, so that the disturbed data is read out when the second read operation is performed on the same address.
Disclosure of Invention
In order to solve the problem of data loss in the existing read operation data amplification process, the invention provides a write-back circuit and a write-back method for improving the read stability of a sense amplifier. The read stability of the first-stage sensitive amplifier is improved, and the reliability of read operation is improved.
In order to achieve the purpose, the invention adopts the following technical means:
a write back circuit for improving sense amplifier read stability, comprising:
a first-stage sense amplifier: for amplifying the data for the first time and transferring the amplified data onto an amplifying line;
a second-stage sense amplifier: the second amplification is carried out on the first amplification data;
main DQ read control circuit: the first-stage sense amplifier is connected with the second-stage sense amplifier; and the first-stage sensitive amplifier and the second-stage sensitive amplifier are controlled to be switched on or switched off;
when the amplifier is switched on, the amplifier is used for transmitting the first amplified data to a second-stage sensitive amplifier for secondary amplification; and writing the second amplified data back to the amplifying line, thereby writing back to the first-stage sense amplifier, and recovering the voltage peak coupled on the bit line BL or BL _ N of the first-stage sense amplifier.
As a further improvement of the present invention, the master DQ read control circuit is configured to write back the further amplified high-level data, low-level data, or intermediate-level data onto the amplification line.
As a further improvement of the invention, the main DQ read control circuit is connected with the second-stage sense amplifier through a transmission gate.
As a further improvement of the present invention, the master DQ read control circuit includes a pass transistor M0, a pass transistor M1, a precharge PMOS transistor P10 and a precharge PMOS transistor P11, and an equalization PMOS transistor P12;
the gates of the PRE-charge PMOS transistor P10, the PRE-charge PMOS transistor P11 and the equalizing PMOS transistor P12 are connected to a PRE-charge inverse signal line MDQ _ PRE _ N, the source of the PRE-charge PMOS transistor P10 and the source of the PRE-charge PMOS transistor P11 are connected to a power supply voltage VDD, the drain of the PRE-charge PMOS transistor P10 of the PRE-charge PMOS transistor P11 is connected to the source of the equalizing PMOS transistor P12 and then connected to a first end of a transmission tube M0, and the source end of the transmission tube M0 is connected to an amplification line MDQ of a first-stage sense amplifier; the drain electrode of the pre-charging PMOS transistor P11 is connected with the drain electrode of the equalizing PMOS transistor P12 and then is connected with the first end of a transmission tube M1, and the source end of the transmission tube M1 is connected with the amplification line MDQ _ N of the first-stage sensitive amplifier; the grid electrode of the NMOS transistor of the transmission transistor M0 and the grid electrode of the NMOS transistor of the transmission transistor M1 are connected to an enabling signal line RE, and the grid electrode of the PMOS transistor of the transmission transistor M0 and the grid electrode of the PMOS transistor of the transmission transistor M1 are both connected with an enabling inverse signal line RE _ N; the second end of the transmission tube M0 and the second end of the transmission tube M1 are respectively connected with the two ends of the second-stage sensitive amplifier.
As a further improvement of the invention, the main DQ read control circuit is connected with the second-stage sensitive amplifier through a thick-gate NMOS tube.
As a further improvement of the present invention, the main DQ read control circuit includes a thick gate NMOS transistor HN0, a thick gate NMOS transistor HN1, a precharge PMOS transistor P10, a precharge PMOS transistor P11, and an equalization PMOS transistor P12;
the gates of the PRE-charge PMOS transistor P10, the PRE-charge PMOS transistor P11 and the equalizing PMOS transistor P12 are connected to a PRE-charge inverse signal line MDQ _ PRE _ N, the drain of the PRE-charge PMOS transistor P10 is connected with the source of the equalizing PMOS transistor P12 and then connected with the source of the thick-gate NMOS tube HN0, and the source of the thick-gate NMOS tube HN0 is connected with the amplification line MDQ of the first-stage sense amplifier; the drain electrode of the pre-charging PMOS transistor P11 is connected with the drain electrode of the equalizing PMOS transistor P12 and then is connected with the source electrode of a thick-gate NMOS tube HN1, and the source electrode of the thick-gate NMOS tube HN1 is connected with an amplifying line MDQ _ N of the first-stage sensitive amplifier; the grid electrode of the thick-grid NMOS tube HN0 and the grid electrode of the thick-grid NMOS tube HN1 are connected to an enabling signal line RE, and the drain electrode of the thick-grid NMOS tube HN0 and the drain electrode of the thick-grid NMOS tube HN1 are respectively connected with two ends of the second-stage sensitive amplifier.
A write-back method of a write-back circuit for improving the read stability of a sensitive amplifier comprises the following steps:
the first-stage sensitive amplifier amplifies data for the first time and transmits the amplified data for the first time to an amplifying line;
the main DQ read control circuit transmits the data amplified for the first time to a second-stage sensitive amplifier;
the second-stage sensitive amplifier amplifies the amplified data for the second time;
and the main DQ read control circuit writes the data amplified for the second time back to the amplifying line, thereby writing back to the first-stage sense amplifier, and recovers the voltage peak coupled on the bit line BL or BL _ N of the first-stage sense amplifier.
As a further improvement of the invention, the main DQ read control circuit is connected with the second-stage sense amplifier through a transmission gate or the main DQ read control circuit is connected with the second-stage sense amplifier through a thick-gate NMOS tube.
As a further improvement of the invention, the second-stage sense amplifier is connected with the MDQ and the inverse signal MDQ _ N thereof through the transmission gate, the transmission gate is simultaneously controlled by the read enable signal RE and the read enable signal inverse RE _ N, when the second-stage sense amplifier works, the signals RE and RE _ N are both effective, and the transmission gate can write the data amplified for the second time to the MDQ and the inverse signal MDQ _ N thereof and then write the data back to the BL/BL _ N through the MDQ/MDQ _ N.
As a further improvement of the invention, the second-stage sense amplifier is connected with the MDQ and an inverse signal MDQ _ N thereof through a thick-gate NMOS tube, the threshold voltage of the thick-gate NMOS tube is higher than that of a typical NMOS tube, the grid electrode of the thick-gate NMOS tube is connected with a read enable signal RE, when the second-stage sense amplifier works, the read enable signal RE is kept effective and has the voltage of peak voltage VPP, the peak voltage VPP is higher than a power supply voltage VDD, and according to the transmission principle of the NMOS tube, the thick-gate NMOS tube with the grid voltage VPP can transmit data amplified for the second time to the MDQ and the inverse signal MDQ _ N thereof and then write back to BL/BL _ N through the MDQ/MDQ _ N.
The second amplified data are high-level VDD and low-level VSS signals amplified by the second-stage sensitive amplifier
Compared with the prior art, the invention has the following advantages:
compared with the traditional memory read operation data amplification circuit, the invention has the greatest difference that a data path between the first-stage sensitive amplifier and the second-stage sensitive amplifier is kept in the process that the second-stage sensitive amplifier realizes the second amplification of data. The working voltage of a first-stage sensitive amplifier in the memory read operation data amplification circuit is different from that of a main DQ control circuit, wherein VBLH in the first-stage sensitive amplifier is smaller than VDD of the read control circuit. The voltage of the gate control signal column selection line CSL of the NMOS transistor N10 and the NMOS transistor N11 connecting the first stage sense amplifier and the main DQ control circuit is higher than VBLH, so that the high level VDD on the MDQ/MDQ _ N line can cause an unexpected voltage peak to be coupled out on the low level of BL or BL _ N, and even cause data to be disturbed and lost.
According to the traditional read operation data amplification circuit, an MDQ and a second-stage sense amplifier are connected through a PMOS pipe P0 and a PMOS pipe P1, when data pass through the MDQ from a first-stage sense amplifier and generate voltage difference at two ends of the second-stage sense amplifier, the PMOS pipe P0 and the PMOS pipe P1 are conducted, when the voltage difference established between MA and MA _ N reaches the offset voltage of the second-stage sense amplifier, the PMOS pipe P0 and the PMOS pipe P1 are disconnected, SAE is effective, the second-stage sense amplifier amplifies the voltage difference on the MA and MA _ N, and the second-stage sense amplifier is isolated from the first-stage sense amplifier.
In the first scheme, the MDQ and the second-stage sensitive amplifier are connected through the pass tube M0 and the pass tube M1, in the process that data pass through the MDQ from the first-stage sensitive amplifier and generate voltage difference at two ends of the second-stage sensitive amplifier, the pass tube M0 and the pass tube M1 are conducted, when the voltage difference established between the MA and the MA _ N reaches the offset voltage of the second-stage sensitive amplifier, the SAE is effective, the pass tube M0 and the pass tube M1 are kept conducted, and when the second-stage sensitive amplifier amplifies the voltage difference between the MA and the MA _ N, the pass tube M0 and the pass tube M1 can effectively transmit the high level and the low level, so that the amplified signals are written back to the first-stage sensitive amplifier.
In the second scheme, the MDQ and the second-stage sense amplifier are connected through thick-gate NMOS tubes HN0 and HN 1. When the voltage difference between MA and MA _ N reaches the offset voltage of the second-stage sensitive amplifier, SAE is effective, HN0 and HN1 are kept conductive, and when the voltage difference between MA and MA _ N is amplified by the second-stage sensitive amplifier, the HN0 and HN1 can effectively transmit high level and low level, so that the amplified signal is written back to the first-stage sensitive amplifier.
Therefore, compared with the traditional read operation data amplifying circuit, the two schemes in the invention can well transmit high level and low level, realize the data write-back to the first-stage sensitive amplifier, recover the voltage peak coupled on BL or BL _ N, and even rewrite the error data generated by interference. The read stability of the first-stage sensitive amplifier is improved, and the reliability of read operation is improved.
Drawings
Fig. 1 is a schematic diagram of a conventional memory read operation data amplification circuit.
FIG. 2 is a schematic diagram of a write back circuit for improving the read stability of a sense amplifier.
FIG. 3 is a schematic diagram of a second write back circuit for improving the read stability of a sense amplifier.
Fig. 4 is a waveform diagram of a conventional memory read operation data amplifying circuit.
FIG. 5 is a diagram of a data loss waveform of an amplifier of a conventional data amplifying circuit for a memory read operation.
FIG. 6 is a waveform diagram of the present invention incorporating a write back circuit to improve the read stability of the sense amplifier.
Detailed Description
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description of the embodiments of the present invention with reference to the accompanying drawings and examples is given by way of illustration and not limitation.
As shown in fig. 2, a write-back circuit for improving the read stability of a sense amplifier according to the present invention is formed by connecting a second stage sense amplifier to an MDQ and its inverse signal MDQ _ N through a transmission gate, wherein the transmission gate is controlled by a read enable signal RE and a read enable signal inverse RE _ N at the same time, when the second stage sense amplifier operates, the signals RE and RE _ N are both valid, and the transmission gate can transmit the high level and the low level amplified by the second stage sense amplifier to the MDQ and its inverse signal MDQ _ N, and then write back to BL/BL _ N through the MDQ/MDQ _ N.
As shown in fig. 3, the second write-back circuit for improving the read stability of the sense amplifier is to connect the second stage sense amplifier to the MDQ and its inverse signal MDQ _ N through a thick gate NMOS transistor, the gate of the thick gate NMOS transistor is connected to a read enable signal RE, and when the second stage sense amplifier operates, the read enable signal RE is kept valid and the voltage is the peak voltage VPP, so the thick gate NMOS transistor can transmit the high level and low level signals amplified by the second stage sense amplifier to the MDQ and its inverse signal MDQ _ N, and then write back to BL/BL _ N through the MDQ/MDQ _ N.
Compared with the traditional memory read operation data amplification circuit, the invention has the greatest difference that a data path between the first-stage sensitive amplifier and the second-stage sensitive amplifier is kept in the process that the second-stage sensitive amplifier realizes the second amplification of data. The working voltages of a first-stage sensitive amplifier and an MDQ reading control circuit in the memory reading operation data amplifying circuit are different, wherein VBLH in the first-stage sensitive amplifier is smaller than VDD of the reading control circuit. The voltage of the gate control signal column selection line CSL of the NMOS transistor N10 and the NMOS transistor N11 connecting the first stage sense amplifier and the main DQ control circuit is higher than VBLH, so that the high level VDD on the MDQ/MDQ _ N line can cause an unexpected voltage peak to be coupled out on the low level of BL or BL _ N, and even cause data to be disturbed and lost.
In the first scheme, the MDQ and the second-stage sensitive amplifier are connected through the transmission tube M0 and the transmission tube M1, when data generate voltage difference at two ends of the second-stage sensitive amplifier from the first-stage sensitive amplifier through the amplification line MDQ, the transmission tube M0 and the transmission tube M1 are conducted, when the voltage difference established between the MA and the MA _ N reaches the offset voltage of the second-stage sensitive amplifier, the SAE is effective, the transmission tube M0 and the transmission tube M1 are conducted, and when the voltage difference between the MA and the MA _ N is amplified by the second-stage sensitive amplifier, the transmission tube M0 and the transmission tube M1 can effectively transmit high level and low level, so that the amplified signals are written back to the first-stage sensitive amplifier.
In the second scheme, the MDQ and the second-stage sense amplifier are connected through thick-gate NMOS tubes HN0 and HN 1. When the voltage difference between MA and MA _ N reaches the offset voltage of the second-stage sensitive amplifier, SAE is effective, HN0 and HN1 are kept conductive, and when the voltage difference between MA and MA _ N is amplified by the second-stage sensitive amplifier, the HN0 and HN1 can effectively transmit high level and low level, so that the amplified signal is written back to the first-stage sensitive amplifier.
Therefore, compared with the traditional read operation data amplifying circuit, the two schemes in the invention can well transmit high level and low level, realize the data write-back to the first-stage sensitive amplifier, recover the voltage peak coupled on BL or BL _ N, and even rewrite the error data generated by interference. The read stability of the first-stage sensitive amplifier is improved, and the reliability of read operation is improved.
The invention is described in detail below with reference to the figures and specific examples.
Example 1
Referring to fig. 2, fig. 2 is a write-back circuit for improving the read stability of a sense amplifier according to the present invention, which includes a first-stage sense amplifier, an NMOS transistor N10 and an NMOS transistor N11 connected to the first-stage sense amplifier and a main DQ read control circuit; the pre-charge PMOS transistor P10, the PMOS transistor P11 and the equalizing PMOS transistor P12 form a pre-charge circuit of the main DQ, and the pass transistor M0 and the pass transistor M1 are connected with the main DQ read control circuit and the second-stage sense amplifier.
The power supply of the first-stage sense amplifier is connected to VBLH, the sources of the NMOS transistor N10 and the NMOS transistor N11 are respectively connected to the bit line BL and the bit line bar signal BL _ N, the gates of the NMOS transistor N10 and the NMOS transistor N11 are connected to the column selection line CSL signal, and the drains of the NMOS transistor N10 and the NMOS transistor N11 are respectively connected to the amplification line MDQ and the amplification line MDQ _ N.
The gates of PRE-charge PMOS transistors P10 and P11 and equalization PMOS transistor P12 of the main DQ read control circuit are connected to the amplification line MDQ _ PRE _ N, the sources of P10 and P11 are connected to VDD, the drain of P10 is connected to the amplification line MDQ, the drain of P11 is connected to the amplification line MDQ _ N, and the source and drain of equalization transistor P12 are connected to MDQ and MDQ _ N, respectively. The first end of a transmission tube M0 is connected with the MDQ, the first end of a transmission tube M1 is connected with the MDQ _ N, the grid electrode of an NMOS tube of M0 and the grid electrode of an NMOS tube of M1 are connected with an enabling signal line RE, the grid electrode of a PMOS tube of M0 and the grid electrode of a PMOS tube of M1 are connected with an enabling signal inverse RE _ N, the second end of M0 and the second end of M1 are respectively connected with the MA/MA _ N of the second-stage sensitive amplifier, the power supply of the second-stage sensitive amplifier is connected with VDD, and the enabling signal is SAE. It should be noted that the first end and the second end of M0 and M1 are the connecting ends in the transmission direction of the transmission tube, i.e. the source end or the drain end of the MOS tube.
The operation principle of the first write-back circuit for improving the read stability of the sense amplifier will now be described with reference to fig. 6, which is a waveform diagram of the write-back circuit for improving the read stability of the sense amplifier.
In the non-working stage, the first-stage sensitive amplifier and the second-stage sensitive amplifier do not work, the bit line BL/BL _ N is precharged to the bit line precharge voltage, the NMOS tubes N10 and N11 are turned off, the precharge PMOS tube P10, the PMOS tube P11 and the equalizing tube P12 are turned on, the amplifying line MDQ/MDQ _ N is precharged, the inverse MDQ _ PRE _ N is low, and the MDQ/MDQ _ N is kept at the power supply voltage VDD. Pass transistor M0, pass transistor M1 are turned off, precharge PMOS transistor P4, PMOS transistor P5 and equalizing transistor P6 are turned on, MA/MA _ N precharge inverse signal MA _ PRE _ N is low, MA/MA _ N is maintained at power supply voltage VDD, and sense amplifier enable SAE of the second stage is low.
At the beginning of a read operation, the charge on the memory cell causes BL to be pulled up from the bit line precharge voltage through charge sharing, creating a voltage difference between BL and BL _ N until the voltage difference reaches the offset voltage of the first sense amplifier, which operates to amplify the voltage difference on BL/BL _ N to a recognizable digital signal. The MDQ precharge bar signal MDQ _ PRE _ N is pulled high, P10-P12 are turned off, precharge bar MA _ PRE _ N is high, and P4-P6 are turned off.
In the signal transmission phase, the column selection line CSL is active, N10-N11 is turned on, the read enable RE is the power voltage VDD, the inverse signal RE _ N is the ground voltage VSS, M0-M1 are turned on, the MDQ is pulled down by the low level on the BL, the inverse signal MDQ _ N is kept at VDD, the pulled down MDQ pulls MA down, the inverse signal MA _ N is kept at VDD, until a certain voltage difference is established between MA and MA _ N, until the voltage difference reaches the offset voltage of the second-stage sense amplifier.
In the working stage of the second-stage sense amplifier, a read enable RE keeps VDD, a back signal RE _ N keeps VSS, M0-M1 keeps an on state, a second-stage sense amplifier enable SAE is high, the second-stage sense amplifier starts to amplify the voltage difference between MA and MA _ N, and in the process of continuous discharge of MA, low level and high level on MA and MA _ N can be written back to the first-stage sense amplifier well on average through transmission tubes M0-M1; after a period of write-back time, the column select line CSL is low, N10-N11 is turned off, the read enable RE is VSS, the inverse signal RE _ N is VDD, and M0-M1 are turned off; SAE is low and the data amplification phase ends. MDQ _ PRE _ N is pulled low and MDQ/MDQ _ N is precharged to VDD. MA _ PRE _ N is pulled low and MA/MA _ N is precharged to VDD.
Example 2
FIG. 3 is a schematic diagram of a second write-back circuit for improving the read stability of a sense amplifier. The circuit comprises a first-stage sensitive amplifier, an NMOS transistor N10 and an NMOS transistor N11 are connected with the first-stage sensitive amplifier and a main DQ read control circuit; the pre-charge PMOS transistor P10, the PMOS transistor P11 and the equalizing PMOS transistor P12 constitute a pre-charge circuit for the main DQ, and the thick gate NMOS transistor HN0 and the transistor HN1 connect the main DQ and the second stage sense amplifier.
The power supply of the first-stage sense amplifier is connected to VBLH, the sources of NMOS transistor N10 and NMOS transistor N11 are connected to the bit line BL and bit line bar signal BL _ N, the gates of N10 and N11 are connected to the column selection line CSL signal, and the drains of N10 and N11 are respectively connected to the amplifying line MDQ/MDQ _ N.
The gates of PRE-charge PMOS transistors P10 and P11 and equalization PMOS transistor P12 of the main DQ read control circuit are connected to MDQ _ PRE _ N, the sources of P10 and P11 are connected to VDD, the drain of P10 is connected to MDQ, the drain of P11 is connected to MDQ _ N, and the source and drain of equalization transistor P12 are connected to MDQ and MDQ _ N, respectively. The source of the thick-gate NMOS tube HN0 is connected with the MDQ, the source of the thick-gate NMOS tube HN1 is connected with the MDQ _ N, the grid of HN0 and the grid of HN1 are connected with an enabling signal line RE, the drain of HN0 and the drain of HN0 are respectively connected with MA/MA _ N of the second-stage sensitive amplifier, the power supply of the second-stage sensitive amplifier is connected with VDD, and the enabling signal is SAE.
The operation of the second improved sense amplifier read stability write back circuit is now described with reference to the waveform diagram of FIG. 6 added to the write back circuit to improve sense amplifier read stability.
In the non-working stage, the first-stage sensitive amplifier and the second-stage sensitive amplifier do not work, the bit line BL/BL _ N is precharged to the bit line precharge voltage, the NMOS tubes N10 and N11 are turned off, the precharge PMOS tube P10, the PMOS tube P11 and the equalizing tube P12 are turned on, the precharge inverse MDQ _ PRE _ N of the amplifying line MDQ/MDQ _ N is low, and the MDQ/MDQ _ N is kept at the power supply voltage VDD. The read enable signal RE is low, the thick gate NMOS transistors HN0 and HN1 are turned off, the PRE-charge PMOS transistor P4, the PMOS transistor P5 and the equalizing transistor P6 are turned on, the MA/MA _ N PRE-charge inverse MA _ PRE _ N is low, the MA/MA _ N is kept at the power supply voltage VDD, and the sense amplifier enable SAE of the second stage is low.
At the beginning of a read operation, the charge on the memory cell causes BL to be pulled up from the bit line precharge voltage through charge sharing, creating a voltage difference between BL and BL _ N until the voltage difference reaches the offset voltage of the first sense amplifier, which operates to amplify the voltage difference on BL/BL _ N to a recognizable digital signal. The MDQ precharge bar signal MDQ _ PRE _ N is pulled high, P10-P12 are turned off, precharge bar MA _ PRE _ N is high, and P4-P6 are turned off.
During the signaling phase, the column select line CSL is asserted, N10-N11 is turned on, the read enable RE is the peak voltage VPP, HN0-HN1 is turned on, the low level on BL pulls down the MDQ, and its inverse MDQ _ N remains at VDD. Through the turned-on HN0-HN1 tube, the pulled-down MDQ pulls down MA, and the inverse signal MA _ N is kept at VDD until a certain voltage difference is established between MA and MA _ N until the voltage difference reaches the offset voltage of the second-stage sense amplifier.
In the working phase of the second-stage sense amplifier, the read enable RE keeps VPP, and HN0-HN1 keeps an on state; enabling SAE to be high, starting to amplify the voltage difference between MA and MA _ N by the second-stage sense amplifier, and writing back the low level and the high level on MA and MA _ N to the first-stage sense amplifier in a good average manner, especially writing back the low level, through a thick-gate NMOS tube HN0-HN1 with the gate voltage VPP in the process of continuous discharge of MA; after a period of write-back time, the column select line CSL is low, N10-N11 is turned off, the read enable RE is VSS, and HN0-HN1 is turned off; SAE is low and the data amplification phase ends. MDQ _ PRE _ N is pulled low and MDQ/MDQ _ N is precharged to VDD. MA _ PRE _ N is pulled low and MA/MA _ N is precharged to VDD.
Both schemes can realize the transmission of high level and low level, realize the data write-back to the first-stage sensitive amplifier, recover the voltage peak coupled on BL or BL _ N, and even rewrite the error data generated by interference. Therefore, the reading stability of the first-stage sensitive amplifier is improved, and the reliability of reading operation is improved.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention have been described in further detail, it should be understood that the above are only exemplary embodiments of the present invention, and the embodiments of the present invention should not be considered as limited thereto.
Although specific embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the specific embodiments described above, which are intended to be illustrative, instructive, and not restrictive. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. A write back circuit for improving read stability of a sense amplifier, comprising:
a first-stage sense amplifier: for amplifying the data for the first time and transferring the amplified data onto an amplifying line;
a second-stage sense amplifier: the second amplification is carried out on the first amplification data;
main DQ read control circuit: the first-stage sense amplifier is connected with the second-stage sense amplifier; and the first-stage sensitive amplifier and the second-stage sensitive amplifier are controlled to be switched on or switched off;
when the amplifier is switched on, the amplifier is used for transmitting the first amplified data to a second-stage sensitive amplifier for secondary amplification; and writing the second amplified data back to the amplifying line so as to write back to the first-stage sense amplifier, recovering a voltage peak coupled to the bit line BL or BL _ N of the first-stage sense amplifier, and maintaining a data path between the first-stage sense amplifier and the second-stage sense amplifier by the main DO read control circuit in the process of amplifying the first amplified data by the second sense amplifier.
2. The write back circuit for improving the read stability of a sense amplifier of claim 1, wherein the main DQ read control circuit is configured to write back the further amplified high level data, low level data or intermediate level data onto the amplifying line.
3. The write back circuit for improving the read stability of a sense amplifier according to claim 1, wherein the main DQ read control circuit is connected to the sense amplifier of the second stage through a transmission gate.
4. The write back circuit for improving the read stability of the sense amplifier of claim 3, wherein the master DQ read control circuit comprises a pass transistor M0, a pass transistor M1, a pre-charge PMOS transistor P10 and a pre-charge PMOS transistor P11, and an equalization PMOS transistor P12;
the gates of the PRE-charge PMOS transistor P10, the PRE-charge PMOS transistor P11 and the equalizing PMOS transistor P12 are connected to a PRE-charge inverse signal line MDQ _ PRE _ N, the source of the PRE-charge PMOS transistor P10 and the source of the PRE-charge PMOS transistor P11 are connected to a power supply voltage VDD, the drain of the PRE-charge PMOS transistor P10 is connected to the source of the equalizing PMOS transistor P12 and then connected to the first end of a transmission tube M0, and the first end of the transmission tube M0 is connected to an amplification line MDQ of the first-stage sense amplifier; the drain electrode of the pre-charging PMOS transistor P11 is connected with the drain electrode of the equalizing PMOS transistor P12 and then is connected with the first end of a transmission tube M1, and the first end of the transmission tube M1 is connected with an amplifying line MDQ _ N of the first-stage sensitive amplifier; the grid electrode of the NMOS transistor of the transmission transistor M0 and the grid electrode of the NMOS transistor of the transmission transistor M1 are connected to an enabling signal line RE, and the grid electrode of the PMOS transistor of the transmission transistor M0 and the grid electrode of the PMOS transistor of the transmission transistor M1 are both connected with an enabling inverse signal line RE _ N; the second end of the transmission tube M0 and the second end of the transmission tube M1 are respectively connected with the two ends of the second-stage sensitive amplifier.
5. The write-back circuit for improving the read stability of the sense amplifier of claim 1, wherein the main DQ read control circuit is connected to the second stage sense amplifier through a thick gate NMOS transistor.
6. The write back circuit of claim 5, wherein the main DQ read control circuit comprises a thick gate NMOS transistor HN0, a thick gate NMOS transistor HN1, a pre-charge PMOS transistor P10 and a pre-charge PMOS transistor P11, and an equalization PMOS transistor P12;
the gates of the PRE-charge PMOS transistor P10, the PRE-charge PMOS transistor P11 and the equalizing PMOS transistor P12 are connected to a PRE-charge inverse signal line MDQ _ PRE _ N, the drain of the PRE-charge PMOS transistor P10 is connected with the source of the equalizing PMOS transistor P12 and then connected with the source of the thick-gate NMOS tube HN0, and the source of the thick-gate NMOS tube HN0 is connected with the amplification line MDQ of the first-stage sense amplifier; the drain electrode of the pre-charging PMOS transistor P11 is connected with the drain electrode of the equalizing PMOS transistor P12 and then is connected with the source electrode of a thick-gate NMOS tube HN1, and the source electrode of the thick-gate NMOS tube HN1 is connected with an amplifying line MDQ _ N of the first-stage sensitive amplifier; the grid electrode of the thick-grid NMOS tube HN0 and the grid electrode of the thick-grid NMOS tube HN1 are connected to an enabling signal line RE, and the drain electrode of the thick-grid NMOS tube HN0 and the drain electrode of the thick-grid NMOS tube HN1 are respectively connected with two ends of the second-stage sensitive amplifier.
7. A write-back method of a write-back circuit for improving the read stability of a sensitive amplifier is characterized by comprising the following steps:
the first-stage sensitive amplifier amplifies data for the first time and transmits the amplified data for the first time to an amplifying line;
the main DQ read control circuit transmits the data amplified for the first time to a second-stage sensitive amplifier;
the second-stage sensitive amplifier amplifies the amplified data for the second time;
the main DQ read control circuit writes the data amplified for the second time back to the amplifying line, so as to write back to the first-stage sense amplifier, and recovers the voltage peak coupled on the bit line BL or BL _ N of the first-stage sense amplifier, and in the process that the second sense amplifier amplifies the data amplified for the first time, the main DO read control circuit keeps the data path between the first-stage sense amplifier and the second-stage sense amplifier.
8. The method of claim 7, wherein the write-back circuit comprises a first write-back circuit for improving the read stability of the sense amplifier,
the main DQ reading control circuit is connected with the second-stage sensitive amplifier through a transmission gate or the main DQ reading control circuit is connected with the second-stage sensitive amplifier through a thick-gate NMOS tube.
9. The method of claim 8, wherein the method for improving write back of a sense amplifier read stability comprises,
the second-stage sensitive amplifier is connected with the MDQ and the inverse signal MDQ _ N thereof through the transmission gate, the transmission gate is simultaneously controlled through the read enable signal RE and the read enable signal inverse RE _ N, when the second-stage sensitive amplifier works, the signals RE and RE _ N are both effective, and the transmission gate can transmit the data amplified for the second time to the MDQ and the inverse signal MDQ _ N thereof and write back to BL/BL _ N through the MDQ/MDQ _ N.
10. The method of claim 8, wherein the method for improving write back of a sense amplifier read stability comprises,
the second-stage sense amplifier, the MDQ and a counter signal MDQ _ N thereof are connected through a thick-gate NMOS tube, a grid electrode of the thick-gate NMOS tube is connected with a read enabling signal RE, when the second-stage sense amplifier works, the read enabling signal RE is kept effective and the voltage is a peak voltage VPP, the thick-gate NMOS tube can transmit data amplified for the second time to the MDQ and the counter signal MDQ _ N thereof and then write back to BL/BL _ N through the MDQ/MDQ _ N;
the second amplified data are high level and low level signals.
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