CN110825386B - Code compiling method and device and storage medium - Google Patents
Code compiling method and device and storage medium Download PDFInfo
- Publication number
- CN110825386B CN110825386B CN201911061952.3A CN201911061952A CN110825386B CN 110825386 B CN110825386 B CN 110825386B CN 201911061952 A CN201911061952 A CN 201911061952A CN 110825386 B CN110825386 B CN 110825386B
- Authority
- CN
- China
- Prior art keywords
- instruction
- node
- jump
- assembly
- directed graph
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 230000009191 jumping Effects 0.000 claims description 17
- 230000009466 transformation Effects 0.000 claims description 16
- 238000001514 detection method Methods 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 230000002265 prevention Effects 0.000 abstract description 4
- 230000014509 gene expression Effects 0.000 description 11
- 238000004590 computer program Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/53—Decompilation; Disassembly
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
The invention discloses a compiling method and device of codes and a storage medium. Wherein the method comprises the following steps: acquiring a byte code file obtained by compiling a first source code file of a target application; performing disassembly operation on the byte code file to obtain an assembly instruction text file; decompiling operation is carried out on the assembly instruction text file, and a second source code file of the target application is obtained, wherein the assembly instruction text file comprises: the jump instruction in the assembly instruction section and the jump relation between the instructions determine the grammar structure of the target code corresponding to the assembly instruction section in the second source code file according to the jump instruction and the jump relation, thereby realizing the technical effect of determining the target code prevention structure according to the jump instruction in the assembly instruction text file and the jump relation between the instructions, and further solving the technical problem of singleness of the code decompilation mode in the prior art.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a method and apparatus for compiling a code, and a storage medium.
Background
Lua is a development language commonly used in game development. The developer typically compiles the lua source code into bytecode using luac or luajit, which is stored in the installation package of the game. lua is a dynamic language, and by compiling the lua program only it is guaranteed that no grammar errors occur, most of which will occur during operation. Meanwhile, the existing lua detection tool cannot directly detect luajit byte codes.
Existing LuaJIT decompilation exists in two open source projects, luaJIT Raw-Bytecode Decompiler (LJD), luaJIT-decomp. For an actual large game item, neither can work properly. Problems exist including: unexpected crashes in the middle of operation, data loss, and unsupported various lua grammar structures, and decompiling results have serious grammar problems and cannot be suitable for decompiling of actual projects.
In view of the above problems, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the invention provides a compiling method and device of codes and a storage medium, which at least solve the technical problem of singleness of a decompiling mode of codes in the prior art.
According to an aspect of an embodiment of the present invention, there is provided a compiling method of a code, including: acquiring a byte code file obtained by compiling a first source code file of a target application; performing disassembly operation on the byte code file to obtain an assembly instruction text file; decompiling the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises: and determining the grammar structure of the target code corresponding to the one section of assembly instruction in the second source code file according to the jump instruction and the jump relation between the jump instruction and the instruction in the one section of assembly instruction.
According to another aspect of the embodiment of the present invention, there is also provided a compiling apparatus for a code, including: the acquisition unit is used for acquiring a byte code file obtained by compiling a first source code file of the target application; the assembly unit is used for performing disassembly operation on the byte code file to obtain an assembly instruction text file; the decompilation unit is used for decompiling the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises: and determining the grammar structure of the target code corresponding to the one section of assembly instruction in the second source code file according to the jump instruction and the jump relation between the jump instruction and the instruction in the one section of assembly instruction.
According to a further aspect of embodiments of the present invention, there is also provided a computer-readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the compiling method of the code described above at runtime.
According to still another aspect of the embodiments of the present invention, there is further provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the compiling method of the code by the computer program.
In the embodiment of the invention, a byte code file obtained by compiling a first source code file of a target application is obtained; performing disassembly operation on the byte code file to obtain an assembly instruction text file; decompilation operation is carried out on the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises jump instructions in a section of assembly instructions and jump relations among the instructions, and a grammar structure of target codes corresponding to the section of assembly instructions in the second source code file is determined according to the jump instructions and the jump relations, so that the technical effect of determining a target code prevention structure according to the jump instructions in the assembly instruction text file and the jump relations among the instructions is achieved, and further the technical problem of singleness of a code decompilation mode in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a flow chart of a compiling method of a code according to an embodiment of the present invention;
FIG. 2 is a schematic flow diagram of disassembly and decompilation in accordance with a preferred embodiment of the present invention;
FIG. 3 is a logic condition analysis flow diagram suitable for use with luajit in accordance with a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a process for restoring a and b or c to assembler instructions in accordance with a preferred embodiment of the present invention;
fig. 5 is a schematic structural view of a compiling apparatus for a code according to an embodiment of the present invention;
fig. 6 is a schematic structural view of a compiling apparatus for still another code according to an embodiment of the present invention;
fig. 7 is a schematic structural view of an electronic device for compiling code according to an embodiment of the invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an embodiment of the present invention, there is also provided a method embodiment of a compiling method of a code, it should be noted that the steps shown in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that herein.
The compiling method of the code according to the embodiment of the present invention will be described in detail.
Fig. 1 is a flowchart of a compiling method of a code according to an embodiment of the invention, as shown in fig. 1, the compiling method of the code comprising the steps of:
step S102, obtaining a byte code file obtained by compiling a first source code file of a target application.
Step S104, disassembling the byte code file to obtain an assembly instruction text file.
Step S106, decompiling operation is carried out on the assembly instruction text file, and a second source code file of the target application is obtained, wherein the assembly instruction text file comprises: and determining the jump instruction and the jump relation between the instructions in the section of assembly instruction, and determining the grammar structure of the target code corresponding to the section of assembly instruction in the second source code file according to the jump instruction and the jump relation.
Through the steps, a byte code file obtained by compiling a first source code file of a target application is obtained; performing disassembly operation on the byte code file to obtain an assembly instruction text file; decompiling operation is carried out on the assembly instruction text file, and a second source code file of the target application is obtained, wherein the assembly instruction text file comprises: the jump instruction in the assembly instruction section and the jump relation between the instructions determine the grammar structure of the target code corresponding to the assembly instruction section in the second source code file according to the jump instruction and the jump relation, thereby realizing the technical effect of determining the target code prevention structure according to the jump instruction in the assembly instruction text file and the jump relation between the instructions, and further solving the technical problem of singleness of the code decompilation mode in the prior art. Further, the byte code file is obtained through compiling the source code, then the byte code file is disassembled, the disassembled source code file is obtained, and the disassembled source code file has high readability, no grammar error and no data loss.
In the solution provided in step S102, the first source code file may be a code file of a target application, where the target application may include, but is not limited to, a game application, an instant messaging application, a shopping application, a payment application, and the like. The first source code file may be a code file formed by a dynamic type programming language lua. Wherein compiling is a process of converting a high-level programming language into another low-level language. That is, a high-level language of a game source code file programmed by the lua language is converted into a low-level language, resulting in a bytecode file.
For example, in the case that the target application is a game application, vulnerability detection is performed on a code operated by a game, which may first assemble the code operated by the game in a low-level language to obtain a bytecode file, and disassemble the bytecode file to obtain an assembly instruction text file; and decompiling the assembly instruction file to obtain the source code of the game application. Code obtained through decompilation is detected, and whether the source code of the game application has a vulnerability is determined. The source code file after the anti-assembly has high readability, no grammar error and no data loss, thereby ensuring the accuracy of detecting the game source code.
In the scheme provided in step S104, the disassembly is used to translate the binary file corresponding to the luajit bytecode into a readable assembly text file.
The Luajit compiler provides a Luajit disassembler at the same time, and the disassembler can output a Luajit assembler instruction text file. And each version of byte code corresponds to a corresponding compiler, and the output assembly instruction text files have the same format.
In practical application, the following is described as an example:
Line 3, line 0001TDUP 0 (array {1 2 4} is encoded into string number 0, string number 0 in string array is changed into variable, variable is stored into register 0)
Line 4, 0002GGET 1 (string number 1 in string array becomes variable, store variable into register 1)
Line 8, 0006GGET 1 (string number 2 in string array becomes variable, store variable into register 5)
lastlinedfained 32 indicates the location of the assembler instruction corresponding to the source code
The stackslots: the number of registers used by the assembler instruction
nestDepth
Numbering of the code of protoIndex
gccon sts {1 2 4}, supplementing assembly data (New addition)
LOCALVAR: name self, start 0, end 13 (New addition)
self (local variable) =supplier
The disassembler may output assembler instructions. But does not output table data, symbol information corresponding to local variable names, and the like.
By reading the source code of the luajit, the internal format of the luajit byte code file can be obtained, so that table information and symbol information can be derived. The sign information includes the variable name, the instruction start address range in which the variable takes effect.
The Table information may analyze correspondence with the source code through a TDUP instruction.
The symbol information may be mapped by the instruction address start range.
In the scheme provided in step S106, the disassembling operation is performed on the byte code file of the low-level language, so as to obtain the assembly instruction text file. The jit compiler of lua. Lua may be executed or the lua source code may be compiled into binary bytecodes. Decompiling: the reverse of the compilation process. The compiled bytecode is generally not suitable for manual reading.
In practical application, the decompiler reads the assembly text file in step S104, and generates the lua source code file.
In the Luajit bytecode, if conditions, elseif, else, break, while conditions, repeat conditions, compare operation expressions (a=a > b), logical operation expressions (e.g. a=a or true) and other lua grammar structures are all implemented by jmp instructions. The greatest challenge in compiling is to reversely analyze the grammar structure corresponding to jmp through the jmp instruction. The if condition, elseif, else, break, while condition, repeat condition are all corresponding to jmp (1-to-many) when compiled.
As an alternative embodiment, decompiling the assembler instruction text file may include: and decompiling the first section of assembly instruction into a first comparison operation assignment code under the condition that the last instruction of the first jump instruction in the first section of assembly instruction in the assembly instruction text file is a comparison instruction, the instruction to which the first jump instruction jumps is a first loading instruction and the data value loaded by the first loading instruction is in a first preset range, wherein the first comparison operation assignment code comprises one comparison operation.
When the last instruction of the first jump instruction in the first section of assembly instruction in the assembly instruction text file is a comparison instruction, the instruction jumped to by the first jump instruction is a load instruction, and the data value loaded by the load instruction is within a first predetermined range, decompiling the first section of assembly instruction into the first comparison operation assignment code may include: and decompiling the first section of assembly instruction into a first comparison operation assignment code under the conditions that the last instruction of the first jump instruction is a comparison instruction, the instruction to which the first jump instruction jumps is a first loading instruction, the value of data loaded by the first loading instruction is in a first preset range, the last instruction of the first loading instruction is a second jump instruction, the last instruction of the second jump instruction is a second loading instruction, and the value of data loaded by the second loading instruction is in a second preset range.
In practical applications, the assignment operation expression is analyzed from the instruction as a whole. For example: local a=a > b, where a > b corresponds to instructions to 0003 to 0009 (compiler-own way), instructions of 0003 to 0009 may be taken as a whole.
jmp: jump to the middle of the assembler instruction of two pieces of loading data ()
KPRI, constant 2 is loaded into register 1, a > b
ISLT，1 is less than 0
The 1 st JMP is preceded by a compare assembler instruction, and the jump to address is a data load assembler instruction, and the number of loads is in a predetermined range, 0.1, followed by a JMP instruction, also a load instruction.
It should be noted that a > b in the similar statement print (a, a > b) also belongs to the compare operation assignment.
As an alternative embodiment, decompiling the assembler instruction text file may include the following:
mode one: and decompiling the second section of assembly instruction into a first logic operation assignment code under the condition that the last instruction of a third jump instruction in the second section of assembly instruction in the assembly instruction text file is a first register data judging instruction, the last instruction of the first register data judging instruction is a third loading instruction, the instruction to which the third jump instruction jumps is a first return loading instruction and the next instruction of the third jump instruction is a fourth loading instruction, wherein the first logic operation assignment code comprises one logic operation.
In practical application, the basic statement of logical operation is connected through an and or operation and is located outside the non-if/elseif/else/while/repeat conditional expression. Such as:
local a＝a and b or c
return d and e or#e
The a and b or c and d and e or#e are logical operation assignment expressions.
The jmp instruction of the assembler instruction corresponding to the expression has obvious characteristics. For example, the assembler instruction corresponding to the expression local a=a and b and c is as follows:
the ISF determines whether the data in the register 0 is False.
jmp: jmp 1 is preceded by ISF, jump to RET0, condition 0004-0007
if 2and 5, execute 7.
And jumping to RET0, and considering the currently corresponding code as a logic operation assignment.
Instructions 0002-0004 assign values to slot 0, and instructions 0005-0007 assign values to slot 0 as well; while 0003 instructions and 0006 instructions have the same jump address.
Mode two: and decompiling the third section of assembly instruction into a second logic operation code under the condition that the last instruction of a fourth jump instruction in a third section of assembly instruction in the assembly instruction text file is a second register data judgment instruction, the last instruction of the second register data judgment instruction is a fifth loading instruction, the instruction to which the fourth jump instruction jumps is a second return loading instruction, the next instruction of the fourth jump instruction is a sixth loading instruction, the next instruction of the sixth loading instruction is a third register data judgment instruction, the next instruction of the third register data judgment instruction is a fifth jump instruction, and the next instruction of the fifth jump instruction is a seventh loading instruction, wherein the second logic operation code comprises two logic operations.
Mode three: constructing a first directed graph according to the assembler instructions in the assembler instruction text file, wherein each node in the first directed graph represents one assembler instruction, the edge of the first directed graph, which points to the second node, represents the assembler instruction represented by the first node and jumps to the assembler instruction represented by the second node, and the edge in the first directed graph has an attribute value for representing a jump condition; and carrying out merging operation on the nodes in the first directed graph to obtain a second directed graph, wherein the merging operation comprises at least one of the following steps: performing and merging on two nodes in the first directed graph, performing or merging on the two nodes in the first directed graph, and performing inverse equivalent transformation on the nodes in the first directed graph; code including logic conditions in the second source code file is determined from the second directed graph.
The merging operation is performed on the nodes in the first directed graph, and obtaining the second directed graph may include the following ways:
mode one: in the first directed graph, when the first jump condition is met, the node a jumps to the node b, no other nodes jump to the node b, and when the first jump condition is not met, both the node a and the node b jump to the same node c, and the node a and the node b are combined to obtain a first combined node, wherein the first combined node jumps to the node c when the first jump condition is not met.
Mode two: and in the first directed graph, when the second jump condition is not met, the node a jumps to the node b, no other nodes jump to the node b, and when the second jump condition is met, both the node a and the node b jump to the same node c, the node a and the node b are subjected to or combination to obtain a second combined node, wherein the second combined node jumps to the node c when the second jump condition is not met.
Mode three: in the first directed graph, when the third jump condition is not met, the node a jumps to the node b, when the third jump condition is met, the node a jumps to the node c, and the node a and the node b cannot be combined and or combined, the equivalent transformation of the inverse of the node a is carried out, so that a first transformation node for replacing the node a is obtained, wherein the first transformation node jumps to the node b when the third jump condition is met, and the first transformation node jumps to the node c when the third jump condition is not met.
Mode four: and repeatedly executing the merging operation on the nodes in the first directed graph until a second directed graph is obtained, wherein the merging and or merging cannot be executed on any two nodes in the second directed graph, and the merging and or merging cannot be executed on any two nodes in a third directed graph obtained by performing the equivalent transformation of inverting any nodes in the second directed graph.
The Lua includes four loops, a numerical value for loop, an iteration for loop, a while loop, and a repeat loop. Both for loops have obvious special diagnosis, e.g. comprising a FORL instruction, FORL instruction. The While LOOP and repeat LOOP also have obvious specificity, both containing LOOP instructions.
As an alternative embodiment, determining the code including the logical condition in the second source code file according to the second directed graph may include: and if the target instruction indicated by the third node corresponding to the if code and the fourth node jumped by the third node in the second directed graph is a non-jump instruction and the previous instruction of the target instruction is an unconditional jump instruction, decompiling the unconditional jump instruction into an else code.
As an alternative embodiment, performing the disassembling operation on the byte code file to obtain the assembly instruction text file may include: and generating a target assembly instruction in the assembly instruction text file, wherein the target assembly is used for encoding target numerical values in a target array in the byte code file into a character string with the number of i, changing the character string with the number of i into target variables, and storing the target variables into a target register.
As an alternative embodiment, after decompiling the assembled text file to obtain the second source code file of the target application, the method may further include: and detecting the second source code file to obtain a detection result, wherein the detection result is used for indicating whether the target application has the loophole.
In connection with the logic analysis of the above embodiments, a preferred embodiment of logic condition analysis is also provided. The logic conditions mainly refer to conditional expressions contained in the while/repeat/if/else statement. Logic conditions typically have a complex structure.
As shown in fig. 2, the disassembly and decompilation flow diagram of the preferred embodiment. Wherein the flow chart comprises the following steps: a step of disassembly and a step of decompilation.
Wherein, the step of disassembling is preceded by obtaining the Luajit bytecode file, and then the process of disassembling includes: identifying a version number, namely identifying the version number applied to the current byte code file; the corresponding Luajit disassembles, namely, the byte code files are assembled in low-level language; and determining the analysis of the assembled file to obtain the assembled file.
The decompilation process includes: preprocessing an instruction; comparing and assigning a logic operation value; circularly identifying; constructing a directed graph CFG; analyzing local variables; directed graph CFG correction; constructing information analysis output; decompiling the function body instruction; generating a function definition global non-function code; outputting a single file decompilation result.
In connection with the logic condition analysis flow diagram as shown in fig. 3, a logic condition analysis flow diagram suitable for luajit is provided. The specific logic condition analysis algorithm is as follows:
Step 1, constructing a CFG;
CFG is a directed graph that contains nodes and edges. A node is an ordered set of instructions and an edge is a jump relationship between nodes. For example, node a includes a jump instruction I whose destination address corresponds to an instruction located at node B, and forms an edge from a to B. The sideband has an attribute value indicating whether the jump condition is true or false.
Instructions within the CFG node only allow the last instruction to contain a jump instruction and do not allow other instructions to jump to intra-node instructions. (logical operation assignment and conditional operation assignment combined instruction is calculated as one instruction)
According to the rule, the instruction of the disassembled file can be divided through the JMP instruction and the UCLO instruction, so that a basic node is obtained. And obtaining the directed edge of the CFG according to the instruction jump relation. It should be noted that if the last instruction of a node is not a jump instruction, the node is connected to the next node.
Step 2, analyzing local variables;
local variable analysis is divided into two cases. If the compilation smears out the debug symbol (without the-g parameter), the following method is used:
in Luajit, non-local variables, expressions, etc. are all split into multiple instructions to be implemented. The plurality of instructions are associated through slots. For example, for
A＝100；
Two instructions are generated in luajit
KPRI 1，0；100
GSET 1，1，A
Simple translation into
Local slot1＝100
A＝slot1
Causing the decompiled source code to expand and the readability to drop rapidly. Considering the expression foo (a), it is decompiled into
local slot0＝foo；
local slot1＝a
slot0(slot1)
Such codes are extremely poorly readable. It is therefore desirable to merge instructions according to certain algorithms to reduce unnecessary local variables.
In the preferred embodiment, it is determined whether an instruction should ultimately generate a local variable according to the following criteria:
1) The slot written inside the CFG node, which is not used by any instruction in the current node, should generate a local variable the last instruction to write the slot.
2) The slot node written in the CFG node is used by any other instruction in the current node, the instruction in any other node is not assigned before being used, and the last instruction written in the slot node should generate a local variable.
3) Slots are assigned as nil/true/false/string/number and the like, and when a function call instruction (call/call) is performed, a table operation instruction (tgets/tsets and the like) is executed, a local variable is generated corresponding to the assignment instruction.
If the compilation time has a-g parameter, the following method is adopted:
the Lua bytecode file can analyze the local variable information. The symbol information carries the living range of the local variable. As shown in the following figure, instruction 0003kshort should generate a local variable, which is finally decompiled to local cccc=1
Step 3, CFG correction;
in lua, the logic condition does not allow for a valuation operation (the valuation operation within the function definition is not considered). In addition to the comparison instruction (LSLT/ISEQ/ISF/IST, etc.) and the last jump instruction of the node, other instructions must be written into one slot to access any slot, otherwise, an instruction which does not meet the requirement appears in the node, and the node should be divided into two nodes.
Further, in step 2, if the instruction is marked to generate a local variable and the instruction is not the last instruction of a node, the node should be divided into two nodes.
Step 4, analyzing the composite condition;
after the CFG is obtained, CFG nodes can be combined through an iterative algorithm, and an and/or/not connection relation among the nodes is obtained.
a) And sequentially analyzing the nodes of the CFG, if the node is the node, if the node a jumps to the node b when the condition is met, and no other nodes jump to the node b, and if the condition is not met, both the node a and the node b jump to the same node C, and the node a and the node b are combined by adopting and, wherein the combined node points to the node C at the edge of which the condition is not met.
b) And sequentially analyzing the nodes of the CFG, if the node is the node, if the node a jumps to the node b when the condition is not met, and no other nodes jump to the node b, and when the condition is met, both the node a and the node b jump to the same node C, combining the node a and the node b by adopting or, and pointing the combined node to the node C at the edge of the condition which is not met.
c) If the node has two outgoing edges, and the conditions of a) and b) are not satisfied, one equivalent transformation is completed. The equivalent transformation process is that the node performs a non operation, and whether the condition attribute of the two sides is interchanged or not. And then re-executing step a) and step b).
If none of the conditions of steps a), b), c) is met, the algorithm is stopped, otherwise the first three steps are repeated.
The process of recovering a and b or c from the assembler instruction is described below by taking if a and b or c then as an example. As shown in fig. 4, the assembly instruction resumes the process of a and b or c.
Step 5, logic instruction analysis, namely If/elseif/else/repeat/while analysis;
elseif conditions can be equivalently split into else and a nested if. For example
if a then
elseif b then
end
Can be equivalently expressed as
if a then
else
if b then
end
end
Meanwhile, else is an unconditional expression, while and repeat can be identified by the LOOP instruction. In addition to while, repeat, other conditional jump instructions may be considered if. If the merged node is an if condition and the node jump target is a non-jump instruction, the previous instruction of the target instruction is an unconditional jump instruction, then the unconditional jump instruction may be confirmed to be else.
For non-nested if/else, its end position corresponds to the jump target, and for nested if/else/while/repeat, the end position needs to be corrected.
It is noted that special handling is required if the if condition is constant true or constant false. For example if true then, the corresponding instruction is two consecutive JMPs.
Step 6, jump instruction analysis, i.e. break/goto analysis.
Through the analysis of step 5, there may also be some jump instructions without conditions. If the jump instruction loops across a layer, it may be determined to be break, otherwise it is translated to goto.
Through the above preferred embodiments, the following beneficial effects are provided: 1) The testing department can be independent of the research and development department, and the code quality risk of the software can be estimated; 2) The test department can be assisted to analyze code change, and the difference test can be accurately realized; 3) The white box test can be realized by the test department.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.
According to another aspect of the embodiment of the present invention, there is also provided a compiling apparatus for a code for implementing the compiling method of a code as described above. As shown in fig. 5, the compiling apparatus for the code includes: an acquisition unit 51, an assembly unit 53 and a decompilation unit 55. The details are as follows.
The obtaining unit 51 is configured to obtain a bytecode file obtained by compiling a first source code file of the target application.
And the assembling unit 53 is used for performing disassembling operation on the byte code file to obtain an assembly instruction text file.
The decompilation unit 55 is configured to decompil the assembly instruction text file to obtain a second source code file of the target application, where the assembly instruction text file includes: and determining the jump instruction and the jump relation between the instructions in the section of assembly instruction, and determining the grammar structure of the target code corresponding to the section of assembly instruction in the second source code file according to the jump instruction and the jump relation.
By the above apparatus, the acquiring unit 51 acquires a bytecode file obtained by compiling the first source code file of the target application; the assembling unit 53 performs disassembling operation on the byte code file to obtain an assembly instruction text file; decompilation unit 55 decompiles the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file includes: and determining the jump instruction and the jump relation between the instructions in the section of assembly instruction, and determining the grammar structure of the target code corresponding to the section of assembly instruction in the second source code file according to the jump instruction and the jump relation. Therefore, the technical effect of determining the target code prevention structure according to the jump instruction in the assembly instruction text file and the jump relation between the instructions is achieved, and the technical problem of singleness of a code decompiling mode in the prior art is solved.
As an alternative embodiment, the decompilation unit may include the following modules:
the first decompilation module is used for decompiling the first section of assembly instructions into first comparison operation assignment codes under the conditions that the last instruction of the first jump instruction in the first section of assembly instructions in the assembly instruction text file is a comparison instruction, the instruction jumped to by the first jump instruction is a first loading instruction, and the data value loaded by the first loading instruction is in a first preset range, wherein the first comparison operation assignment codes comprise one comparison operation.
Wherein, the first decompilation module may include: the first decompilation submodule is used for decompiling the first section of assembly instruction into a first comparison operation assignment code under the condition that the last instruction of the first jump instruction is a comparison instruction, the instruction to which the first jump instruction jumps is a first loading instruction, the value of data loaded by the first loading instruction is in a first preset range, the last instruction of the first loading instruction is a second jump instruction, the last instruction of the second jump instruction is a second loading instruction, and the value of data loaded by the second loading instruction is in a second preset range.
The second decompilation module is configured to decompil the second section of assembly instructions into a first logic operation assignment code when a last instruction of a third jump instruction in the second section of assembly instructions in the assembly instruction text file is a first register data determination instruction, a last instruction of the first register data determination instruction is a third load instruction, an instruction to which the third jump instruction jumps is a first return load instruction, and a next instruction of the third jump instruction is a fourth load instruction, where the first logic operation assignment code includes a logic operation.
And the third inverse compiling module is used for implementing inverse compiling of the third section of assembly instruction into a second logic operation assignment code under the condition that the last instruction of the fourth jump instruction in the third section of assembly instruction in the assembly instruction text file is a second register data judgment instruction, the last instruction of the second register data judgment instruction is a fifth loading instruction, the instruction to which the fourth jump instruction jumps is a second return loading instruction, the next instruction of the fourth jump instruction is a sixth loading instruction, the next instruction of the sixth loading instruction is a third register data judgment instruction, the next instruction of the third register data judgment instruction is a fifth jump instruction, and the next instruction of the fifth jump instruction is a seventh loading instruction, wherein the second logic operation assignment code comprises two logic operations.
As an alternative embodiment, the decompilation unit may further include: the building module is used for building a first directed graph according to the assembly instructions in the assembly instruction text file, wherein each node in the first directed graph represents one assembly instruction, the edge, which points to the second node, of the first node in the first directed graph represents the assembly instruction represented by the first node to jump to the assembly instruction represented by the second node, and the edge in the first directed graph has an attribute value for representing a jump condition; the merging module is used for carrying out merging operation on the nodes in the first directed graph to obtain a second directed graph, wherein the merging operation comprises at least one of the following steps: performing and merging on two nodes in the first directed graph, performing or merging on the two nodes in the first directed graph, and performing inverse equivalent transformation on the nodes in the first directed graph; and the determining module is used for determining codes comprising logic conditions in the second source code file according to the second directed graph.
As an alternative embodiment, the above-mentioned merging module may include the following submodules:
the first merging sub-module is used for jumping to the node b when the first jumping condition is met in the first directed graph, and jumping to the node b from other nodes, and carrying out and merging on the node a and the node b to obtain a first merging node under the condition that the node a and the node b jump to the same node c when the first jumping condition is not met, wherein the first merging node jumps to the node c when the first jumping condition is not met.
And the second merging submodule is used for carrying out or merging on the node a and the node b to obtain a second merging node when the second jump condition is not met in the first directed graph, and no other node jumps to the node b, and the node a and the node b jump to the same node c when the second jump condition is met, wherein the second merging node jumps to the node c when the second jump condition is not met.
The inverting sub-module is used for inverting the node a to obtain a first conversion node for replacing the node a when the third jumping condition is not met, the node a to the node b when the third jumping condition is met, and the node a to the node c when the third jumping condition is met and the node a and the node b cannot be combined and or combined, wherein the first conversion node to the node b when the third jumping condition is met and the first conversion node to the node c when the third jumping condition is not met.
And the repeated merging sub-module is used for repeatedly executing merging operation on the nodes in the first directed graph until a second directed graph is obtained, wherein the merging and merging or merging cannot be executed on any two nodes in the second directed graph, and the merging and merging or merging cannot be executed on any two nodes in a third directed graph obtained by carrying out the inverse equivalent transformation on any nodes in the second directed graph.
As an alternative embodiment, the determining module may include: and the decompilation sub-module is used for decompiling the unconditional jump instruction into an else code when the target instruction indicated by the third node corresponding to the if code in the second directed graph and the fourth node jumped by the third node is a non-jump instruction and the previous instruction of the target instruction is an unconditional jump instruction.
As an alternative embodiment, the assembly unit may further include: the generation module is used for generating a target assembly instruction in the assembly instruction text file, wherein the target assembly is used for encoding target numerical values in a target array in the byte code file into a character string with the number of i, changing the character string with the number of i into a target variable, and storing the target variable into a target register.
FIG. 6 is a schematic diagram of a compiling apparatus for a further code according to an embodiment of the invention, as shown in FIG. 6, the apparatus includes, in addition to: the acquisition unit 51 includes a detection unit 57 in addition to the decompilation unit 55 of the assembly unit 53.
The detecting unit 57 is configured to detect the second source code file of the target application after performing decompilation operation on the assembled text file to obtain the second source code file of the target application, so as to obtain a detection result, where the detection result is used to indicate whether the target application has a bug.
By the embodiment, whether the code of the target application has the loophole can be simply detected, and the code of the target application is modified under the condition that the code of the target application has the loophole, so that the normal operation of the target application is ensured.
According to a further aspect of the embodiments of the present invention there is also provided an electronic device for implementing the compiling method of a code as described above, as shown in fig. 7, the electronic device comprising a memory 702 and a processor 704, the memory 702 having stored therein a computer program, the processor 704 being arranged to perform the steps of any of the method embodiments described above by means of the computer program.
Alternatively, in this embodiment, the electronic apparatus may be located in at least one network device of a plurality of network devices of the computer network.
Alternatively, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, acquiring a byte code file obtained by compiling a first source code file of a target application;
s2, disassembling the byte code file to obtain an assembly instruction text file;
s3, decompiling the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises: and determining the jump instruction and the jump relation between the instructions in the section of assembly instruction, and determining the grammar structure of the target code corresponding to the section of assembly instruction in the second source code file according to the jump instruction and the jump relation.
Alternatively, it will be understood by those skilled in the art that the structure shown in fig. 6 is only schematic, and the electronic device may also be a terminal device such as a smart phone (e.g. an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, and a mobile internet device (Mobile Internet Devices, MID), a PAD, etc. Fig. 6 is not limited to the structure of the electronic device. For example, the electronic device may also include more or fewer components (e.g., network interfaces, etc.) than shown in FIG. 6, or have a different configuration than shown in FIG. 6.
The memory 702 may be used to store software programs and modules, such as program instructions/modules corresponding to the method and apparatus for compiling anti-code of bytecode in the embodiment of the present invention, and the processor 704 executes the software programs and modules stored in the memory 702 to perform various functional applications and data processing, that is, to implement the method for compiling anti-code of bytecode. The memory 702 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 702 may further include memory remotely located relative to the processor 704, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory 702 may be used for various directed graphs CFGs, various logic operation codes, disassembled files, decompiled files, and the like. As an example, as shown in fig. 7, the memory 702 may include, but is not limited to, the fetch unit 51, the assembly unit 53, the decompilation unit 55, and the detection unit 57 in the compiling apparatus including the decompilation of the bytecode. In addition, other module units in the compiling apparatus of the anti-code of the bytecode may be included, but are not limited to, and are not described in detail in this example.
Optionally, the transmission device 706 is used to receive or transmit data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 706 includes a network adapter (Network Interface Controller, NIC) that may be connected to other network devices and routers via a network cable to communicate with the internet or a local area network. In one example, the transmission device 706 is a Radio Frequency (RF) module that is configured to communicate wirelessly with the internet.
According to a further aspect of embodiments of the present invention, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
Alternatively, in the present embodiment, the above-described computer-readable storage medium may be configured to store a computer program for executing the steps of:
s1, acquiring a byte code file obtained by compiling a first source code file of a target application;
s2, disassembling the byte code file to obtain an assembly instruction text file;
S3, decompiling the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises: and determining the jump instruction and the jump relation between the instructions in the section of assembly instruction, and determining the grammar structure of the target code corresponding to the section of assembly instruction in the second source code file according to the jump instruction and the jump relation.
Alternatively, in this embodiment, it will be understood by those skilled in the art that all or part of the steps in the methods of the above embodiments may be performed by a program for instructing a terminal device to execute the steps, where the program may be stored in a computer readable storage medium, and the storage medium may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic or optical disk, and the like.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The integrated units in the above embodiments may be stored in the above-described computer-readable storage medium if implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present invention may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing one or more computer devices (which may be personal computers, servers or network devices, etc.) to perform all or part of the steps of the method described in the embodiments of the present invention.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
In several embodiments provided in the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, such as the division of the units, is merely a logical function division, and may be implemented in another manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (15)
1. A method of compiling code, comprising:
acquiring a byte code file obtained by compiling a first source code file of a target application, wherein the first source code file is a code file formed according to a dynamic type programming language;
performing disassembly operation on the byte code file to obtain an assembly instruction text file;
decompiling the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises: and determining the grammar structure of the target code corresponding to the one section of assembly instruction in the second source code file according to the jump instruction and the jump relation between the jump instruction and the instruction in the one section of assembly instruction.
2. The method of claim 1, wherein decompiling the assembler instruction text file comprises:
and decompiling the first section of assembly instruction into a first comparison operation assignment code under the conditions that the last instruction of a first jump instruction in the first section of assembly instruction in the assembly instruction text file is a comparison instruction, the instruction jumped to by the first jump instruction is a first loading instruction, and the data value loaded by the first loading instruction is in a first preset range, wherein the first comparison operation assignment code comprises one comparison operation.
3. The method of claim 2, wherein decompiling the first segment of assembly instructions into a first compare operation assignment code if a last instruction of a first jump instruction in the first segment of assembly instructions in the assembly instruction text file is a compare instruction, the instruction to which the first jump instruction jumps is a load instruction, the data value loaded by the load instruction is within a first predetermined range, comprising:
and decompiling the first section of assembly instruction into the first comparison operation assignment code under the conditions that the last instruction of the first jump instruction is a comparison instruction, the instruction to which the first jump instruction jumps is a first loading instruction, the data value loaded by the first loading instruction is in the first preset range, the last instruction of the first loading instruction is a second jump instruction, the last instruction of the second jump instruction is a second loading instruction, and the data value loaded by the second loading instruction is in the second preset range.
4. The method of claim 1, wherein decompiling the assembler instruction text file comprises:
and decompiling the second section assembly instruction into a first logic operation assignment code under the condition that the last instruction of a third jump instruction in the second section assembly instruction in the assembly instruction text file is a first register data judging instruction, the last instruction of the first register data judging instruction is a third loading instruction, the instruction to which the third jump instruction jumps is a first return loading instruction, and the next instruction of the third jump instruction is a fourth loading instruction, wherein the first logic operation assignment code comprises one logic operation.
5. The method of claim 1, wherein decompiling the assembler instruction text file comprises:
and decompiling the third section of assembly instruction into a second logic operation assignment code under the conditions that the last instruction of a fourth jump instruction in a third section of assembly instruction in the assembly instruction text file is a second register data judgment instruction, the last instruction of the second register data judgment instruction is a fifth loading instruction, the instruction jumped to by the fourth jump instruction is a second return loading instruction, the next instruction of the fourth jump instruction is a sixth loading instruction, the next instruction of the sixth loading instruction is a third register data judgment instruction, the next instruction of the third register data judgment instruction is a fifth jump instruction, the instruction jumped to by the fifth jump instruction is the second return loading instruction, and the next instruction of the fifth jump instruction is a seventh loading instruction, wherein the second logic operation assignment code comprises two logic operations.
6. The method of claim 1, wherein decompiling the assembler instruction text file comprises:
constructing a first directed graph according to the assembler instructions in the assembler instruction text file, wherein each node in the first directed graph represents one assembler instruction, the edge of the first directed graph, which points to a second node, represents the assembler instruction represented by the first node to jump to the assembler instruction represented by the second node, and the edge in the first directed graph has an attribute value for representing a jump condition;
and carrying out merging operation on the nodes in the first directed graph to obtain a second directed graph, wherein the merging operation comprises at least one of the following steps: performing and merging on two nodes in the first directed graph, performing or merging on the two nodes in the first directed graph, and performing inverse equivalent transformation on the nodes in the first directed graph;
and determining codes including logic conditions in the second source code file according to the second directed graph.
7. The method of claim 6, wherein the merging the nodes in the first directed graph to obtain a second directed graph comprises:
And when the first jump condition is met, jumping to a node b by the node a in the first directed graph, jumping to the node b by no other nodes, and jumping to the same node c by the node a and the node b when the first jump condition is not met, carrying out the and merging on the node a and the node b to obtain a first merging node, wherein the first merging node jumps to the node c when the first jump condition is not met.
8. The method of claim 6, wherein the merging the nodes in the first directed graph to obtain a second directed graph comprises:
and when the second jump condition is not met, jumping to the node b by the node a in the first directed graph, jumping to the same node c by the node a and the node b, and jumping to the node b by no other node, and under the condition that the node a and the node b jump to the same node c when the second jump condition is met, carrying out or merging on the node a and the node b to obtain a second merging node, wherein the second merging node jumps to the node c when the second jump condition is not met.
9. The method of claim 6, wherein the merging the nodes in the first directed graph to obtain a second directed graph comprises:
And when the third jump condition is not met, the node a jumps to the node b, the node a jumps to the node c when the third jump condition is met, and the and merging and or merging cannot be performed on the node a and the node b, the equivalent transformation for reversing the node a is performed, so that a first transformation node for replacing the node a is obtained, wherein the first transformation node jumps to the node b when the third jump condition is met, and the first transformation node jumps to the node c when the third jump condition is not met.
10. The method of claim 6, wherein the determining code in the second source code file that includes logic conditions from the second directed graph comprises:
and if the third node in the second directed graph corresponds to the if code, the target instruction indicated by the fourth node jumped by the third node is a non-jump instruction, and the previous instruction of the target instruction is an unconditional jump instruction, decompiling the unconditional jump instruction into an else code.
11. The method according to any one of claims 6 to 10, wherein the merging the nodes in the first directed graph to obtain a second directed graph includes:
And repeatedly executing the merging operation on the nodes in the first directed graph until the second directed graph is obtained, wherein the and merging and the or merging cannot be executed on any two nodes in the second directed graph, and the and merging and the or merging cannot be executed on any two nodes in a third directed graph obtained by performing the inverse equivalence transformation on any nodes in the second directed graph.
12. The method according to any one of claims 1 to 10, wherein disassembling the bytecode file to obtain an assembler instruction text file comprises:
and generating a target assembly instruction in the assembly instruction text file, wherein the target assembly is used for encoding target numerical values in a target array in the byte code file into a character string with the number of i, changing the character string with the number of i into a target variable, and storing the target variable into a target register.
13. The method according to any one of claims 1 to 10, wherein after said decompiling the assembler instruction text file to obtain a second source code file for the target application, the method further comprises:
And detecting the second source code file to obtain a detection result, wherein the detection result is used for indicating whether the target application has a vulnerability.
14. A compiling apparatus for codes, comprising:
the system comprises an acquisition unit, a storage unit and a storage unit, wherein the acquisition unit is used for acquiring a byte code file obtained by compiling a first source code file of a target application, and the first source code file is a code file formed according to a dynamic type programming language;
the assembly unit is used for performing disassembly operation on the byte code file to obtain an assembly instruction text file;
the decompilation unit is used for decompiling the assembly instruction text file to obtain a second source code file of the target application, wherein the assembly instruction text file comprises: and determining the grammar structure of the target code corresponding to the one section of assembly instruction in the second source code file according to the jump instruction and the jump relation between the jump instruction and the instruction in the one section of assembly instruction.
15. A computer readable storage medium comprising a stored program, wherein the program when run performs the method of any one of the preceding claims 1 to 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911061952.3A CN110825386B (en) | 2019-11-01 | 2019-11-01 | Code compiling method and device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911061952.3A CN110825386B (en) | 2019-11-01 | 2019-11-01 | Code compiling method and device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110825386A CN110825386A (en) | 2020-02-21 |
| CN110825386B true CN110825386B (en) | 2023-07-14 |
Family
ID=69552033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911061952.3A Active CN110825386B (en) | 2019-11-01 | 2019-11-01 | Code compiling method and device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110825386B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111475168B (en) * | 2020-04-14 | 2023-05-05 | 中国人民解放军战略支援部队信息工程大学 | A code compilation method and device |
| CN119356689A (en) * | 2020-09-21 | 2025-01-24 | 华为技术有限公司 | A code processing method, device and storage medium |
| CN112181834B (en) * | 2020-09-29 | 2022-02-25 | 苏州亿歌网络科技有限公司 | Method, device and equipment for debugging lua based on gdb and storage medium |
| CN113377433B (en) * | 2021-05-27 | 2023-03-21 | 北京北方华创微电子装备有限公司 | Method for executing semiconductor process |
| CN113672232B (en) * | 2021-07-09 | 2024-06-11 | 华为技术有限公司 | Program compiling method and device |
| CN114579094A (en) * | 2022-02-24 | 2022-06-03 | 成都北中网芯科技有限公司 | Dynamic language and assembly mixed compiling method |
| WO2025007327A1 (en) * | 2023-07-06 | 2025-01-09 | 华为技术有限公司 | Disassembly method and device |
| CN117971238A (en) * | 2024-01-31 | 2024-05-03 | 北京中科昊芯科技有限公司 | System and method for verifying instruction correlation in instruction set |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0818728A1 (en) * | 1996-06-11 | 1998-01-14 | Siemens Nixdorf Informationssysteme AG | Method of processing indexed jumps during code transformation |
| WO2001099034A2 (en) * | 2000-06-21 | 2001-12-27 | Aladdin Knowledge Systems; Ltd. | System for obfuscating computer code to prevent disassembly |
| CN101216775A (en) * | 2008-01-03 | 2008-07-09 | 北京深思洛克数据保护中心 | Software program protection method, device and system |
| US7661092B1 (en) * | 2008-12-30 | 2010-02-09 | International Business Machines Corporation | Intelligent reuse of local variables during bytecode compilation |
| WO2012056023A1 (en) * | 2010-10-28 | 2012-05-03 | Innowake Gmbh | Method and system for generating code |
| CN103235724A (en) * | 2013-05-10 | 2013-08-07 | 中国人民解放军信息工程大学 | Atomic operation semantic description based integrated translation method for multisource binary codes |
| CN103885770A (en) * | 2014-01-21 | 2014-06-25 | 唐道成 | Implementation method for retrieving assembly files from executable files for single chip microcomputer |
| CN104915211A (en) * | 2015-06-18 | 2015-09-16 | 西安交通大学 | Intrinsic function recognition method based on sub-graph isomorphism matching algorithm in decompilation |
| WO2017153815A1 (en) * | 2016-03-11 | 2017-09-14 | Lzlabs Gmbh | Load module compiler |
| CN107402799A (en) * | 2017-07-25 | 2017-11-28 | 北京计算机技术及应用研究所 | The method for performing TMS320C25 chip assembly instructions is explained in X86 computers ultrahigh speed |
| CN107526621A (en) * | 2017-08-07 | 2017-12-29 | 深圳芯邦科技股份有限公司 | A kind of external memory master control code Compilation Method and device |
| CN108345773A (en) * | 2017-07-27 | 2018-07-31 | 江苏通付盾信息安全技术有限公司 | Code protection method and device, electronic equipment, storage medium based on virtual machine |
| CN108614707A (en) * | 2018-04-27 | 2018-10-02 | 深圳市腾讯网络信息技术有限公司 | Static code inspection method, device, storage medium and computer equipment |
| CN110378107A (en) * | 2019-07-25 | 2019-10-25 | 腾讯科技（深圳）有限公司 | A kind of method and relevant apparatus of installation kit detection |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140143762A1 (en) * | 2012-11-21 | 2014-05-22 | Fujitsu Limited | Symbolic execution of dynamic programming languages |
| US9213563B2 (en) * | 2013-12-30 | 2015-12-15 | Unisys Corporation | Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation |
| US10303449B2 (en) * | 2017-07-31 | 2019-05-28 | Oracle International Corporation | Compiling non-native constants |
-
2019
- 2019-11-01 CN CN201911061952.3A patent/CN110825386B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0818728A1 (en) * | 1996-06-11 | 1998-01-14 | Siemens Nixdorf Informationssysteme AG | Method of processing indexed jumps during code transformation |
| WO2001099034A2 (en) * | 2000-06-21 | 2001-12-27 | Aladdin Knowledge Systems; Ltd. | System for obfuscating computer code to prevent disassembly |
| CN101216775A (en) * | 2008-01-03 | 2008-07-09 | 北京深思洛克数据保护中心 | Software program protection method, device and system |
| US7661092B1 (en) * | 2008-12-30 | 2010-02-09 | International Business Machines Corporation | Intelligent reuse of local variables during bytecode compilation |
| WO2012056023A1 (en) * | 2010-10-28 | 2012-05-03 | Innowake Gmbh | Method and system for generating code |
| CN103235724A (en) * | 2013-05-10 | 2013-08-07 | 中国人民解放军信息工程大学 | Atomic operation semantic description based integrated translation method for multisource binary codes |
| CN103885770A (en) * | 2014-01-21 | 2014-06-25 | 唐道成 | Implementation method for retrieving assembly files from executable files for single chip microcomputer |
| CN104915211A (en) * | 2015-06-18 | 2015-09-16 | 西安交通大学 | Intrinsic function recognition method based on sub-graph isomorphism matching algorithm in decompilation |
| WO2017153815A1 (en) * | 2016-03-11 | 2017-09-14 | Lzlabs Gmbh | Load module compiler |
| CN107402799A (en) * | 2017-07-25 | 2017-11-28 | 北京计算机技术及应用研究所 | The method for performing TMS320C25 chip assembly instructions is explained in X86 computers ultrahigh speed |
| CN108345773A (en) * | 2017-07-27 | 2018-07-31 | 江苏通付盾信息安全技术有限公司 | Code protection method and device, electronic equipment, storage medium based on virtual machine |
| CN107526621A (en) * | 2017-08-07 | 2017-12-29 | 深圳芯邦科技股份有限公司 | A kind of external memory master control code Compilation Method and device |
| CN108614707A (en) * | 2018-04-27 | 2018-10-02 | 深圳市腾讯网络信息技术有限公司 | Static code inspection method, device, storage medium and computer equipment |
| CN110378107A (en) * | 2019-07-25 | 2019-10-25 | 腾讯科技（深圳）有限公司 | A kind of method and relevant apparatus of installation kit detection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110825386A (en) | 2020-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110825386B (en) | Code compiling method and device and storage medium | |
| KR101418969B1 (en) | Processors and compilation methods | |
| CN108920496B (en) | Rendering method and device | |
| US20150378880A1 (en) | Dynamically Configurable Test Doubles For Software Testing And Validation | |
| CN108710787B (en) | Code obfuscation method and apparatus, computing device, computer storage medium | |
| US10248545B2 (en) | Method for tracking high-level source attribution of generated assembly language code | |
| CN110673837B (en) | Code repairing method and device, electronic equipment and computer readable storage medium | |
| US20160246622A1 (en) | Method and system for implementing invocation stubs for the application programming interfaces embedding with function overload resolution for dynamic computer programming languages | |
| CN112905447B (en) | Test method and system for block chain virtual machine | |
| CN118916886B (en) | RISC-V architecture-oriented binary program verification method and system | |
| CN113031967B (en) | Code conversion method and device | |
| CN106933642B (en) | Application program processing method and processing device | |
| Grimmer et al. | Supporting program analysis for non-mainstream languages: experiences and lessons learned | |
| CN107463421B (en) | Compiling and executing method and system of static flow model | |
| JP2013518352A (en) | Method and apparatus for enhancing understanding of time complexity and flow in code | |
| Heitman et al. | BARF: a multiplatform open source binary analysis and reverse engineering framework | |
| CN118069142B (en) | Compilation optimization method, device, electronic equipment and storage medium | |
| CN113448851A (en) | Automatic test method and system for RUST programming language compiler | |
| JP2008052688A (en) | Patch data generation device for program | |
| US9710360B2 (en) | Optimizing error parsing in an integrated development environment | |
| CN117806651A (en) | PLC software increment compiling method and device | |
| JP2009258796A (en) | Program development device and program development method | |
| CN113094664B (en) | System for preventing android application program from being decompiled | |
| Ellul et al. | Towards a unified programming model for blockchain smart contract DAPP systems | |
| CN118069143B (en) | Memory access processing method, device, electronic device and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 40021083 Country of ref document: HK |
|
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |