CN110824793B - Special-shaped display panel - Google Patents

Abstract

The present invention provides a display panel including a pixel array, a gate line, a first connecting line, a second connecting line and a common electrode. The first connection line and the second connection line are arranged in the edge region of the display panel. The first end of the first connection line is coupled to the corresponding gate line in the profiled region of the active region. The first ends of the second connection lines are coupled to corresponding gate lines in the non-profiled region of the active region of the display panel. The second end of each of the first connection line and the second connection line is coupled to the corresponding pin of the gate driver. The width of the first connection line is greater than the width of the second connection line to compensate for the difference in parasitic capacitance of these gate lines.

Description

Special-shaped display panel

technical field

The present invention relates to a display device, in particular to a special-shaped display panel.

Background technique

Generally, a display panel has an active area and an edge area. The active area has a pixel array (a plurality of pixel circuits), gate lines and source lines, while the edge area does not have any pixel circuits. These pixel circuits may be liquid crystal display (LCD) pixel circuits or other types of pixel circuits. In a general display panel, the common electrodes of these pixel circuits are arranged in the active region. Generally speaking, the shape of the display panel and the shape of the active area are both rectangular. Because the shape of the active region is rectangular, different gate lines (or source lines) have the same number of pixel circuits. That is, different gate lines (or source lines) have similar loads.

Some display devices may have an abnormity display panel (or shaped display panel). For example, the special-shaped display panel may be a notch display panel or other display panels. Compared with the non-profiled region (non-notch region) of the active region, there is a smaller number of pixel circuits in the profiled region (notch region) of the active region. That is, the load of the gate line in the profiled region (notch region) is different from that of the gate line within the non-profiled region (non-notch region). The load includes parasitic capacitance, parasitic resistance or other load elements. For example, the parasitic capacitance of the gate line in the gap region is smaller than the parasitic capacitance of the gate line in the non-gap region. The difference in parasitic capacitance between the gate lines in the profiled region and the gate lines in the non-profiled region may cause poor gray scale.

SUMMARY OF THE INVENTION

The present invention provides a display panel that can compensate for the difference in parasitic capacitance between gate lines in a profiled region and gate lines in a non-profiled region.

Embodiments of the present invention provide a display panel. The display panel includes a pixel array, a plurality of gate lines, at least one first connection line, at least one second connection line, and a common electrode. The pixel array and the gate lines are arranged in the first region of the display panel. The first connection line and the second connection line are arranged in the second area of the display panel. The first end of each of the first connection lines is coupled to a corresponding gate line of the gate lines in the first subregion of the first region. The second end of each of the first connection lines is coupled to the corresponding pin of the gate driver. The first end of each of the second connection lines is coupled to a corresponding gate line of the gate lines in the second subregion of the first region. The second end of each of the second connecting lines is coupled to the corresponding pin of the gate driver. The common electrode includes a main portion and an extension portion, the main portion is disposed in the first region, and the extension portion extends to the second region. The width of the first connection line is greater than the width of the second connection line.

In an embodiment of the present invention, the above-mentioned gate lines of the first sub-region include a first gate line and a second gate line. The distance from the first gate line to the second sub-region is greater than the distance from the second gate line to the second sub-region. A width of a connection line of the at least one first connection line coupled to the first gate line is greater than a width of a connection line of the at least one first connection line coupled to the second gate line.

In an embodiment of the present invention, the above-mentioned gate lines of the first sub-region include a first gate line group and a second gate line group. The distance from the first gate line group to the second sub-region is greater than the distance from the second gate line group to the second sub-region. A plurality of connection lines in the at least one first connection line coupled to the first gate line group have a width greater than a plurality of connections in the at least one first connection line coupled to the second gate line group The width of the line.

In an embodiment of the present invention, the widths of each of the at least one first connection lines are equal to each other, and the widths of each of the at least one second connection lines are equal to each other.

In an embodiment of the present invention, the at least one first connection line is arranged in a detour in the second area.

In an embodiment of the present invention, the above-mentioned display panel further includes a first substrate and a second substrate. The pixel array and the gate line are arranged on the first substrate. The common electrode is disposed on the second substrate.

In an embodiment of the present invention, the at least one first connection line and the at least one second connection line are disposed on the first substrate.

In an embodiment of the present invention, the above-mentioned display panel further includes a liquid crystal layer. The liquid crystal layer is disposed between the first substrate and the second substrate.

In an embodiment of the present invention, the above-mentioned gate driver includes an integrated gate driver (IGD).

Embodiments of the present invention provide a display panel. The display panel includes a pixel array, a plurality of gate lines, at least one first connection line, at least one second connection line, and a common electrode. The pixel array and the gate lines are arranged in the first region of the display panel. The first connection line and the second connection line are arranged in the second area of the display panel. The first end of each of the first connection lines is coupled to a corresponding gate line of the gate lines in the first subregion of the first region. The second end of each of the first connection lines is coupled to the corresponding pin of the gate driver. The first end of each of the second connection lines is coupled to a corresponding gate line of the gate lines in the second subregion of the first region. The second end of each of the second connecting lines is coupled to the corresponding pin of the gate driver. The common electrode includes a main portion and an extension portion, the main portion is disposed in the first region, and the extension portion extends to the second region. Wherein, the first connecting line is arranged in the second area in a detour.

Based on the above, the common electrode of the display panel according to the embodiments of the present invention extends from the first region to the second region, so as to form a parasitic capacitance with the first connection line disposed in the second region. The parasitic capacitance of the first connection line may be used to compensate for the difference in parasitic capacitance of the gate line in the first sub-region and the gate line in the second sub-region.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1 illustrates a schematic diagram of a display panel;

FIG. 2A and FIG. 2B are partial enlarged schematic diagrams showing the special-shaped area shown in FIG. 1 according to an embodiment;

FIG. 3 is a schematic diagram showing an equivalent circuit of the gate line in the non-profiled region shown in FIG. 2A;

FIG. 4 is a schematic diagram showing an equivalent circuit of the gate line in the irregular region shown in FIG. 2A;

5A and 5B are partial enlarged schematic diagrams illustrating the irregular-shaped area shown in FIG. 1 according to an embodiment of the present invention.

Description of reference numbers:

100: Display panel

101: Notch

110: Active Zone

111: Alien Zone

112: Non-Alien Zones

120: Edge Zone

200: Gate driver

CL1, CL2, CL3, CL5, CL6, CL7: the first connection line

CL4, CL8: the second connecting line

GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8: gate lines

VCOM, VCOM1: common electrode

VCOM11: Extension

VCOM12: Main part

Detailed ways

The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or A connection means is indirectly connected to the second device. In addition, where possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts. Components/components/steps using the same reference numerals or using the same terminology in different embodiments may refer to related descriptions of each other.

FIG. 1 is a schematic diagram of a display panel 100 . The display panel 100 includes a first area and a second area. In this embodiment, the first area may be an active area 110 of the display panel 100 , and the second area may be an edge area 120 of the display panel 100 . The active region 110 has a pixel array (a plurality of pixel circuits, not shown), gate lines (not shown) and source lines (not shown). The pixel circuit may be a liquid crystal display (LCD) pixel circuit or other types of pixel circuits. According to design requirements, the pixel circuit may be an existing pixel circuit or other pixel circuits. This embodiment does not limit the layout structure of the pixel array, gate lines and source lines in the active region 110 .

The display panel 100 shown in FIG. 1 is an abnormity display panel (or shaped display panel). Since the display panel 100 has the notch 101, the display panel 100 may be referred to as a notch display panel. Based on the notch 101 of the display panel 100 , the active region 110 also has a notch, as shown in FIG. 1 . The active region 110 has a first sub-region and a second sub-region. For the convenience of description, the first sub-region may be a region with a notch in the active region 110 (referred to as a special-shaped region 111 ), and the second sub-region may be another region in the active region 110 (referred to as a special-shaped region 111 ). is the non-shaped area 112).

Compared with the non-shaped area (non-notch area) 112 of the active area 110 , the irregular-shaped area (notch area) 111 of the active area 110 has a smaller number of pixel circuits. That is, the load of the gate line (not shown) within the profiled region (notch region) 111 is different from that of the gate line (not shown) within the non-profiled region (non-notch region) 112 . The load includes parasitic capacitance, parasitic resistance or other load elements. For example, the parasitic capacitance of the gate lines in the profiled region 111 is smaller than the parasitic capacitance of the gate lines in the non-profiled region 112 . The difference in parasitic capacitance between the gate lines in the profiled region 111 and the gate lines in the non-profiled region 112 may cause poor gray scale.

FIG. 2A and FIG. 2B are partial enlarged schematic diagrams illustrating the special-shaped area 111 shown in FIG. 1 according to an embodiment. 2A and 2B illustrate enlarged views of the upper right corner of the display panel 100 shown in FIG. 1 . FIG. 2A shows a schematic layout of gate lines, connecting lines and pins of a gate driver, and FIG. 2B shows a schematic layout of a common electrode VCOM. Please refer to FIG. 2A and FIG. 2B . According to design requirements, in some embodiments, the common electrode VCOM may be stacked over the gate line. In other embodiments, the gate line may be stacked over the common electrode VCOM. A plurality of gate lines (eg, gate lines GL1 , GL2 , GL3 and GL4 shown in FIG. 2A ) are disposed in the active region 110 . The gate line GL1 , the gate line GL2 and the gate line GL3 are arranged in the hetero-shaped region 111 of the active region 110 , and the gate line GL4 is arranged in the non-shaped region 112 of the active region 110 .

At least one first connection line (eg, the first connection lines CL1 , CL2 and CL3 shown in FIG. 2A ) is disposed in the edge region 120 of the display panel 100 . The first end of the first connection line CL1 is coupled to a corresponding gate line (the gate line GL1 ) in the shaped region 111 of the active region 110 , and the second end of the first connection line CL1 is coupled to the gate driver A corresponding pin of 200. The first end of the first connection line CL2 is coupled to a corresponding gate line (the gate line GL2 ) in the shaped region 111 of the active region 110 , and the second end of the first connection line CL2 is coupled to the gate driver The other corresponding pin of 200. The first end of the first connection line CL3 is coupled to a corresponding gate line (the gate line GL3 ) in the profiled region 111 of the active region 110 , and the second end of the first connection line CL3 is coupled to the gate driver The other corresponding pin of 200.

At least one second connection line (eg, the second connection line CL4 shown in FIG. 2A ) is disposed in the edge region 120 of the display panel 100 . The first end of each of the at least one second connection line is coupled to a corresponding gate line of the non-profiled region 112 of the active region 110 , and the second end of each of the at least one second connection line is coupled to Connected to the corresponding pins of the gate driver 200 . For example, the first end of the second connection line CL4 is coupled to the gate line GL4 of the non-isolated region 112 of the active region 110 , and the second end of the second connection line CL4 is coupled to a corresponding one of the gate driver 200 pins, as shown in Figure 2A.

This embodiment does not limit the implementation of the gate driver 200 . For example, the gate driver 200 may be an existing gate driver or other gate driver circuits/devices. For another example, the gate driver 200 may include an integrated gate driver (IGD).

In the embodiment shown in FIGS. 2A and 2B , the pixel circuit (not shown) of the display panel 100 and the common electrode VCOM of the pixel circuit are disposed in the active region 110 . Compared to the non-profiled region (non-notch region) 112 of the active region 110 , the profiled region (notch region) 111 of the active region 110 has a smaller number of pixel circuits (not shown). That is, the load of the gate line (eg, gate line GL2 ) within the profiled region 111 is different from that of the gate line (eg, gate line GL4 ) within the non-profiled region 112 .

FIG. 3 is a schematic diagram illustrating an equivalent circuit of the gate line GL4 in the non-profiled region 112 shown in FIG. 2A . Please refer to FIG. 2A and FIG. 3 . The gate line GL4 includes a plurality of parasitic resistances. Other gate lines in the non-isolated region 112 shown in FIG. 2 can be deduced by referring to the related description of the gate line GL4 in FIG. 3 , and thus will not be repeated.

FIG. 4 is a schematic diagram illustrating an equivalent circuit of the gate line GL2 in the irregular region 111 shown in FIG. 2A . Please refer to FIG. 2A and FIG. 4 . The gate line GL2 includes a plurality of parasitic resistances. Based on the common electrode VCOM disposed in the active region 110 , there are multiple parasitic capacitances between the gate line GL2 and the common electrode VCOM. Other gate lines (eg, gate lines GL1 and GL3 ) in the hetero-shaped region 111 shown in FIG. 2A can be deduced with reference to the related description of the gate line GL2 in FIG.

Compared with the equivalent circuit of the gate line GL4 shown in FIG. 3 , the gate line GL2 shown in FIG. 4 has a smaller amount of parasitic capacitance (because the shaped region 111 has a notch). The difference in parasitic capacitance between the gate line GL2 in the profiled region 111 and the gate line GL4 in the non-profiled region 112 may cause poor gray scale.

FIGS. 5A and 5B are partial enlarged schematic views illustrating the irregular-shaped area 111 shown in FIG. 1 according to an embodiment of the present invention. 5A and 5B illustrate enlarged views of the upper right corner of the display panel 100 shown in FIG. 1 . FIG. 5A shows a schematic layout of gate lines, connecting lines and pins of a gate driver, and FIG. 5B shows a schematic layout of a common electrode VCOM1 . A plurality of gate lines (eg, gate lines GL5 , GL6 , GL7 and GL8 shown in FIG. 5A ) are disposed in the active region 110 . The gate line GL5 , the gate line GL6 and the gate line GL7 are arranged in the irregular-shaped region 111 of the active region 110 , and the gate line GL8 is arranged in the non-shaped region 112 of the active region 110 . The gate lines GL5 , GL6 , GL7 and GL8 shown in FIG. 5A can be deduced by referring to the related descriptions of the gate lines GL1 , GL2 , GL3 and GL4 shown in FIGS. 2A to 4 , and thus will not be repeated.

Please refer to FIG. 5A. At least one first connection line (eg, the first connection lines CL5 , CL6 and CL7 shown in FIG. 5A ) is disposed in the edge region 120 of the display panel 100 . The first end of the first connection line CL5 is coupled to a corresponding gate line (the gate line GL5 ) in the profiled region 111 of the active region 110 , and the second end of the first connection line CL5 is coupled to the gate driver A corresponding pin of 200. The first end of the first connection line CL6 is coupled to a corresponding gate line (the gate line GL6 ) in the shaped region 111 of the active region 110 , and the second end of the first connection line CL6 is coupled to the gate driver The other corresponding pin of 200. The first end of the first connection line CL7 is coupled to a corresponding gate line (the gate line GL7 ) in the profiled region 111 of the active region 110 , and the second end of the first connection line CL7 is coupled to the gate driver The other corresponding pin of 200.

At least one second connection line (eg, the second connection line CL8 shown in FIG. 5A ) is disposed in the edge region 120 of the display panel 100 . The first end of each of the at least one second connection line is coupled to a corresponding gate line of the non-profiled region 112 of the active region 110 , and the second end of each of the at least one second connection line is coupled to Connected to the corresponding pins of the gate driver 200 . For example, the first end of the second connection line CL8 is coupled to the gate line GL8 of the non-isolated region 112 of the active region 110 , and the second end of the second connection line CL8 is coupled to a corresponding one of the gate driver 200 pins, as shown in Figure 5A.

In the embodiment shown in FIGS. 5A and 5B , the common electrode VCOM1 includes a main portion VCOM12 and an extension portion VCOM11 . The main portion VCOM12 of the common electrode VCOM1 is disposed in the active region 110 . The extending portion VCOM11 of the common electrode VCOM1 extends to the edge region 120 (as shown in FIG. 5B ) to form parasitic capacitances with the first connection lines (eg, the first connection lines CL5 , CL6 and CL7 shown in FIG. 5A ). Please refer to FIG. 5A and FIG. 5B . According to design requirements, in some embodiments, the main portion VCOM12 of the common electrode VCOM1 may overlap the gate line, and the extension portion VCOM11 of the common electrode VCOM1 may overlap the connecting line. In other embodiments, the gate line may be stacked over the main portion VCOM12 of the common electrode VCOM1, and the connection line may be stacked over the extension portion VCOM11 of the common electrode VCOM1.

In the embodiment shown in FIG. 5A , the width of the first connection lines (eg, the first connection lines CL5 , CL6 and CL7 shown in FIG. 5A ) is larger than that of the second connection lines (eg, the second connection lines shown in FIG. 5A ) CL8) to compensate for the difference between the gate line of the shaped area 111 (eg, the gate line GL5, GL6 or GL7 shown in FIG. 5A ) and the gate line of the non-shaped area 112 (eg, the gate line GL8 shown in FIG. 5A ) Parasitic capacitance difference.

This embodiment does not limit the structure of the display panel shown in FIG. 5A . For example, the structure of the display panel shown in FIG. 5A may be an existing structure or other structures. For another example, the display panel shown in FIG. 5A includes a first substrate (not shown) and a second substrate (not shown). According to design requirements, a pixel array (not shown), a gate line (not shown), the first connection lines (such as the first connection lines CL5, CL6 and CL7 shown in FIG. 5A ) and the second connection lines (For example, the second connection line CL8 shown in FIG. 5A ) can be disposed on the first substrate, and the common electrode VCOM1 can be disposed on the second substrate. A liquid crystal layer (not shown) may be disposed between the first substrate and the second substrate.

In the embodiment shown in FIG. 5A , the first connection lines (eg, the first connection lines CL5 , CL6 and CL7 shown in FIG. 5A ) are detoured in the edge region 120 to increase the parasitic capacitance. In addition, the first connection line detoured in the edge region 120 can also be used to compensate for the gate lines (such as the gate lines GL5, GL5, GL6 or GL7 ) and a gate line (eg, gate line GL8 shown in FIG. 5A ) in the non-profiled region 112 of the active region 110 has a difference in parasitic resistance. Based on the compensation of the parasitic capacitance (parasitic resistance) formed by the first connection lines (such as the first connection lines CL5, CL6 and CL7 shown in FIG. 5A ), the gate lines of the shaped region 111 (such as the gate lines shown in FIG. 5A ) The load of GL5, GL6 or GL7) may be closer to the load of the gate line of the non-profiled region 112 (eg, gate line GL8 shown in FIG. 5A).

The line widths of the first connection lines (eg, the first connection lines CL5, CL6 and CL7 shown in FIG. 5A ) can be determined according to design requirements. For example, in some embodiments, the widths of each of the first connection lines are equal to each other, and the widths of each of the second connection lines are equal to each other.

In other embodiments, the line widths of the first connecting lines (eg, the first connecting lines CL5 , CL6 and CL7 shown in FIG. 5A ) may be determined according to the positions of the gate lines in the shaped region 111 . For example, because the distance from the gate line GL5 to the non-profiled region 112 is greater than the distance from the gate line GL6 to the non-profiled region 112, the width of the first connection line CL5 coupled to the gate line GL5 is greater than that coupled to the gate The width of the first connection line CL6 of the pole line GL6. Similarly, it can be inferred that the width of the first connection line CL6 coupled to the gate line GL6 is greater than the width of the first connection line CL7 coupled to the gate line GL7.

In still other embodiments, the gate lines (eg, the gate lines GL5 , GL6 and GL7 shown in FIG. 5A ) in the shaped region 111 may be divided into several groups. For example, the gate lines in the profiled region 111 can be divided into a first gate line group and a second gate line group, wherein the distance from the first gate line group to the non-profiled region 112 It is greater than the distance from the second gate line group to the non-isolated region 112 . The widths of the plurality of connection lines coupled to the first gate line group in the first connection lines (eg, the first connection lines CL5, CL6 and CL7 shown in FIG. 5A ) are larger than those of the first connection lines The width of the plurality of connecting lines coupled to the second gate line group.

To sum up, the common electrode VCOM1 of the display panel according to the embodiments of the present invention may extend from the active region 110 to the edge region 120 so as to be connected with the first connection line (eg, as shown in FIG. 5A ) disposed in the edge region 120 The first connection lines CL5, CL6 and CL7) form parasitic capacitances. The parasitic capacitance of the first connection line can be used to compensate for the parasitic capacitance difference between the gate line in the profiled region 111 and the gate line in the non-profiled region 112 .

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the invention shall be determined by the claims.

Claims (10)

1. A display panel, wherein the display panel comprises: a pixel array, configured in the first area of the display panel; a plurality of gate lines, disposed in the first region; At least one first connection line is arranged in a meandering manner in the second area of the display panel, wherein the first end of each of the at least one first connection line is coupled to the first sub-section in the first area a corresponding gate line of the plurality of gate lines in the region, the second end of each of the at least one first connection line is coupled to a corresponding pin of the gate driver; At least one second connection line, configured in the second region, wherein the first end of each of the at least one second connection line is coupled to the second sub-region of the first region a corresponding gate line of the plurality of gate lines, the second end of each of the at least one second connection line is coupled to a corresponding pin of the gate driver; and a common electrode, comprising a main portion and an extension portion, the main portion is disposed in the first region, the extension portion extends to the second region to form a parasitic capacitance with the at least one first connection line; Wherein the width of the at least one first connection line is greater than the width of the at least one second connection line. 2 . The display panel according to claim 1 , wherein the plurality of gate lines in the first sub-region comprises a first gate line and a second gate line, and the first gate line The distance to the second sub-region is greater than the distance from the second gate line to the second sub-region, and the at least one first connection line is coupled to the connection line of the first gate line. The width is greater than a width of a connection line coupled to the second gate line among the at least one first connection line. 3 . The display panel according to claim 1 , wherein the plurality of gate lines in the first sub-region comprises a first gate line group and a second gate line group, and the first gate line group The distance from a gate line group to the second sub-region is greater than the distance from the second gate line group to the second sub-region, and the at least one first connection line is coupled to the first connection line. The widths of the plurality of connection lines of a gate line group are greater than the widths of the plurality of connection lines of the at least one first connection line coupled to the second gate line group. 4 . The display panel of claim 1 , wherein widths of each of the at least one first connection line are equal to each other, and widths of each of the at least one second connection line are equal to each other. 5 . equal. 5 . The display panel according to claim 1 , wherein the at least one first connection line is disposed in the second region in a detour. 6 . 6. The display panel according to claim 1, wherein the display panel further comprises: a first substrate, wherein the pixel array and the plurality of gate lines are disposed on the first substrate; and A second substrate, wherein the common electrode is disposed on the second substrate. 7 . The display panel of claim 6 , wherein the at least one first connection line and the at least one second connection line are disposed on the first substrate. 8 . 8. The display panel according to claim 6, wherein the display panel further comprises: The liquid crystal layer is disposed between the first substrate and the second substrate. 9. The display panel of claim 1, wherein the gate driver comprises an integrated gate driver. 10. A display panel, wherein the display panel comprises: a pixel array, configured in the first area of the display panel; a plurality of gate lines, disposed in the first region; At least one first connection line, configured in the second area of the display panel, wherein the first end of each of the at least one first connection line is coupled to the first sub-area in the first area the corresponding gate lines of the plurality of gate lines, the second end of each of the at least one first connection line is coupled to the corresponding pin of the gate driver; At least one second connection line, configured in the second region, wherein the first end of each of the at least one second connection line is coupled to the second sub-region of the first region a corresponding gate line of the plurality of gate lines, the second end of each of the at least one second connection line is coupled to a corresponding pin of the gate driver; and a common electrode, comprising a main portion and an extension portion, the main portion is disposed in the first region, the extension portion extends to the second region to form a parasitic capacitance with the at least one first connection line; Wherein, the at least one first connecting line is arranged in the second region in a detour.

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