CN110798215A - Sex input signal buffer of micropower wireless communication chip - Google Patents
Sex input signal buffer of micropower wireless communication chip Download PDFInfo
- Publication number
- CN110798215A CN110798215A CN201911040928.1A CN201911040928A CN110798215A CN 110798215 A CN110798215 A CN 110798215A CN 201911040928 A CN201911040928 A CN 201911040928A CN 110798215 A CN110798215 A CN 110798215A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- switch
- input
- voltage
- nmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 title claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 116
- 238000005070 sampling Methods 0.000 claims abstract description 51
- 101710129178 Outer plastidial membrane protein porin Proteins 0.000 claims description 6
- 102100037820 Voltage-dependent anion-selective channel protein 1 Human genes 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000003321 amplification Effects 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005034 decoration Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a sex input signal buffer of a micropower wireless communication chip, which comprises an input drive circuit and a following holding circuit; the method is characterized in that: the input drive circuit is of a source electrode following structure, and the nonlinearity of the NMOS source electrode follower is reduced through a linearization enhancement technology; the follow-up hold circuit mainly switches among three phases of resetting a sampling capacitor, inputting follow-up and margin amplification. The invention discloses a linear input signal buffer of a micro-power wireless communication chip, which reduces the amplitude of the relative voltage between each port of an input tube of a main source follower changing along with the change of an input signal and the relative static voltage difference through a plurality of auxiliary source follower circuits, and improves the linearity of the main source follower under the condition of large signal input.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit technology, and more particularly, to an input driving circuit of a data converter circuit.
Background
Analog-to-digital converters are widely used in modern electronic systems as bridges for converting analog signals to digital signals. With the development of wireless communication and radar systems, analog-to-digital converters are required to have higher conversion rate, higher accuracy, higher input bandwidth, lower power consumption, higher integration level and lower cost by circuit systems.
Pipeline analog-to-digital converters can obtain a proper compromise between conversion rate and conversion precision. To reduce the power consumption of the circuit as much as possible, circuit designers combine a conventional sample-and-hold circuit with the first stage pipeline of a pipeline analog-to-digital converter and omit an on-chip input driver. For the sampling rate analog-to-digital converter commonly used at present, the modifications can effectively reduce the power consumption of the circuit. However, the sampling rate of the analog-to-digital converter in the current system is more and more required, and the switching pulse of the sampling switch is more and more interfered with the sampled signal. The linearity of the converter cannot be guaranteed by means of off-chip filters. Therefore, an on-chip input driving circuit must be added.
If a conventional unity gain negative feedback circuit is used as an input driver, the unity gain negative feedback circuit is substantially impossible to implement given power consumption requirements and large bandwidth input ranges. If the bipolar transistor is used as a main component of the input driver, the mask layer of the layout is increased, the integration level of the chip is reduced, and the cost is increased.
However, if a conventional unity gain negative feedback circuit is used as an input driver, the unity gain negative feedback circuit is substantially impossible to implement given power consumption requirements and large bandwidth input ranges. If the bipolar transistor is used as a main component of the input driver, the mask layer of the layout is increased, the integration level of the chip is reduced, and the cost is increased.
Disclosure of Invention
To solve the above-mentioned conventional drawbacks, the present invention provides a linear input signal buffer of a micro-power wireless communication chip, which can be integrated in a CMOS process and consumes lower power consumption than a conventional input driving circuit.
To achieve the above-mentioned objectives, the high linearity input signal buffer applied to the high speed analog-to-digital converter of the present invention adopts the following technical solutions:
a linear input signal buffer of a micro-power wireless communication chip comprises an input driving circuit and a following holding circuit, and is characterized in that: the input drive circuit is of a source electrode following structure, and the nonlinearity of the NMOS source electrode follower is reduced through a linearization enhancement technology; the follow-hold circuit is switched among three phases of resetting the sampling capacitor, inputting follow and margin amplifying.
The follow-hold circuit comprises an operational amplifier A0, a sampling capacitor C4, a feedback capacitor C5, a switch S7, a switch S8, a switch S9 and a switch S10; the negative plate of the sampling capacitor C4 is connected to the output terminal V3 of the input driving circuit through a switch S7, to the input common mode voltage VCM of the operational amplifier a0 through a switch S8, and to the voltage signal VDAC through a switch S9; the signal VDAC is a voltage signal output by the following and holding circuit through digital-to-analog conversion after the input signal is quantized at the sampling time point; the positive plate of the sampling capacitor C4 is connected to the negative terminal input of the operational amplifier A0, to the positive plate of the feedback capacitor C5, to the input common mode voltage VCM of the operational amplifier A0 through switch S10; the negative plate of the feedback capacitor C5 is connected with the output end of the operational amplifier A0; the positive terminal of the operational amplifier A0 inputs the voltage VCM.
The following and holding circuit is switched among three phases of resetting a sampling capacitor, inputting following and margin amplifying; the switch S7 operates at clock phase Φ 1; the switch S8 operates at a clock phase phirst; the switch S9 operates at clock phase Φ 2; the switches S10 and S11 operate at clock phase φ 1 x.
In order to reduce the influence of the residual charge of the sampling capacitor on the linearity of the sampling circuit, the following and holding circuit needs to reset the sampling capacitor before entering an input following phase; at the moment, the clock phases phi rst and phi 1x are both high levels; in the input following phase, the clock phases phi 1 and phi 1x are both high level, and the voltage at the two ends of the sampling capacitor C4 follows the input signal; in the margin amplifying phase, the clock phase phi 2 is high, the other clocks are low, and after the voltage of the sampling capacitor C4 is subtracted from the voltage signal VDAC, the rest capacitors are all transferred to the feedback capacitor C5.
The grid electrode of the NMOS tube M1 is connected to an input signal VIN, the drain terminal of the NMOS tube M1 is connected to a power supply voltage VDD, and the source terminal of the NMOS tube M1 is connected to a bias current source IB 1; the source end of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 through a capacitor C1, and is connected to the negative plate of a capacitor C3 through a switch S5; the negative plate of capacitor C3 is connected to signal VCM through switch S6; the positive plate of the capacitor C3 is connected to the source end of the NMOS tube M4; the node of the source end of the NMOS transistor M4 is V2, and is connected to a bias current source IB 2; the gate of the NMOS transistor M4 is connected to the bias voltage VB, and the drain is connected to the node V3 and the source of the NMOS transistor M3; the node V3 is the output node of the input drive circuit; the gate of the NMOS transistor M3 is connected to the input signal VIN, and its drain is connected to the source of the NMOS transistor, and the node is V2; the drain terminal of the NMOS transistor M2 is connected to the power supply voltage VDD, and the gate thereof is connected to the node V1 through the capacitor C1; the positive plate of the capacitor C2 is connected to the positive plate of the capacitor C1 through the switch S3 and to the bias voltage Vb1 through the switch S1; the negative plate of the capacitor C2 is connected to the negative plate of the capacitor C1 through the switch S4 and to the bias voltage Vb2 through the switch S2.
The NMOS transistor M3 is a main source follower transistor of the input drive circuit; the source electrode of the NMOS tube M3 is the output end of the input drive circuit, and the output node is V3; the input drive circuit reduces the nonlinearity of the output signal of the NMOS tube M3 through a plurality of auxiliary circuits; the auxiliary circuit comprises a source follower circuit consisting of an NMOS tube M1 and a bias current source IB1, a current buffer consisting of a capacitor C3, a switch S5, a switch S6 and an NMOS tube M4, and a source follower circuit consisting of an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a bias current source IB 2.
The gates of the NMOS transistor M1 and the NMOS transistor M3 are connected to the input end VIN; the source of the NMOS tube is a node V1 and is connected to a bias current source IB 1; the drain terminal of the NMOS tube M1 is connected to a power supply voltage VDD; the node V1 and the node V3 are both the follow voltage of the input signal, and the difference between the follow voltage and the input signal is the threshold voltage of an NMOS transistor.
The source end of the NMOS tube M4 is a low impedance point, and in the input following stage, the source end of the NMOS tube M4 is a virtual point; the switch S5 is closed, the switch S6 is opened, a current buffer consisting of the capacitor C3 and the NMOS tube M4 generates a current on the capacitor C3 which is approximately equal to the current on the sampling capacitor C4 in the input following stage; the NMOS tube M4 transfers the current on the capacitor C3 to the sampling capacitor C4, so that the variation of the channel current of the NMOS tube M3 is reduced; in the margin amplifying phase, the switch S5 is opened, the switch S6 is closed, and the capacitor C3 is reset; the voltage of the negative plate of the capacitor C3 at the moment is equal to the voltage of the negative plate of the sampling capacitor C4 in the reset phase; when the follow-hold circuit jumps from the reset phase to the input follow phase, the capacitor C3 and the sampling capacitor C4 have corresponding voltage jumps; the charge required by the jump of the negative plate voltage of the sampling capacitor C4 is provided by the NMOS tube M1, the capacitor C3 and the NMOS tube M4 of the signal path; this speeds up the voltage build-up of the sampling capacitor C4.
A source follower circuit consisting of an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a bias current source IB2 ensures that the voltage difference between a node V2 and an input signal VIN is constant; the switch S1, the switch S2, the switch S3, the switch S4, the capacitor C1 and the capacitor C2 form a switch capacitor network, and constant voltage difference between the grid voltage of the NMOS tube M2 and the input signal VIN is guaranteed.
The NMOS transistor M3 is a main source follower transistor of the input drive circuit; the voltage difference among the grid, the drain and the source of the NMOS transistor M3 does not change obviously due to the large swing fluctuation of the input VIN; the charge and discharge current of the sampling capacitor C4 at the input following phase is provided by an NMOS tube M1, a capacitor C3 and an NMOS tube M4; according to these characteristics, the nonlinearity of the NMOS transistor M3 under a large signal input condition can be reduced.
The invention adopting the technical scheme has the following beneficial effects:
the invention reduces the amplitude of the change of the relative voltage between the ports of the input tube of the main source follower along with the change of the input signal through a plurality of auxiliary source follower circuits. The relatively static voltage difference improves the linearity of the main source follower under the condition of large signal input.
Drawings
Fig. 1 is a diagram of a conventional negative feedback type unity gain input signal buffer.
Fig. 2 is a diagram of a conventional emitter follower type input signal buffer.
Fig. 3 is a high linearity input signal buffer according to the present invention.
FIG. 4 is a timing diagram illustrating the operation of the high linearity input signal buffer according to the present invention.
FIG. 5 is a simplified circuit diagram of the input buffer circuit of the present invention in the input follower state.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Fig. 1 is a conventional negative feedback type unity gain input signal buffer. The operational amplifier in the circuit has very high direct current gain, and can ensure small enough error voltage between input and output. The high gain characteristic of the operational amplifier reduces the nonlinearity of the NMOS transistor. The circuit can be used as an input signal buffer with high linearity. However, it is difficult to simultaneously realize high gain, high speed and low power consumption in the negative feedback connection mode of the operational amplifier.
Fig. 2 is a conventional emitter follower type input signal buffer. The circuit is an open-loop structure and can realize high-speed unit gain under low power consumption. Although the emitter follower circuit of the bipolar transistor has better linearity than the CMOS source follower circuit. However, the linearity required for high-speed and high-precision analog-to-digital converters is still not satisfied.
Fig. 3 is a high linearity input signal buffer provided in the linearity input signal buffer of the micro-power wireless communication chip according to the present invention. The circuit of fig. 3 is a source follower circuit, and the nonlinearity of the source follower circuit is reduced by a linearization enhancement technique. The NMOS transistor M3 in the figure is the main source follower transistor of the input driving circuit of the present invention. The source terminal of the NMOS transistor M3 is connected to the sampling capacitor C4 through the switch S7. And a source follower of the NMOS transistor M1, a capacitor C3 and a sub-circuit of the NMOS transistor M4 provide charging and discharging current for the sampling capacitor C4. And the NMOS transistor M2 is used as a source follower for reducing voltage fluctuation between the three ports of the NMOS transistor M3. These improvements are all intended to increase the linearity of the NMOS transistor M3 with time.
Fig. 4 is a switching timing of the main switches of the input driving circuit of the present invention. The time sequence is used for controlling the input drive circuit to circularly switch among three phases of resetting the sampling capacitor, input following and margin amplifying in sequence.
When the input driving circuit is in the reset sampling capacitor phase, the switches S8 and S10 in fig. 2 are in the closed state, and the other switches are in the open state. Both ports of the sampling capacitor C4 are controlled by a dc voltage signal. Although the negative plate of the capacitor C3 is at the floating state at this time, the capacitor C3 has been reset at the previous phase. Before the reset sampling capacitor phase is finished, the negative plate voltages of the capacitor C3 and the capacitor C4 are VCM.
When the circuit works in the input following stage, the switch S1, the switch S2, the switch S5, the switch S7 and the switch S10 are in the closed state, and other switches are in the open state. Fig. 5 is a simplified circuit of the circuit of fig. 2 in an input following phase. The capacitor C1 is a large-capacitance capacitor, and the voltage difference on the capacitor C1 is constant between Vb1 and Vb2 through periodic charge transfer of the switch S1, the switch S2, the switch S3, the switch S4 and the capacitor C2. The node V4 follows the input signal VIN through a two-stage source follower circuit composed of an NMOS transistor M1 and an NMOS transistor M2. The node V3 follows the input signal VIN through the source of the NMOS transistor M3. The three port voltages of the NMOS transistor M3 can be kept constant during the input variation.
Node V2 is connected to the source of NMOS transistor M4, and node V2 is a low impedance node. The voltage fluctuation amount of the node V2 is much smaller than that of the input signal VIN, and the node V2 can be regarded as a virtual point. Node V1 is driven by the source of NMOS transistor M1, and node V1 follows the input VIN. Since the capacitor C3 is connected between the node V1 and the node V2, the current of the capacitor C3 can only flow into the node V3 through the NMOS transistor M4. The capacitance value of the sampling capacitor C4 is equal to that of the capacitor C3, and the magnitude and direction of the current flowing into the negative plate of the capacitor C4 are the same as those of the current flowing into the negative plate of the capacitor C3.
The current path formed by the NMOS transistor M1, the capacitor C3 and the NMOS transistor M4 reduces the variation of the channel current of the NMOS transistor M3. The voltage signal path formed by the capacitor C1 and the NMOS transistor M2 reduces voltage fluctuation among three ports of the NMOS transistor M3. The invention mainly reduces the nonlinearity of the source output of the NMOS tube M3 through the two linearity enhancement technologies.
The NMOS transistor M1 and the NMOS transistor M3 are in the same proportion with the bias current source IB1 and the bias current source IB 2. The dc levels at node V1 and node V3 are equal, while the ac voltage signals are approximately equal. When the input drive circuit is switched to the input following phase from the reset sampling capacitor, the voltages of the negative plates of the capacitor C3 and the capacitor C4 jump from the voltage value VCM to the voltage value VIN-VGS 1. The charge required for the capacitor C4 to jump from the reset state to the follow state is provided by a current path formed by the NMOS transistor M1, the capacitor C3 and the NMOS transistor M4. This increases the speed of the sampling capacitor C4, increasing the maximum allowable sampling rate of the input drive circuit.
In the margin amplification phase, the switches S5 and S7 are in the off state. The input drive circuit is in a no-load state. Switch S6 is closed and capacitor C3 is reset. The input drive circuit waits to enter the reset sampling capacitor phase.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A linear input signal buffer of a micro-power wireless communication chip comprises an input driving circuit and a following holding circuit, and is characterized in that: the input driving circuit is of a source electrode following structure, and nonlinearity of the NMOS source electrode follower is reduced through linearization enhancement; the follow-hold circuit is switched among three phases of resetting the sampling capacitor, inputting follow and margin amplifying.
2. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 1, wherein: the follow-hold circuit comprises an operational amplifier A0, a sampling capacitor C4, a feedback capacitor C5, a switch S7, a switch S8, a switch S9 and a switch S10; the negative plate of the sampling capacitor C4 is connected to the output terminal V3 of the input driving circuit through a switch S7, to the input common mode voltage VCM of the operational amplifier a0 through a switch S8, and to the voltage signal VDAC through a switch S9; the signal VDAC is a voltage signal output by the following and holding circuit through digital-to-analog conversion after the input signal is quantized at the sampling time point; the positive plate of the sampling capacitor C4 is connected to the negative terminal input of the operational amplifier A0, to the positive plate of the feedback capacitor C5, to the input common mode voltage VCM of the operational amplifier A0 through switch S10; the negative plate of the feedback capacitor C5 is connected with the output end of the operational amplifier A0; the positive terminal of the operational amplifier A0 inputs the voltage VCM.
3. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 2, wherein: the following and holding circuit is switched among three phases of resetting a sampling capacitor, inputting following and margin amplifying; the switch S7 operates at clock phase Φ 1; the switch S8 operates at a clock phase phirst; the switch S9 operates at clock phase Φ 2; the switches S10 and S11 operate at clock phase φ 1 x.
4. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 3, wherein: in order to reduce the influence of the residual charge of the sampling capacitor on the linearity of the sampling circuit, the following and holding circuit needs to reset the sampling capacitor before entering an input following phase; at the moment, the clock phases phi rst and phi 1x are both high levels; in the input following phase, the clock phases phi 1 and phi 1x are both high level, and the voltage at the two ends of the sampling capacitor C4 follows the input signal; in the margin amplifying phase, the clock phase phi 2 is high, the other clocks are low, and after the voltage of the sampling capacitor C4 is subtracted from the voltage signal VDAC, the rest capacitors are all transferred to the feedback capacitor C5.
5. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 1, wherein: the grid electrode of the NMOS tube M1 is connected to an input signal VIN, the drain terminal of the NMOS tube M1 is connected to a power supply voltage VDD, and the source terminal of the NMOS tube M1 is connected to a bias current source IB 1; the source end of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 through a capacitor C1, and is connected to the negative plate of a capacitor C3 through a switch S5; the negative plate of capacitor C3 is connected to signal VCM through switch S6; the positive plate of the capacitor C3 is connected to the source end of the NMOS tube M4; the node of the source end of the NMOS transistor M4 is V2, and is connected to a bias current source IB 2; the gate of the NMOS transistor M4 is connected to the bias voltage VB, and the drain is connected to the node V3 and the source of the NMOS transistor M3; the node V3 is the output node of the input drive circuit; the gate of the NMOS transistor M3 is connected to the input signal VIN, and its drain is connected to the source of the NMOS transistor, and the node is V2; the drain terminal of the NMOS transistor M2 is connected to the power supply voltage VDD, and the gate thereof is connected to the node V1 through the capacitor C1; the positive plate of the capacitor C2 is connected to the positive plate of the capacitor C1 through the switch S3 and to the bias voltage Vb1 through the switch S1; the negative plate of the capacitor C2 is connected to the negative plate of the capacitor C1 through the switch S4 and to the bias voltage Vb2 through the switch S2.
6. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 5, wherein: the NMOS transistor M3 is a main source follower transistor of the input drive circuit; the source electrode of the NMOS tube M3 is the output end of the input drive circuit, and the output node is V3; the input drive circuit reduces the nonlinearity of the output signal of the NMOS tube M3 through a plurality of auxiliary circuits; the auxiliary circuit comprises a source follower circuit consisting of an NMOS tube M1 and a bias current source IB1, a current buffer consisting of a capacitor C3, a switch S5, a switch S6 and an NMOS tube M4, and a source follower circuit consisting of an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a bias current source IB 2.
7. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 5, wherein: the gates of the NMOS transistor M1 and the NMOS transistor M3 are connected to the input end VIN; the source of the NMOS tube is a node V1 and is connected to a bias current source IB 1; the drain terminal of the NMOS tube M1 is connected to a power supply voltage VDD; the node V1 and the node V3 are both the follow voltage of the input signal, and the difference between the follow voltage and the input signal is the threshold voltage of an NMOS transistor.
8. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 5, wherein: the source end of the NMOS tube M4 is a low impedance point, and in the input following stage, the source end of the NMOS tube M4 is a virtual point; the switch S5 is closed, the switch S6 is opened, a current buffer consisting of the capacitor C3 and the NMOS tube M4 generates a current on the capacitor C3 which is approximately equal to the current on the sampling capacitor C4 in the input following stage; the NMOS tube M4 transfers the current on the capacitor C3 to the sampling capacitor C4, so that the variation of the channel current of the NMOS tube M3 is reduced; in the margin amplifying phase, the switch S5 is opened, the switch S6 is closed, and the capacitor C3 is reset; the voltage of the negative plate of the capacitor C3 at the moment is equal to the voltage of the negative plate of the sampling capacitor C4 in the reset phase; when the follow-hold circuit jumps from the reset phase to the input follow phase, the capacitor C3 and the sampling capacitor C4 have corresponding voltage jumps; the charge required by the jump of the negative plate voltage of the sampling capacitor C4 is provided by the NMOS tube M1, the capacitor C3 and the NMOS tube M4 of the signal path; this speeds up the voltage build-up of the sampling capacitor C4.
9. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 5, wherein: a source follower circuit consisting of an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a bias current source IB2 ensures that the voltage difference between a node V2 and an input signal VIN is constant; the switch S1, the switch S2, the switch S3, the switch S4, the capacitor C1 and the capacitor C2 form a switch capacitor network, and constant voltage difference between the grid voltage of the NMOS tube M2 and the input signal VIN is guaranteed.
10. The linear input signal buffer applied to the micro-power wireless communication chip according to claim 5, wherein: the NMOS transistor M3 is a main source follower transistor of the input drive circuit; the voltage difference among the grid, the drain and the source of the NMOS transistor M3 does not change obviously due to the large swing fluctuation of the input VIN; the charge and discharge current of the sampling capacitor C4 in the input following phase is provided by an NMOS tube M1, a capacitor C3 and an NMOS tube M4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911040928.1A CN110798215A (en) | 2019-10-30 | 2019-10-30 | Sex input signal buffer of micropower wireless communication chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911040928.1A CN110798215A (en) | 2019-10-30 | 2019-10-30 | Sex input signal buffer of micropower wireless communication chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110798215A true CN110798215A (en) | 2020-02-14 |
Family
ID=69441923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911040928.1A Pending CN110798215A (en) | 2019-10-30 | 2019-10-30 | Sex input signal buffer of micropower wireless communication chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110798215A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105071806A (en) * | 2015-08-28 | 2015-11-18 | 西安启微迭仪半导体科技有限公司 | High-linearity input signal buffer applied to high-speed analog-digital converter |
-
2019
- 2019-10-30 CN CN201911040928.1A patent/CN110798215A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105071806A (en) * | 2015-08-28 | 2015-11-18 | 西安启微迭仪半导体科技有限公司 | High-linearity input signal buffer applied to high-speed analog-digital converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101277112B (en) | Low-power consumption assembly line a/d converter by sharing operation amplifier | |
| KR100590464B1 (en) | Sampling switch | |
| US8441382B2 (en) | Current steering DAC with switched cascode output current source/sink | |
| CN101860335B (en) | Double-input operational amplifier shared margin gain amplifying circuit | |
| US8610422B2 (en) | Dynamic biasing of an amplifier using capacitive driving of internal bias voltages | |
| CN101692603B (en) | Gain bootstrap type C class reverser and application circuit thereof | |
| CN108777579B (en) | Gate voltage bootstrap switch | |
| CN112953503B (en) | High-linearity grid voltage bootstrap switch circuit | |
| KR20140035958A (en) | Distributed bootstrap switch | |
| US7564273B2 (en) | Low-voltage comparator-based switched-capacitor networks | |
| CN105071806B (en) | High linearity buffer input signal device applied to high-speed AD converter | |
| CN111245413A (en) | High-speed high-linearity grid voltage bootstrap switch circuit | |
| WO2020042436A1 (en) | Buffer circuit and buffer | |
| US6970038B2 (en) | Switching scheme to improve linearity and noise in switched capacitor stage with switched feedback capacitor | |
| CN113630121A (en) | Sampling holding and knee point detection circuit | |
| CN115694491A (en) | Global Offset Calibration Method and Circuit for Array Level Dynamic Comparator | |
| US7071778B2 (en) | High-speed low-power dynamic current biased operational amplifier | |
| CN111970004A (en) | Bootstrap switch structure without influencing service life of device | |
| CN103279162B (en) | Low-power-consumption reference voltage buffer based on assembly line ADC | |
| CN113452371B (en) | Successive approximation register analog-to-digital converter and related control method | |
| CN204967796U (en) | Be applied to high -speed adc's high linearity incoming signal buffer | |
| CN113098455B (en) | High-speed bootstrap switch with low on-resistance | |
| CN110798215A (en) | Sex input signal buffer of micropower wireless communication chip | |
| CN103023508B (en) | A current-steering digital-to-analog converter current source unit circuit | |
| Cho | A 2.24-mW, 61.8-dB SNDR, 20-MS/s pipelined ADC with charge-pump-based dynamic biasing for power reduction in op amp sharing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200214 |
|
| WD01 | Invention patent application deemed withdrawn after publication |