CN110797937A - BMS charge and discharge management circuit - Google Patents
BMS charge and discharge management circuit Download PDFInfo
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- CN110797937A CN110797937A CN201910989626.2A CN201910989626A CN110797937A CN 110797937 A CN110797937 A CN 110797937A CN 201910989626 A CN201910989626 A CN 201910989626A CN 110797937 A CN110797937 A CN 110797937A
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- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 230000003287 optical effect Effects 0.000 claims abstract description 10
- 238000007599 discharging Methods 0.000 claims description 38
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 6
- 229910052744 lithium Inorganic materials 0.000 description 6
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
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Abstract
The invention discloses a BMS charge and discharge management circuit which comprises a resistor R68, a resistor R71, a resistor R74, a resistor R77, a resistor R84, a resistor R87, a resistor R90, a resistor R93, a triode Q10, a diode D22, a diode D5, a diode D6, an optical coupler OC2, a discharge MOS circuit, a charge MOS circuit, a capacitor C29 and a capacitor C30. The invention has the beneficial effects that: this circuit can realize control and management to charge-discharge current on the BMS main control board, and the circuit control end has adopted opto-coupler isolation formula control mode, has protected the little voltage circuit of front level, and the MOS switch both ends are battery ground and charger ground, because the disconnection and the closure in ground return circuit only, so even MOS burns the short circuit under the abnormal conditions, also can not produce and strike sparks.
Description
Technical Field
The invention relates to the technical field of charging and discharging management, in particular to a BMS charging and discharging management circuit.
Background
Due to the rapid development of power lithium batteries in recent years, the rapid development of power lithium batteries has a great breakthrough in both production process and material technology improvement or price advantage, and therefore, the rapid development of power lithium batteries lays a solid foundation for multiple series and multiple strings. The era of replacing lead-acid batteries is more and more recent. The market occupation rate of electric bicycles and backup power supplies is naturally also beginning to be greatly expanded, which is a non-repudiatable fact. Compared with lead-acid batteries, the safety of charging and discharging of lithium batteries is a big disadvantage. Phenomena such as overcharge explosion, over-discharge, fire and the like of the lithium battery are often seen in the market. Therefore, for the safety and the service life of the battery, the charge and discharge management of the lithium battery is naturally insufficient, and at the moment, the charge and discharge management of the battery is also a very core technology.
General BMS charge and discharge control circuit begins and ends discharging, can produce surge pulse current when charging and ends, can burn out preceding stage's MOS or triode because the protection is not in time many times, sometimes burns one piece at a time just, and the investigation is also difficult. If any one is missed, the missed block is sent to a client, so that a potential safety hazard is caused. In addition, people who have studied the electric vehicle controller know that if the protection of the controller is not good or the MOS is short-circuited under abnormal conditions, the positive and negative electrodes of the battery at the two ends of the MOS are directly short-circuited under the condition of Hall voltage, and then the MOS is burned by quickly firing, so that fire disasters can be caused if the MOS is serious, and the electric vehicle controller is very afraid.
An effective solution to the problems in the related art has not been proposed yet.
Disclosure of Invention
In order to solve the problems in the related art, the present invention provides a BMS charging and discharging management circuit, which employs a MOS having one terminal connected to a battery ground and one terminal connected to a charger ground. The positive end of the battery and the positive end of the charger are connected outside the board, namely, the charging and discharging control of the battery is realized by controlling the on-off of two grounds, and the battery charger is safe and reliable so as to overcome the technical problems in the prior art.
Therefore, the invention adopts the following specific technical scheme:
a BMS charge and discharge management circuit comprises a resistor R68, a resistor R71, a resistor R74, a resistor R77, a resistor R84, a resistor R87, a resistor R90, a resistor R93, a triode Q10, a diode D22, a diode D5, a diode D6, an optical coupler OC2, a discharge MOS circuit, a charge MOS circuit, a capacitor C29 and a capacitor C30;
one end of the resistor R74 is connected with a DSG-EN pin of a single chip microcomputer, the other end of the resistor R74 is sequentially connected with one end of the resistor R77 and a base of the triode Q10, the other end of the resistor R77 is grounded, an emitter of the triode Q10 is grounded, a collector of the triode Q10 is connected with a first input end of the optocoupler OC2 through the resistor R68, a second input end of the optocoupler OC2 is connected with +5V voltage, a first output end of the optocoupler OC2 is connected with an anode of the diode D22 through the resistor R71, a second output end of the optocoupler OC2 is connected with +12V voltage, and a cathode of the diode D22 is sequentially connected with the discharging MOS circuit and the charging MOS circuit;
one end of the discharge MOS circuit far away from the charge MOS circuit is connected with one end of the resistor R84, one end of the resistor R87, one end of the resistor R90 and one end of the resistor R93 in sequence, the other end of the resistor R84, the other end of the resistor R87, the other end of the resistor R90 and the other end of the resistor R93 are respectively connected with a battery negative BAT-in turn, one end of the discharge MOS circuit close to the charge MOS circuit is connected with the anode of the diode D5 and one end of the capacitor C30 in turn, one end of the charging MOS circuit close to the discharging MOS circuit is sequentially connected with the anode of the diode D6 and one end of the capacitor C29, the cathode of the diode D5 is connected with the cathode of the diode D6, the other end of the capacitor C29 is connected with the other end of the capacitor C30, and one end of the charging MOS circuit, which is far away from the discharging MOS circuit, is connected with the ground P-of the charger.
Further, the discharge MOS circuit includes a MOS transistor Q13, a MOS transistor Q15, a MOS transistor Q17, a MOS transistor Q19, a resistor R81, a resistor R82, a resistor R85, a resistor R88, a resistor R92, a resistor R94, a resistor R96, and a resistor R98.
Furthermore, one end of the resistor R81 is sequentially connected to the negative electrode of the diode D22, one end of the resistor R85, one end of the resistor R92 and one end of the resistor R96, the other end of the resistor R81 is sequentially connected to one end of the resistor R82 and the gate of the MOS transistor Q13, the source of the MOS transistor Q13 is sequentially connected to the other end of the resistor R82 and one end of the resistor R84, the drain of the MOS transistor Q13 is sequentially connected to the charging MOS circuit and the drain of the MOS transistor Q19, the other end of the resistor R85 is sequentially connected to one end of the resistor R88 and the gate of the MOS transistor Q15, the source of the MOS transistor Q13 is sequentially connected to the other end of the resistor R88 and one end of the resistor R84, the drain of the MOS transistor Q15 is connected to the charging circuit, the other end of the resistor R92 is sequentially connected to one end of the resistor R94 and one end of the gate of the MOS transistor Q17, the source of MOS pipe Q17 in proper order with the other end of resistance R94 and the one end of resistance R84 is connected, MOS pipe Q17 the drain-source resistance with the MOS circuit connection that charges, the other end of resistance R96 in proper order with the one end of resistance R98 and the grid of MOS pipe Q19 is connected, MOS pipe Q19 the source in proper order with the other end of resistance R98 and the one end of resistance R84 is connected, just MOS pipe Q19 the source in proper order with diode D5's positive pole and the one end of electric capacity C30 is connected.
Further, the charging MOS circuit includes a MOS transistor Q14, a MOS transistor Q16, a MOS transistor Q18, a MOS transistor Q20, a resistor R79, a resistor R83, a resistor R86, a resistor R89, a resistor R91, a resistor R95, a resistor R97, and a resistor R99.
Furthermore, one end of the resistor R79 is sequentially connected to the negative electrode of the diode D22, one end of the resistor R86, one end of the resistor R91 and one end of the resistor R97, the other end of the resistor R79 is sequentially connected to one end of the resistor R83 and the gate of the MOS transistor Q14, the source of the MOS transistor Q14 is sequentially connected to the other end of the resistor R83 and the ground P-of the charger, the drain of the MOS transistor Q14 is connected to the drain of the MOS transistor Q13, the other end of the resistor R86 is sequentially connected to one end of the resistor R89 and the gate of the MOS transistor Q16, the source of the MOS transistor Q16 is sequentially connected to the other end of the resistor R89 and the ground P-of the charger, the drain of the MOS transistor Q16 is connected to the drain of the MOS transistor Q15, the other end of the resistor 539r 91 is sequentially connected to one end of the resistor R95 and the gate of the transistor Q67 18, the source of MOS pipe Q18 in proper order with the other end of resistance R95 and the ground P-connection of charger, the drain-source resistance of MOS pipe Q18 with the drain-source resistance of MOS pipe Q17 is connected, the other end of resistance R97 in proper order with the one end of resistance R99 and the grid of MOS pipe Q20 is connected, the source of MOS pipe Q20 in proper order with the other end of resistance R99 and the ground P-connection of charger, the drain-source resistance of MOS pipe Q20 with the drain-source resistance of MOS pipe Q19 is connected, and the source of MOS pipe Q20 in proper order with the positive pole of diode D6 and the one end of electric capacity C29 is connected.
Further, the diode D5 and the diode D6 are both zener diodes.
The invention has the beneficial effects that: this circuit can realize control and management to charge-discharge current on the BMS main control board, the circuit control end has adopted opto-coupler isolated control mode, the little voltage circuit of front level has been protected, MOS switch both ends are battery ground and charger ground, because only disconnection and the closure in ground return circuit, so even MOS burns the short circuit under the abnormal conditions, can not produce the strike fire yet, burn heavy current abnormal conditions such as board, the most is the unable control of charge-discharge and turn-offs, it last current can accomplish more than 60A, under the good condition is done in the PCB heat dissipation, can accomplish about 80A.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is one of schematic diagrams of a BMS charge and discharge management circuit according to an embodiment of the present invention;
fig. 2 is a second schematic diagram of a BMS charging and discharging management circuit according to an embodiment of the present invention.
Detailed Description
For further explanation of the various embodiments, the drawings which form a part of the disclosure and which are incorporated in and constitute a part of this specification, illustrate embodiments and, together with the description, serve to explain the principles of operation of the embodiments, and to enable others of ordinary skill in the art to understand the various embodiments and advantages of the invention, and, by reference to these figures, reference is made to the accompanying drawings, which are not to scale and wherein like reference numerals generally refer to like elements.
According to an embodiment of the present invention, there is provided a BMS charging and discharging management circuit.
Referring to the drawings and the detailed description, as shown in fig. 1-2, a BMS charging and discharging management circuit according to an embodiment of the present invention includes a resistor R68, a resistor R71, a resistor R74, a resistor R77, a resistor R84, a resistor R87, a resistor R90, a resistor R93, a transistor Q10, a diode D22, a diode D5, a diode D6, an optocoupler OC2, a discharging MOS circuit, a charging MOS circuit, a capacitor C29, and a capacitor C30;
one end of the resistor R74 is connected with a DSG-EN pin of a single chip microcomputer, the other end of the resistor R74 is sequentially connected with one end of the resistor R77 and a base of the triode Q10, the other end of the resistor R77 is grounded, an emitter of the triode Q10 is grounded, a collector of the triode Q10 is connected with a first input end of the optocoupler OC2 through the resistor R68, a second input end of the optocoupler OC2 is connected with +5V voltage, a first output end of the optocoupler OC2 is connected with an anode of the diode D22 through the resistor R71, a second output end of the optocoupler OC2 is connected with +12V voltage, and a cathode of the diode D22 is sequentially connected with the discharging MOS circuit and the charging MOS circuit;
one end of the discharge MOS circuit far away from the charge MOS circuit is connected with one end of the resistor R84, one end of the resistor R87, one end of the resistor R90 and one end of the resistor R93 in sequence, the other end of the resistor R84, the other end of the resistor R87, the other end of the resistor R90 and the other end of the resistor R93 are respectively connected with a battery negative BAT-in turn, one end of the discharge MOS circuit close to the charge MOS circuit is connected with the anode of the diode D5 and one end of the capacitor C30 in turn, one end of the charging MOS circuit close to the discharging MOS circuit is sequentially connected with the anode of the diode D6 and one end of the capacitor C29, the cathode of the diode D5 is connected with the cathode of the diode D6, the other end of the capacitor C29 is connected with the other end of the capacitor C30, and one end of the charging MOS circuit, which is far away from the discharging MOS circuit, is connected with the ground P-of the charger.
In one embodiment, the discharge MOS circuit includes a MOS transistor Q13, a MOS transistor Q15, a MOS transistor Q17, a MOS transistor Q19, a resistor R81, a resistor R82, a resistor R85, a resistor R88, a resistor R92, a resistor R94, a resistor R96, and a resistor R98.
In one embodiment, one end of the resistor R81 is sequentially connected to a negative electrode of the diode D22, one end of the resistor R85, one end of the resistor R92, and one end of the resistor R96, the other end of the resistor R81 is sequentially connected to one end of the resistor R82 and a gate of the MOS transistor Q13, a source of the MOS transistor Q13 is sequentially connected to the other end of the resistor R82 and one end of the resistor R84, a drain of the MOS transistor Q13 is sequentially connected to the charging MOS circuit and a drain of the MOS transistor Q19, the other end of the resistor R85 is sequentially connected to one end of the resistor R88 and a gate of the MOS transistor Q15, a source of the MOS transistor Q13 is sequentially connected to the other end of the resistor R88 and one end of the resistor R84, a drain of the MOS transistor Q15 is connected to the MOS charging circuit, and the other end of the resistor R92 is sequentially connected to one end of the resistor R94 and one end of the gate of the MOS transistor Q17, the source of MOS pipe Q17 in proper order with the other end of resistance R94 and the one end of resistance R84 is connected, MOS pipe Q17 the drain-source resistance with the MOS circuit connection that charges, the other end of resistance R96 in proper order with the one end of resistance R98 and the grid of MOS pipe Q19 is connected, MOS pipe Q19 the source in proper order with the other end of resistance R98 and the one end of resistance R84 is connected, just MOS pipe Q19 the source in proper order with diode D5's positive pole and the one end of electric capacity C30 is connected.
In one embodiment, the charging MOS circuit includes a MOS transistor Q14, a MOS transistor Q16, a MOS transistor Q18, a MOS transistor Q20, a resistor R79, a resistor R83, a resistor R86, a resistor R89, a resistor R91, a resistor R95, a resistor R97, and a resistor R99.
In one embodiment, one end of the resistor R79 is sequentially connected to the negative electrode of the diode D22, one end of the resistor R86, one end of the resistor R91 and one end of the resistor R97, the other end of the resistor R79 is sequentially connected to one end of the resistor R83 and the gate of the MOS transistor Q14, the source of the MOS transistor Q14 is sequentially connected to the other end of the resistor R83 and the ground P-of the charger, the drain of the MOS transistor Q14 is connected to the drain of the MOS transistor Q13, the other end of the resistor R86 is sequentially connected to one end of the resistor R89 and the gate of the MOS transistor Q16, the source of the MOS transistor Q16 is sequentially connected to the other end of the resistor R89 and the ground P-of the charger, the drain of the MOS transistor Q16 is connected to the drain of the MOS transistor Q15, the other end of the resistor R91 is sequentially connected to one end of the resistor R95 and the gate of the transistor Q18, the source of MOS pipe Q18 in proper order with the other end of resistance R95 and the ground P-connection of charger, the drain-source resistance of MOS pipe Q18 with the drain-source resistance of MOS pipe Q17 is connected, the other end of resistance R97 in proper order with the one end of resistance R99 and the grid of MOS pipe Q20 is connected, the source of MOS pipe Q20 in proper order with the other end of resistance R99 and the ground P-connection of charger, the drain-source resistance of MOS pipe Q20 with the drain-source resistance of MOS pipe Q19 is connected, and the source of MOS pipe Q20 in proper order with the positive pole of diode D6 and the one end of electric capacity C29 is connected.
In one embodiment, the diode D5 and the diode D6 are both zener diodes.
The working principle is as follows: when the BMS charge and discharge management circuit is applied specifically, a charge and discharge control end and an optical coupler isolation circuit are shown in figure 1, a DSG-EN pin of a single chip microcomputer is shown as a control end, and the conduction and the closing of an optical coupler OC2 are realized by controlling the conduction and the cut-off of a triode Q10; FIG. 2 is a detailed diagram of a discharging MOS circuit and a charging MOS circuit,
MOS tube Q13 and MOS tube Q15, MOS tube Q17 and MOS tube Q19 constitute a discharging MOS circuit, the left side of the discharging MOS circuit is connected with battery negative BAT-, MOS tube Q14 and MOS tube Q16, MOS tube Q18 and MOS tube Q20 are charging MOS circuits, the left side of the charging MOS circuit is connected with the right side of the discharging MOS circuit, the right side of the charging MOS circuit is connected with the ground P-of the charger, the charging MOS and the discharging MOS are conducted at the same time, and the loop can be conducted.
A DSG-EN pin of the singlechip is a control end, and the conduction and the cut-off of an optical coupler OC2 are realized by controlling the conduction and the cut-off of a triode Q10, wherein a resistor R71 with the resistance value of 510 ohms is a current-limiting protection resistor, a resistor R71 with the resistance value of 1K at the output end of the optical coupler is a current-limiting protection resistor, and a diode D22 is used for preventing the high voltage of a charge and discharge end from flowing backwards to damage the optical coupler;
the resistor R81, the resistor R85, the resistor R92 and the resistor R96 are VGS current-limiting resistors in the discharging MOS circuit, the resistor R79, the resistor R86, the resistor R91 and the resistor R97 are VGS current-limiting resistors in the charging MOS circuit, the resistor R82, the resistor R88, the resistor R94 and the resistor R98 are unloading resistors at the GS end of the discharging MOS circuit, and the resistor R83, the resistor R89, the resistor R95 and the resistor R99 are unloading resistors at the GS end of the charging MOS circuit;
the diode D5 and the diode D6 are TVS protection tubes at drain and source terminals of the discharging MOS circuit and the charging MOS circuit, respectively, to prevent the MOS from being damaged by high voltage pulses at the drain and source terminals, and the capacitor C29 and the capacitor C30 are buffer capacitors at the drain and source terminals of the discharging MOS circuit and the charging MOS circuit, respectively, to prevent the discharging MOS circuit and the charging MOS circuit from being damaged by an excessively high voltage suddenly rising under a sudden power-on or sudden power-off condition, and only under a condition that the charging and discharging circuits are simultaneously conducted, the circuits have charging or discharging current, and when the circuits are conducted, the battery ground is connected with the ground of the charger to form a current circuit.
The control of the optocoupler OC2 is realized by a singlechip control pin DSG-EN through a triode Q10, when the singlechip control pin DSG-EN is at a high level, the optocoupler OC2 is conducted, and 12V voltage is applied to the grid terminal of the discharge MOS circuit to enable the discharge MOS to be conducted; conversely, the discharge MOS circuit is off. The control of the charging MOS circuit is the same as that of the discharging MOS circuit, the isolation of the control end and the execution end is realized through an optical coupler, the interference and the damage of a rear stage to a front stage are avoided, and in addition, the drain end and the source end of the discharging MOS circuit and the drain end and the source end of the charging MOS circuit are respectively a battery ground and a charger ground, so that the large current and the fire disaster generated under the abnormal condition are avoided.
In summary, according to the above technical solution of the present invention, the circuit can control and manage the charging and discharging current on the BMS host control board, the circuit control terminal adopts an optical coupling isolation control manner to protect the front-stage small voltage circuit, the two terminals of the MOS switch are the battery ground and the charger ground, and only the ground loop is opened and closed, so even if the MOS is in a short circuit due to abnormal conditions, the ignition cannot be generated, the board burning and other abnormal conditions of large current cannot be controlled to be turned off due to the charging and discharging at most, the continuous current can be more than 60A, and the PCB can be controlled to about 80A when the heat dissipation is good.
The specific meanings of the above terms in the present invention can be understood according to specific situations.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. The BMS charge and discharge management circuit is characterized by comprising a resistor R68, a resistor R71, a resistor R74, a resistor R77, a resistor R84, a resistor R87, a resistor R90, a resistor R93, a triode Q10, a diode D22, a diode D5, a diode D6, an optical coupler OC2, a discharge MOS circuit, a charge MOS circuit, a capacitor C29 and a capacitor C30;
one end of the resistor R74 is connected with a DSG-EN pin of a single chip microcomputer, the other end of the resistor R74 is sequentially connected with one end of the resistor R77 and a base of the triode Q10, the other end of the resistor R77 is grounded, an emitter of the triode Q10 is grounded, a collector of the triode Q10 is connected with a first input end of the optocoupler OC2 through the resistor R68, a second input end of the optocoupler OC2 is connected with +5V voltage, a first output end of the optocoupler OC2 is connected with an anode of the diode D22 through the resistor R71, a second output end of the optocoupler OC2 is connected with +12V voltage, and a cathode of the diode D22 is sequentially connected with the discharging MOS circuit and the charging MOS circuit;
one end of the discharge MOS circuit far away from the charge MOS circuit is connected with one end of the resistor R84, one end of the resistor R87, one end of the resistor R90 and one end of the resistor R93 in sequence, the other end of the resistor R84, the other end of the resistor R87, the other end of the resistor R90 and the other end of the resistor R93 are respectively connected with a battery negative BAT-in turn, one end of the discharge MOS circuit close to the charge MOS circuit is connected with the anode of the diode D5 and one end of the capacitor C30 in turn, one end of the charging MOS circuit close to the discharging MOS circuit is sequentially connected with the anode of the diode D6 and one end of the capacitor C29, the cathode of the diode D5 is connected with the cathode of the diode D6, the other end of the capacitor C29 is connected with the other end of the capacitor C30, and one end of the charging MOS circuit, which is far away from the discharging MOS circuit, is connected with the ground P-of the charger.
2. The BMS charging and discharging management circuit according to claim 1, wherein the discharging MOS circuit comprises a MOS transistor Q13, a MOS transistor Q15, a MOS transistor Q17, a MOS transistor Q19, a resistor R81, a resistor R82, a resistor R85, a resistor R88, a resistor R92, a resistor R94, a resistor R96 and a resistor R98.
3. The BMS charge and discharge management circuit according to claim 2, wherein one end of the resistor R81 is sequentially connected to the negative electrode of the diode D22, one end of the resistor R85, one end of the resistor R92, and one end of the resistor R96, the other end of the resistor R81 is sequentially connected to one end of the resistor R82 and the gate of the MOS transistor Q13, the source of the MOS transistor Q13 is sequentially connected to the other end of the resistor R82 and one end of the resistor R84, the drain of the MOS transistor Q13 is sequentially connected to the charging MOS circuit and the drain of the MOS transistor Q19, the other end of the resistor R85 is sequentially connected to one end of the resistor R88 and the gate of the MOS transistor Q15, the source of the MOS transistor Q13 is sequentially connected to the other end of the resistor R88 and one end of the resistor R84, the drain of the MOS transistor Q15 is connected to the charging MOS circuit, the other end of the resistor R92 is sequentially connected to the gate 94 and the gate 17 of the MOS transistor Q17, the source of MOS pipe Q17 in proper order with the other end of resistance R94 and the one end of resistance R84 is connected, MOS pipe Q17 the drain-source resistance with the MOS circuit connection that charges, the other end of resistance R96 in proper order with the one end of resistance R98 and the grid of MOS pipe Q19 is connected, MOS pipe Q19 the source in proper order with the other end of resistance R98 and the one end of resistance R84 is connected, just MOS pipe Q19 the source in proper order with diode D5's positive pole and the one end of electric capacity C30 is connected.
4. The BMS charging and discharging management circuit according to claim 3, wherein the charging MOS circuit comprises a MOS transistor Q14, a MOS transistor Q16, a MOS transistor Q18, a MOS transistor Q20, a resistor R79, a resistor R83, a resistor R86, a resistor R89, a resistor R91, a resistor R95, a resistor R97 and a resistor R99.
5. The BMS charge and discharge management circuit according to claim 4, wherein one end of said resistor R79 is sequentially connected to a negative electrode of said diode D22, one end of said resistor R86, one end of said resistor R91 and one end of said resistor R97, the other end of said resistor R79 is sequentially connected to one end of said resistor R83 and a gate of said MOS transistor Q14, the source of said MOS transistor Q14 is sequentially connected to the other end of said resistor R83 and a ground P-of said charger, the drain of said MOS transistor Q14 is connected to the drain of said MOS transistor Q13, the other end of said resistor R86 is sequentially connected to one end of said resistor R89 and a gate of said MOS transistor Q16, the source of said MOS transistor Q16 is sequentially connected to the other end of said resistor R89 and a ground P-of said charger, the drain of said MOS transistor Q16 is connected to the drain of said MOS transistor Q15, the other end of said resistor R5 is sequentially connected to one end of said resistor R95 and a gate of said MOS transistor Q57324, the source of MOS pipe Q18 in proper order with the other end of resistance R95 and the ground P-connection of charger, the drain-source resistance of MOS pipe Q18 with the drain-source resistance of MOS pipe Q17 is connected, the other end of resistance R97 in proper order with the one end of resistance R99 and the grid of MOS pipe Q20 is connected, the source of MOS pipe Q20 in proper order with the other end of resistance R99 and the ground P-connection of charger, the drain-source resistance of MOS pipe Q20 with the drain-source resistance of MOS pipe Q19 is connected, and the source of MOS pipe Q20 in proper order with the positive pole of diode D6 and the one end of electric capacity C29 is connected.
6. The BMS charge and discharge management circuit according to claim 5, wherein both of the diode D5 and the diode D6 are zener diodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910989626.2A CN110797937A (en) | 2019-10-17 | 2019-10-17 | BMS charge and discharge management circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910989626.2A CN110797937A (en) | 2019-10-17 | 2019-10-17 | BMS charge and discharge management circuit |
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| CN110797937A true CN110797937A (en) | 2020-02-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118889350A (en) * | 2024-09-27 | 2024-11-01 | 中发信息咨询(浙江)有限公司 | A three-phase current limiting protection circuit |
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