CN110797363A - Back-illuminated time-delay integral image sensor and method of forming the same - Google Patents

Abstract

A backside illuminated time delay integral image sensor and a method for forming the same, wherein the backside illuminated time delay integral image sensor comprises: a substrate, the substrate includes a first face and a second face opposite, the substrate includes a plurality of photoelectric doping the first surface exposes the surface of the photoelectric doped region; the circuit device layer on the first surface; the anti-reflection and anti-reflection layer on the second surface, and the anti-reflection and anti-reflection layer covering several of the photoelectrically doped regions. The back-illuminated time delay integrating image sensor has higher performance.

Description

Back-illuminated time-delay integral image sensor and method of forming the same

technical field

The present invention relates to the field of semiconductors, and in particular, to a back-illuminated time-delay integral image sensor and a method for forming the same.

Background technique

Time Delay Integration (TDI) image sensor is an evolution of linear image sensor. The imaging mechanism of the time-delay integral image sensor is to expose the pixels passing through the photographed object line by line, and accumulate the exposure results, so as to solve the problem of weak imaging signal caused by insufficient exposure time of high-speed moving objects. The time-delay integral image sensor can increase the effective exposure time and improve the image signal-to-noise ratio.

Time-delay integral image sensors are divided into two types: CCD and CMOS. One is to make a TDI image sensor on the CCD process. Due to the particularity of the CCD process, other processing circuits cannot be integrated on the image sensor, and the versatility and flexibility are poor. Another TDI image sensor is a CMOS type. The TDI image sensor is based on a general CMOS manufacturing process, and a device similar to a CCD function is embedded, namely an eCCD (embedded CCD), thereby forming a TDI-CMOS image sensor.

However, the performance of existing TDI-CMOS image sensors is still poor.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a back-illuminated time-delay integral image sensor and a method for forming the same, so as to improve the performance of the back-illuminated time-delay integral image sensor.

In order to solve the above technical problems, the technical solution of the present invention provides a backside-illuminated time-delay integral image sensor, comprising: a substrate, the substrate includes a first surface and a second surface opposite to each other, the substrate includes a plurality of photoelectric doped regions, and the first surface exposes the surface of the photoelectric doped region; the circuit device layer on the first surface; the anti-reflection and anti-reflection layer on the second surface, and the anti-reflection and anti-reflection layer covers several the photoelectrically doped region.

Optionally, the material of the anti-reflection and anti-reflection layer includes: fluoride, oxide or nitride; the fluoride includes: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, Tantalum oxide or Al2O3; the nitride includes: silicon nitride or oxynitride silicide.

Optionally, the thickness of the anti-reflection and anti-reflection layer ranges from 200 angstroms to 1500 angstroms.

Optionally, the circuit device layer includes: a dielectric layer on a substrate; a plurality of gate structures located in the dielectric layer, the plurality of gate structures are located on the surface of each of the photoelectric doped regions, and a plurality of the gate structures are located in the dielectric layer. The gate structure is located on the first side; the interconnect structure is located in the dielectric layer.

Optionally, a plurality of the gate structures are arranged in parallel along a first direction, and a plurality of the gate structures straddle one of the photoelectric doped regions along a second direction, and the second direction is perpendicular to the first direction.

Optionally, the interconnection structure includes: a plurality of overlapping conductive layers located on the gate structure; conductive layers located between two adjacent conductive layers, between the conductive layer and the substrate, or between the conductive layer and the gate structure plug.

Optionally, it further includes: a first protective layer on the surface of the dielectric layer.

Optionally, the material of the first protective layer includes: silicon oxide, silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

Optionally, it further includes: a second protective layer located on the surface of the second surface, and the second protective layer is located between the anti-reflection and anti-reflection layer and the substrate.

Optionally, the material of the second protective layer includes: silicon oxide, silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

Optionally, the gate structure includes: a gate dielectric layer on the surface of the first surface and a gate electrode layer on the surface of the gate dielectric layer.

Optionally, the substrate further includes: a plurality of isolation regions, the isolation regions are located between adjacent photoelectric doping regions; and an isolation structure is provided in the isolation regions.

Optionally, the substrate is doped with first ions; the photoelectric doped region is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.

Correspondingly, the technical solution of the present invention also provides a method for forming a backside illuminated time-delay integral image sensor according to any of the above, including: providing a substrate, the substrate includes a first surface and a second surface opposite to each other, and the substrate includes a plurality of a photoelectric doped region, and the first surface exposes the surface of the photoelectric doped region; a circuit device layer is formed on the first surface; an anti-reflection and antireflection layer is formed on the second surface, and the The anti-reflection and anti-reflection layer covers several of the photoelectric doped regions.

Optionally, the formation process of the anti-reflection and anti-reflection layer includes: chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

Optionally, the circuit device layer includes: a dielectric layer on a substrate; a plurality of gate structures located in the dielectric layer, the plurality of gate structures are located on the surface of each of the photoelectric doped regions, and a plurality of the gate structures are located in the dielectric layer. The gate structure is located on the first surface; the interconnection structure is located in the dielectric layer; the method for forming the back-illuminated time delay integration image sensor further includes: after forming the dielectric layer, forming the anti-reflection and anti-reflection Before the layer, a first protective layer is formed on the surface of the dielectric layer.

Optionally, the method further includes: after forming the first protective layer and before forming the anti-reflection and anti-reflection layer, forming a second protective layer on the surface of the second surface.

Optionally, the method further includes: performing a thinning process on the substrate after forming the first protective layer and before forming the second protective layer.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the back-illuminated time-delay integral image sensor provided by the technical solution of the present invention, the second surface has an anti-reflection and anti-reflection layer. When the light is illuminated from the back of the image sensor, that is, the light passing through the anti-reflection and anti-reflection layer enters the substrate from the second surface, so that the incident light can directly enter the photoelectric doped region for photoelectric conversion, thereby avoiding Being blocked by the devices in the circuit device layer, it is beneficial to increase the amount of incident light, thereby improving the sensitivity, signal-to-noise ratio and quantum effect of the back-illuminated time delay integral image sensor, so that the back-illuminated time delay integral image sensor is blocked. The performance of the sensor is better.

Further, the back-illuminated time-delay integral image sensor further includes: a first protective layer on the surface of the interconnect structure, the first protective layer can reduce the influence of the conductive layer and the conductive plug in the interconnect structure by subsequent processes , to protect the interconnect structure. Further, the back-illuminated time delay integral image sensor further includes: a second protective layer on the second surface, and the second protective layer is located between the anti-reflection and anti-reflection layer and the substrate. On the one hand, the second protective layer can increase the bonding force between the anti-reflection and anti-reflection layer and the substrate; on the other hand, the second protective layer can passivate the silicon surface and reduce the damage to the silicon substrate and ionic contamination.

Description of drawings

1 to 3 are schematic structural diagrams of a time-delay integral image sensor;

4 to 11 are schematic structural diagrams of steps of a method for forming a backside-illuminated time-delay integral image sensor according to an embodiment of the present invention.

Detailed ways

As mentioned in the background, existing time delay integrating image sensors have poor performance.

The reasons for the poor performance of the existing time delay integration image sensor will be described in detail below with reference to the accompanying drawings. FIG. 1 to FIG. 3 are schematic structural diagrams of a time delay integration image sensor.

Please refer to FIGS. 1 to 3. FIG. 2 is a schematic cross-sectional view of FIG. 1 along the tangent line A-A1, FIG. 3 is a schematic cross-sectional view of FIG. 1 along the tangent line B-B1, and FIG. 1 is a top view of FIG. 2 along the X direction. 1 is a schematic diagram omitting the structure on the gate structure, the image sensor includes: a substrate 100, the substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, and the substrate 100 includes A plurality of pixel regions I have isolation regions II between adjacent pixel regions I; a photoelectric doping region 110 located in the pixel region I; a number of gate structures 120 located on the first surface 101, and a number of all The gate structure 120 spans one of the photoelectrically doped regions; the interconnect structure 130 is located on the gate structure; the anti-reflection and anti-reflection layer 140 is located on the interconnect structure 130 .

In the above time-delay integral image sensor, the substrate 100 has first dopant ions, the photoelectric doping region 110 has second dopant ions, and the conductivity type of the first dopant ions is the same as the second dopant ion. The conductivity type of the impurity ions is reversed and thus can form a photodiode. When light irradiates the substrate 100, the photodiode converts photons into electrons through the photovoltaic effect, thereby realizing the generation of signal charges; When a potential well is formed, the electrons generated by the photodiode are collected into the potential well, thereby realizing the storage of signal charges; by applying different voltages on different gate structures 120, the charges stored in the potential well can be driven to move toward a certain direction to transmit.

However, when light irradiates the time-delay integrator image sensor from the front, that is, from the anti-reflection and anti-reflection layer 120 on the first surface 101 , the light is affected by the stacked interconnect structure 130 before entering the substrate 100 . and the blocking of several gate structures 120 , resulting in lower sensitivity, signal-to-noise ratio and quantum efficiency of the image sensor, resulting in poor performance of the image sensor.

In order to solve the above technical problem, an embodiment of the present invention provides a backside-illuminated time-delay integrator image sensor, including: a substrate includes a first surface and a second surface opposite to each other, the substrate includes a plurality of photoelectric doped regions, and the first surface The surface of the photoelectric doped region is exposed on one side; the circuit device layer is located on the first side; the anti-reflection and anti-reflection layer is located on the second side, and the anti-reflection and anti-reflection layer covers a plurality of the photoelectric doped regions Miscellaneous area. The performance of the graphics sensor is better.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

4 to 11 are schematic structural diagrams of each step of a method for forming a backside-illuminated time delay integrating image sensor according to an embodiment of the present invention.

Please refer to FIGS. 4 and 5. FIG. 5 is a schematic cross-sectional view of FIG. 4 along the M-N tangent direction, and FIG. 4 is a top view of FIG. 5 along the X direction. On the second surface 202 , the substrate 200 includes a plurality of photoelectric doping regions 210 , and the first surface 201 exposes the surface of the photoelectric doping regions 210 .

The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the substrate 200 further includes: a plurality of isolation regions (not marked in the figure), the isolation regions are located between adjacent photoelectric doping regions 210 ; and the isolation regions have isolation structures 211 .

In this embodiment, the substrate 200 is doped with first ions; the photoelectric doping region 210 is doped with second ions, and the first ions and the second ions have opposite conductivity types.

Specifically, the substrate 200 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on the surface of the substrate, and the first surface 201 is the exposed surface of the silicon epitaxial layer, so The second surface 202 is the exposed surface of the substrate.

Since the conductivity types of the second dopant ions in the photoelectric doping region 210 are opposite to the conductivity types of the first dopant ions in the substrate 200 , a photodiode is formed. The photodiode is used to convert photons in incident light into electrons.

In this embodiment, the first ions are P-type ions, including boron ions, and the second ions are N-type ions, including phosphorus ions or arsenic ions.

In other embodiments, the first ions are N-type ions, and the second ions are P-type ions.

Please refer to FIGS. 6 and 7 , FIG. 6 is a schematic diagram based on FIG. 4 , and FIG. 7 is a schematic diagram based on FIG. 5 . It should be noted that FIG. 6 is a schematic diagram omitting the structure on the gate structure. A circuit device layer 220 is formed on the first surface 201 .

The circuit device layer 220 is used to electrically connect the photodiode with peripheral circuits.

The circuit device layer 220 includes: a dielectric layer (not marked in the figure) located on the substrate 200; a plurality of gate structures 221 located in the dielectric layer, and the plurality of gate structures 221 are located in each of the photoelectric doping layers. The surface of the region 210, and a plurality of the gate structures 210 are located on the first surface 201; the interconnect structures 224 are located in the dielectric layer.

The method for forming the circuit device layer 220 includes: forming a plurality of gate structures 221 on the first surface 201 ; forming a first dielectric layer 222 on the first surface 201 and covering the first dielectric layer 222 a plurality of top surfaces and sidewall surfaces of the gate structures 221; a second dielectric layer 223 is formed on the surface of the first dielectric layer 221, and the second dielectric layer 223 has an interconnection structure 224 therein.

In this embodiment, the dielectric layer includes a first dielectric layer 222 located on the first surface 201 and a second dielectric layer 223 located on the surface of the first dielectric layer 222 .

In this embodiment, a plurality of the gate structures 221 are arranged in parallel along the first direction Y1, and a plurality of the gate structures straddle one of the photoelectric doped regions 210 along the second direction Y2, and the second direction Y2 is vertical in the first direction Y1.

In this embodiment, the interconnect structure 224 includes: a plurality of overlapping conductive layers (not shown in the figure) located on the gate structure 221; located between two adjacent conductive layers and between the conductive layer and the substrate A conductive plug (not marked in the figure) between or between the conductive layer and the gate structure.

Referring to FIG. 8 , a first protective layer 230 is formed on the surface of the circuit device layer 220 .

In this embodiment, specifically, the first protective layer 230 is formed on the surface of the dielectric layer.

The first protective layer 230 is used to reduce the influence of the external environment on the devices in the circuit device layer 220 .

The material of the first protective layer 230 includes: silicon oxide, silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

In this embodiment, the material of the first protective layer 230 is silicon oxide.

The formation process of the first protective layer 230 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

Referring to FIG. 9 , after the first protective layer 230 is formed, the substrate 200 is thinned.

It should be noted that the thinned substrate 200 is still the substrate 200 , and the thinned substrate 200 includes a first surface 201 and a second surface 202 opposite to each other.

The method for the thinning process includes: providing a carrier substrate (not shown in the figure); bonding the surface of the carrier substrate with the surface of the first protective layer 230 on the base 200; the bonding process After that, a thinning process is performed on the substrate 200 from the surface of the second surface 202 to form the final substrate 200 .

The thinning process includes: a chemical mechanical polishing process.

Referring to FIG. 10 , after the thinning process, a second protective layer 240 is formed on the surface of the second surface 202 .

The function of the second protective layer 240 is, on the one hand, to increase the bonding force between the subsequently formed anti-reflection and anti-reflection layer and the substrate 200, and on the other hand, to reduce the damage and ion contamination of the silicon substrate.

The formation process of the second protective layer 240 includes: thermal oxidation process, chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

The material of the second protective layer 240 includes: silicon oxide, silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

In this embodiment, the material of the second protective layer 240 is silicon oxide.

Referring to FIG. 11 , after the second protective layer 240 is formed, an anti-reflection and anti-reflection layer 250 is formed on the second surface 202 , and the anti-reflection and anti-reflection layer 250 covers a plurality of the photoelectric doped regions 210 .

The anti-reflection and anti-reflection layer 250 is used to reduce the reflection of light, thereby helping to increase the amount of incident light.

The material of the anti-reflection and anti-reflection layer 250 includes: fluoride, oxide or nitride; the fluoride includes: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide or Al2O3; the nitride includes: silicon nitride or oxynitride silicide. In this embodiment, the material of the anti-reflection and anti-reflection layer 250 is tantalum oxide, and the thickness of the anti-reflection and anti-reflection layer is 520 angstroms. The anti-reflection and anti-reflection layer 250 can effectively reduce the reflection of light, thereby increasing the The incident amount of light entering the substrate 200 is large.

The process of forming the anti-reflection and anti-reflection layer 250 includes: chemical vapor deposition process, physical vapor deposition process or spin coating process.

By forming the anti-reflection and anti-reflection layer 250 on the second surface 202 . When the light is illuminated from the back of the time delay integral image sensor, that is, the light passing through the anti-reflection and anti-reflection layer 250 enters the substrate 200 from the second surface 202, so that the incident light can directly enter the photoelectric doped region 210. Photoelectric conversion is performed in the circuit device layer 220 to avoid blocking by the devices in the circuit device layer 220, which is beneficial to the improvement of the light incident amount, thereby improving the sensitivity, signal-to-noise ratio and quantum effect of the image sensor, so that the performance of the image sensor is higher than that of the image sensor. it is good.

Correspondingly, an embodiment of the present invention further provides a back-illuminated time-delay integrator image sensor formed by the above method. Please continue to refer to FIG. 11 . surface 202, the substrate 200 includes a plurality of photoelectric doping regions 210, and the first surface 201 exposes the surface of the photoelectric doping regions 210; the circuit device layer 220 on the first surface 201; the second surface 201 The anti-reflection and anti-reflection layer 250 on the surface 202 , and the anti-reflection and anti-reflection layer 250 covers a plurality of the photoelectric doped regions 210 .

Because the second surface 202 has an anti-reflection and anti-reflection layer 250 . When the light is illuminated from the back of the image sensor, that is, the light passing through the anti-reflection and anti-reflection layer 250 enters the substrate 200 from the second surface 202, so that the incident light can directly enter the photoelectric doped region 210 for photoelectricity. conversion, thereby avoiding being blocked by devices in the circuit device layer 220, which is beneficial to increase the amount of incident light, thereby improving the sensitivity, signal-to-noise ratio and quantum effect of the image sensor, making the image sensor better.

The following detailed description is given in conjunction with the accompanying drawings.

The material of the anti-reflection and anti-reflection layer 250 includes: fluoride, oxide or nitride; the fluoride includes: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide or Al2O3; the nitride includes: silicon nitride or oxynitride silicide.

In this embodiment, the material of the anti-reflection and anti-reflection layer 250 is tantalum oxide.

The thickness of the anti-reflection and anti-reflection layer 250 ranges from 200 angstroms to 1500 angstroms.

The significance of selecting the thickness range is: if the thickness is less than 200 angstroms, the anti-reflection and anti-reflection layer 250 with a thickness that is too thin cannot effectively reduce the reflection of light, resulting in that the amount of incident light entering the substrate 200 is still low. The performance of the formed image sensor is poor; if the thickness is greater than 1500 angstroms, under the condition of ensuring that the reflection of light is fully avoided, forming an anti-reflection and anti-reflection layer 250 with a thickness that is too thick will correspondingly increase the process cost and process time. Not conducive to improving work efficiency.

The circuit device layer 220 includes: a dielectric layer (not shown in the figure) located on the substrate 200; a plurality of gate structures 221 located in the dielectric layer, and the plurality of gate structures 221 are located in each of the photoelectric doping layers. The surface of the region 210, and a plurality of the gate structures 221 are located on the first surface 201; the interconnect structures 224 are located in the dielectric layer.

In this embodiment, the dielectric layer includes a first dielectric layer 222 located on the first surface 201 and a second dielectric layer 223 located on the surface of the first dielectric layer 222 .

In this embodiment, a plurality of the gate structures 221 are arranged in parallel along the first direction Y1 (shown in FIG. 7 ), and a plurality of the gate structures 221 are arranged across one along the second direction Y2 (shown in FIG. 7 ). In the photoelectric doped region 210, the second direction Y2 is perpendicular to the first direction Y1.

The gate structure 221 includes a gate dielectric layer (not shown in the figure) on the surface of the first surface 201 and a gate electrode layer (not shown in the figure) on the surface of the gate dielectric layer.

In this embodiment, the material of the gate dielectric layer is silicon oxide, and the material of the gate electrode layer is polysilicon.

The interconnection structure 224 includes: several overlapping conductive layers (not shown in the figure) located on the gate structure 221; located between two adjacent conductive layers, between the conductive layer and the substrate, or between the conductive layer and the gate Conductive plugs (not shown) between structures.

The backside illuminated time delay integral image sensor further includes: a first protective layer 230 on the surface of the medium layer.

The first protective layer 230 can reduce the influence of the conductive layers and conductive plugs in the interconnection structure 224 by subsequent processes, and protect the interconnection structure 224, thereby improving the performance of the image sensor.

The material of the first protective layer 230 includes: silicon oxide, silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

In this embodiment, the material of the first protective layer 230 is silicon oxide.

The BSI image sensor further includes: a second protective layer 240 located on the surface of the second surface 202 , and the second protective layer 240 is located between the anti-reflection and anti-reflection layer 250 and the substrate 200 .

The role of the second protective layer 240 is that, on the one hand, the second protective layer 240 can increase the bonding force between the anti-reflection and anti-reflection layer 250 and the substrate 200, and on the other hand, the second protective layer It can passivate the silicon surface and reduce the damage and ion contamination of the silicon substrate.

The material of the second protective layer 240 includes: silicon oxide, silicon nitride, silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

In this embodiment, the material of the second protective layer 240 is silicon oxide.

In this embodiment, the substrate 200 further includes: a plurality of isolation regions (not shown in the figure), the isolation regions are located between adjacent photoelectric doping regions 210 ; and the isolation regions have isolation structures 211 .

In this embodiment, the substrate 200 is doped with first ions; the photoelectric doped region is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (18)

1. A backside-illuminated time delay integral image sensor, comprising:

the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surfaces of the photoelectric doping regions are exposed out of the first face;

a circuit device layer on the first side;

and the anti-reflection and anti-reflection layer is positioned on the second surface and covers a plurality of the photoelectric doped regions.

2. The backside-illuminated time delay integration image sensor of claim 1, wherein the material of the anti-reflection layer comprises: fluoride, oxide or nitride; the fluorinated compound comprises: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide, or aluminum oxide; the nitride includes: silicon nitride or silicon oxynitride.

3. The backside illuminated time delay integration image sensor of claim 1, wherein the anti-reflection layer has a thickness in the range of: 200 to 1500 angstroms.

4. The backside-illuminated time delay integrating image sensor of claim 1, wherein the circuit device layer comprises: a dielectric layer on the substrate; a plurality of gate structures located in the dielectric layer, the plurality of gate structures being located on the surface of each of the photoelectric doped regions, and the plurality of gate structures being located on the first surface; an interconnect structure located within the dielectric layer.

5. The backside illuminated time delay integrating image sensor of claim 4, wherein a plurality of the gate structures are arranged in parallel along a first direction, and a plurality of the gate structures cross one of the electro-optically doped regions along a second direction, the second direction being perpendicular to the first direction.

6. The backside-illuminated time delay integrating image sensor of claim 4, wherein the interconnect structure comprises: several overlapped conductive layers on the gate structure; and the conductive plugs are positioned between two adjacent conductive layers, between the conductive layers and the substrate or between the conductive layers and the grid electrode structure.

7. The backside illuminated time delay integrating image sensor of claim 4, further comprising: and the first protective layer is positioned on the surface of the dielectric layer.

8. The backside-illuminated time delay integration image sensor of claim 7, wherein the material of the first protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

9. The backside-illuminated time delay integration image sensor of claim 1, further comprising: and the second protective layer is positioned on the surface of the second surface and positioned between the anti-reflection layer and the substrate.

10. The backside-illuminated time delay integration image sensor of claim 9, wherein the material of the second protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

11. The backside-illuminated time delay integrating image sensor of claim 4, wherein the gate structure comprises: the gate electrode layer is positioned on the surface of the gate dielectric layer.

12. The backside-illuminated time delay integration image sensor of claim 1, wherein the substrate further comprises: the isolation regions are positioned between the adjacent photoelectric doping regions; the isolation region has an isolation structure therein.

13. The backside-illuminated time delay integration image sensor of claim 1, wherein the substrate is doped with first ions; the photoelectric doping area is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.

14. The method of forming a backside illuminated time delay integrating image sensor of any of claims 1 to 13, comprising:

providing a substrate, wherein the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surface of each photoelectric doping region is exposed by the first face;

forming a circuit device layer on the first face;

and forming an anti-reflection and anti-reflection layer on the second surface, wherein the anti-reflection and anti-reflection layer covers a plurality of photoelectric doped regions.

15. The method of claim 14, wherein the anti-reflection layer is formed by a process comprising: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

16. The method of forming a backside illuminated time delay integrating image sensor of claim 14, wherein the circuit device layer comprises: a dielectric layer on the substrate; the gate structures are positioned in the dielectric layer, positioned on the surface of each photoelectric doping region and positioned on the first surface; an interconnect structure located within the dielectric layer; the method for forming the image sensor further comprises the following steps: and after the dielectric layer is formed and before the anti-reflection and anti-reflection layer is formed, forming a first protective layer on the surface of the dielectric layer.

17. The method of forming a backside illuminated time delay integrating image sensor of claim 16, further comprising: and after the first protective layer is formed and before the anti-reflection and anti-reflection layer is formed, a second protective layer is formed on the surface of the second surface.

18. The method of forming a backside illuminated time delay integrating image sensor of claim 17, further comprising: and thinning the substrate after the first protective layer is formed and before the second protective layer is formed.

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