CN110780184A - Integrated circuit test system and test method - Google Patents
Integrated circuit test system and test method Download PDFInfo
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- CN110780184A CN110780184A CN201910998342.XA CN201910998342A CN110780184A CN 110780184 A CN110780184 A CN 110780184A CN 201910998342 A CN201910998342 A CN 201910998342A CN 110780184 A CN110780184 A CN 110780184A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application discloses an integrated circuit test system and a test method. The integrated circuit test system comprises: the probe card is used for connecting with a target to be detected; the pattern signal generating module is connected with the probe card and used for generating a test signal; the human-computer interaction module is connected with the graphic signal generation module; the graphic signal generation module comprises a single chip microcomputer and an FPGA unit, a test instruction is transmitted to the single chip microcomputer through the man-machine interaction module, the single chip microcomputer controls the FPGA unit to generate a corresponding test signal, and the test signal is transmitted to a target to be tested through the probe card. The graphic signal generating module is used as a core component, the single chip microcomputer in the module is used as a control unit, and the FPGA unit is controlled to generate corresponding test signals, so that the size of the test system can be greatly reduced, the cost is reduced, and the reliability and the usability of the test system are enhanced.
Description
Technical Field
The invention relates to the technical field of semiconductor test analysis, in particular to a process failure test system and a test method.
Background
In the prior art, a plurality of ICs are generally fabricated in the form of dies at a time on a semiconductor material wafer, and the semiconductor wafer is divided after fabrication is completed to obtain a plurality of individual IC chips. Therefore, before being singulated into packages and mounted in various electronic systems, the IC needs to be tested to evaluate its functionality, in particular to ensure that it is not defective.
The existing wafer test machine is large in size, occupied space and inconvenient to carry, cannot be carried, only can support testing in a fixed occasion, is not enough in flexibility and convenience, cannot be used independently, needs to carry out human-computer interaction through a PC (personal computer), has certain network risk, is complex in operation interface, and can be used proficiently after being trained for many times by an operator. The equipment cost and the labor cost are high, and the large-area application cannot be realized.
It is desirable to further improve the wafer tester to reduce the cost of the test system, enhance the reliability and ease of use, and reduce the space occupied by the test system.
Disclosure of Invention
The invention aims to provide a portable integrated circuit test system and a test method, wherein a graphic signal generation module is used as a core component, a singlechip in the module is used as a control unit, and an FPGA unit is controlled to generate a corresponding test signal, so that the volume of the test system can be reduced, the cost is reduced, and the usability of the test system is enhanced.
According to an aspect of the present invention, there is provided an integrated circuit test system, comprising: the probe card is used for connecting with a target to be detected; the pattern signal generating module is connected with the probe card and used for generating a test signal; the human-computer interaction module is connected with the graphic signal generation module; the graphic signal generation module comprises a single chip microcomputer and an FPGA unit, a test instruction is transmitted to the single chip microcomputer through the man-machine interaction module, the single chip microcomputer controls the FPGA unit to generate a corresponding test signal, and the test signal is transmitted to a target to be tested through the probe card.
Preferably, the graphics signal generating module further includes a clock unit and a storage unit, the clock unit is configured to generate a clock signal, and the storage unit is configured to store a test result and a preset test instruction.
Preferably, the probe card is suitable for a plurality of objects to be tested, and the preset test instructions also include a plurality of types, which are respectively suitable for the plurality of objects to be tested.
Preferably, the graphic signal generation module further comprises a communication unit, and the communication unit comprises a plurality of I/O interfaces respectively used for communicating with the probe card, the human-computer interaction module and an external device.
Preferably, the communication unit comprises a network port, and the human-computer interaction module is connected with the graphic signal generation module through the network port.
Preferably, the number of the network ports is multiple, and at least one network port is used for connecting external equipment, so that the external equipment obtains the test result.
Preferably, the probe card is connected to the pattern signal generating module by a bus cable.
Preferably, the human-computer interaction module comprises a display unit and an input unit, the input unit is used for inputting a test instruction, and the display unit is used for displaying input information, related parameters and a test result.
Preferably, the graphic signal generation module and the human-computer interaction module are designed in an integrated manner.
According to another aspect of the present invention, there is provided an integrated circuit testing method, the method comprising the steps of: initializing a graphics signal generation module; inputting a command prompt corresponding to the test; the FPGA unit generates a test signal and transmits the test signal into a target to be tested through a probe card; the target to be tested receives and executes the test signal, and transmits the generated feedback information to the singlechip; the single chip transmits the test result to the man-machine interaction module for display.
Preferably, the single chip microcomputer generates a corresponding test instruction according to the command prompt, and transmits the test instruction to the FPGA unit, so that the FPGA unit generates a corresponding test signal.
Preferably, the graphics signal generating module further includes a storage unit, the test result is stored in the storage unit, and the test result in the storage unit can be extracted to other external devices through the I/O interface as needed.
The integrated circuit test system and the test method provided by the embodiment of the invention adopt the graphic signal generation module as a core component, use the single chip microcomputer in the module as a control unit, and control the FPGA unit on the module to generate the corresponding test signal, thereby effectively reducing the volume of the test system and greatly reducing the cost of the test system. Furthermore, because the test system adopts an embedded design, a large amount of complex information such as setting parameters can be set in the test system in advance, an operator can test the target to be tested only by carrying out a very small amount of operation, the test method is simple and stable, the operator can be skillfully used only by simple training, and the test system and the test method have very strong usability and stability and are convenient for large-scale application.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 shows a schematic diagram of an integrated circuit test system according to a first embodiment of the invention.
FIG. 2 shows a schematic diagram of an integrated circuit test system according to a second embodiment of the invention.
FIG. 3 shows a flow chart of the integrated circuit testing method of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
In the following description, numerous specific details of the invention, such as specific models of singlechips and FPGA units, specific styles of communication interfaces, etc., are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
In the prior art, a test system is usually a large-scale machine, the cost is high, the occupied area is large, the use is not convenient, furthermore, the machine needs to be connected with a PC, human-computer interaction and corresponding test operation are carried out depending on the PC, and certain network risk exists.
The inventor of the present application has noted the above problem, and thus proposes a portable integrated circuit testing system and testing method.
The present invention may be embodied in many forms, some examples of which are described below.
FIG. 1 shows a schematic diagram of an integrated circuit test system according to a first embodiment of the invention. In this embodiment the integrated circuit test system comprises: a probe card 110, a graphic signal generation module 120, and a human-machine interaction module 130. The illustration shows only 1 probe card 110, it should be understood that the present invention is not limited thereto, and the integrated circuit test system may include a plurality of probe cards 110, and a plurality of probe cards 110 are connected to the same pattern signal generating module 120, and such cases should also be included in the scope of the present invention.
The probe card 110 is connected to an object to be tested, the probe card 110 includes a plurality of test heads, for example, and can be applied to a plurality of objects to be tested, and the probe card 110 is connected to the pattern signal generating module 120, for example, by a flat cable, to obtain a desired test signal and transmit the test signal to the object to be tested.
The graphics signal generating module 120 includes, for example, a single chip 121, an FPGA unit 122, a clock unit 123, a storage unit 124, and a communication unit 125, where the clock unit 123 is configured to generate a clock signal for the graphics signal generating module 120 to use; the storage unit 124 is configured to store a test result and a preset test instruction, where the preset test instruction includes multiple types, and is respectively applicable to multiple types of targets to be tested; the communication unit 125 includes, for example, a plurality of I/O interfaces, specifically, a flex cable interface, a network interface, a USB interface, etc., and the graphics signal generating module 120 communicates with the probe card 110 and the human-machine interaction module 130 through the communication unit 125, respectively. The single chip 121 is used as a control unit of the whole graphic signal generation module 120, for example, the single chip 121 is an STM32 series; the FPGA unit 122 is used to generate a test signal, and the FPGA unit is controlled by the single chip 121 to generate a corresponding test signal, for example, an FPGA unit of Xilinx corporation.
The human-computer interaction module 130 includes, for example, an output unit 131 and an input unit 132; the human-computer interaction module 130 is connected to the graphics signal generation module 120 through a network port, the output unit 131 is an LCD display, the input unit 132 is a keyboard key, for example, 51 singlechips are selected for the human-computer interaction module 130 to drive the LCD display and the keyboard key, and an operator can input a corresponding command prompt through the keyboard key to control the graphics signal generation module 120, so that the graphics signal generation module 120 generates a corresponding test signal and provides the test signal to a target to be tested, and the LCD display obtains relevant parameter information such as a test result.
Fig. 2 is a schematic diagram of an integrated circuit testing system according to a second embodiment of the present invention, wherein a structure similar to that of the first embodiment is not repeated herein, and only different parts thereof are described.
The second embodiment changes the human-computer interaction module outside the graphics signal generation module in the first embodiment into the human-computer interaction unit 126 and integrates the human-computer interaction unit into the graphics signal generation module, so that the test system can be made into an all-in-one machine, and is smaller in size and more convenient to use and move.
As shown in fig. 2, the integrated circuit testing system includes a first probe card 111 and a second probe card 112, which total 2 probe cards, wherein the first probe card 111 and the second probe card 112 may be the same probe card, and can measure two same objects to be tested simultaneously, thereby improving testing efficiency; of course, the integrated circuit test system can also be provided with more probe cards according to actual needs so as to further improve the test efficiency.
Further, when the first probe card 111 and the second probe card 112 are different probe cards for measuring different targets to be tested, two different test signals need to be generated for simultaneously measuring two different targets to be tested, in this case, an additional FPGA unit may be added to the graphic signal generating module for generating additional test signals.
FIG. 3 shows a flow chart of the integrated circuit testing method of the present invention, which includes the steps of:
s10, inputting an initialization instruction through the man-machine interaction module, and initializing the graphic signal generation module; an operator connects the probe card with a target to be tested, connects the probe card with the graphic signal generation module through a flat cable, starts the graphic signal generation module after connection is completed, and inputs an initialization instruction through the human-computer interaction module to initialize the graphic signal generation module.
S20, inputting a command prompt corresponding to the test through the man-machine interaction module; and inputting a corresponding command prompt symbol by an operator at the man-machine interaction module according to the test target and the test requirement.
S30, packing information flow according to the command prompt and transmitting to the single chip; the man-machine interaction module packs the command prompt symbols into corresponding information streams according to an information transmission protocol between the man-machine interaction module and the image signal generation module and transmits the corresponding information streams to the single chip microcomputer of the image signal generation module.
The S40 singlechip generates a corresponding test instruction and forwards the test instruction to the FPGA unit; the single chip microcomputer unpacks the information flow to obtain a command prompt, generates a corresponding test instruction according to the corresponding relation between the command prompt and the test instruction prestored in the storage module, and forwards the test instruction to the FPGA unit.
S50, generating a test signal by the FPGA unit and transmitting the test signal to a target to be tested through a probe card; and the FPGA unit generates a corresponding test signal according to the test instruction and transmits the test signal to the target to be tested through the probe card.
S60, the target to be tested receives the test signal and executes the test signal, and the generated feedback information is transmitted to the single chip microcomputer;
the S70 single chip microcomputer transmits the test result to the man-machine interaction module; and the single chip microcomputer generates a corresponding test result according to the feedback information and transmits the test result to the man-machine interaction module.
S80, the human-computer interaction module presents the test result; the man-machine interaction module displays the test result through an LCD display screen for an operator to check.
Furthermore, the test result can be stored in a storage unit of the graphics signal generation module, and the test result in the storage unit can be extracted to other external devices through an I/O interface of the graphics signal generation module as required. An additional external port, such as an ethernet port, can be provided for the test system as needed, so that the system can communicate with other related devices, and the test system can be conveniently matched with a field application environment.
In the above description, technical details of chips, circuit connections, and the like in each module are not described in detail. It will be appreciated by those skilled in the art that modules having the required functionality may be formed by various technical means. In addition, those skilled in the art may also select a chip or circuit connection structure that is not exactly the same as the above description in order to achieve the same purpose. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (12)
1. An integrated circuit test system, comprising:
the probe card is used for connecting with a target to be detected;
the pattern signal generating module is connected with the probe card and used for generating a test signal;
the human-computer interaction module is connected with the graphic signal generation module;
the graphic signal generation module comprises a single chip microcomputer and an FPGA unit, a test instruction is transmitted to the single chip microcomputer through the man-machine interaction module, the single chip microcomputer controls the FPGA unit to generate a corresponding test signal, and the test signal is transmitted to a target to be tested through the probe card.
2. The test system of claim 1, wherein the pattern signal generating module further comprises a clock unit for generating a clock signal and a storage unit for storing the test result and the preset test instruction.
3. The test system of claim 2, wherein the probe card is adapted to be used with a plurality of targets to be tested, and the predetermined test commands include a plurality of commands respectively adapted to be used with the plurality of targets to be tested.
4. The test system of claim 1, wherein the pattern signal generating module further comprises a communication unit, the communication unit comprising a plurality of I/O interfaces for communicating with the probe card, the human-machine interaction module, and an external device, respectively.
5. The test system of claim 4, wherein the communication unit comprises a network port, and the human-computer interaction module is connected with the graphic signal generation module through the network port.
6. The test system according to claim 5, wherein the plurality of network ports are provided, and at least one of the network ports is used for connecting external devices, so that the external devices can obtain the test result.
7. The test system of claim 4, wherein the probe card is connected to the pattern signal generating module by a flex cable.
8. The testing system of claim 1, wherein the human-computer interaction module comprises a display unit and an input unit, the input unit is used for inputting a testing instruction, and the display unit is used for displaying input information, related parameters and a testing result.
9. The test system of claim 1, wherein the graphics signal generation module is integrated with the human-machine interaction module.
10. A method of testing an integrated circuit, the method comprising the steps of:
initializing a graphics signal generation module;
inputting a command prompt corresponding to the test;
the FPGA unit generates a test signal and transmits the test signal into a target to be tested through a probe card;
the target to be tested receives and executes the test signal, and transmits the generated feedback information to the singlechip;
the single chip transmits the test result to the man-machine interaction module for display.
11. The test method according to claim 10, wherein the single chip microcomputer generates a corresponding test instruction according to the command prompt, and transmits the test instruction to the FPGA unit, so that the FPGA unit generates a corresponding test signal.
12. The test method according to claim 10, wherein the pattern signal generating module further comprises a storage unit, the test result is stored in the storage unit, and the test result in the storage unit can be extracted to other external devices through the I/O interface as needed.
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| CN201910998342.XA CN110780184A (en) | 2019-10-21 | 2019-10-21 | Integrated circuit test system and test method |
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| CN201910998342.XA CN110780184A (en) | 2019-10-21 | 2019-10-21 | Integrated circuit test system and test method |
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| CN110780184A true CN110780184A (en) | 2020-02-11 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2565029Y (en) * | 2002-08-15 | 2003-08-06 | 北京自动测试技术研究所 | IC tester with pattern generator based on high-grade microprocessor |
| US20040000922A1 (en) * | 2002-06-28 | 2004-01-01 | Witte Jeffrey Paul | System and method for measuring fault coverage in an integrated circuit |
| CN101029918A (en) * | 2007-01-23 | 2007-09-05 | 北京芯技佳易微电子科技有限公司 | System and method for testing controllable integrated circuit based on programmable device |
| CN101551439A (en) * | 2009-02-24 | 2009-10-07 | 北京时代民芯科技有限公司 | Built-in self-testing method of FPGA input/output module |
| CN103052993A (en) * | 2010-05-28 | 2013-04-17 | 爱德万测试(新加坡)私人有限公司 | Solution for full speed, parallel dut testing |
| CN103064006B (en) * | 2012-12-26 | 2016-09-14 | 中国科学院微电子研究所 | testing device for integrated circuit |
| CN207965053U (en) * | 2018-01-17 | 2018-10-12 | 绍兴快晴贸易有限公司 | It is a kind of based on high-grade microprocessor be pattern generator arrangement for testing integrated circuit |
-
2019
- 2019-10-21 CN CN201910998342.XA patent/CN110780184A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040000922A1 (en) * | 2002-06-28 | 2004-01-01 | Witte Jeffrey Paul | System and method for measuring fault coverage in an integrated circuit |
| CN2565029Y (en) * | 2002-08-15 | 2003-08-06 | 北京自动测试技术研究所 | IC tester with pattern generator based on high-grade microprocessor |
| CN101029918A (en) * | 2007-01-23 | 2007-09-05 | 北京芯技佳易微电子科技有限公司 | System and method for testing controllable integrated circuit based on programmable device |
| CN101551439A (en) * | 2009-02-24 | 2009-10-07 | 北京时代民芯科技有限公司 | Built-in self-testing method of FPGA input/output module |
| CN103052993A (en) * | 2010-05-28 | 2013-04-17 | 爱德万测试(新加坡)私人有限公司 | Solution for full speed, parallel dut testing |
| CN103064006B (en) * | 2012-12-26 | 2016-09-14 | 中国科学院微电子研究所 | testing device for integrated circuit |
| CN207965053U (en) * | 2018-01-17 | 2018-10-12 | 绍兴快晴贸易有限公司 | It is a kind of based on high-grade microprocessor be pattern generator arrangement for testing integrated circuit |
Non-Patent Citations (1)
| Title |
|---|
| 刘大革: "《计算机文化基础》", 30 September 2007, 武汉大学出版社 * |
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