CN110768748B - Convolutional Code Decoder and Convolutional Code Decoding Method - Google Patents

Abstract

The invention discloses a convolution code decoder and a convolution code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention use the predicted information for decoding, so that the signal can be demodulated/decoded more quickly. The early demodulation/decoding of the signal can end the operation state early to achieve the effect of power saving. The convolutional code decoder performs decoding according to a received data and an auxiliary data to obtain a target data, and includes a first error detection data generation circuit, a channel encoding circuit, a first selection circuit, a first Viterbi decoding circuit, A second error detection data generation circuit, a comparison circuit, a second selection circuit and a second Viterbi decoding circuit.

Description

Convolutional Code Decoder and Convolutional Code Decoding Method

technical field

The present invention relates to a wireless communication system, and in particular, to a decoder and a decoding method of the wireless communication system.

Background technique

In Low-Power Wide-Area Network (LPWAN), users pay more and more attention to the requirement of low power consumption. Therefore, how to achieve the effect of coverage extension within limited system resources has been the focus of various industry players in recent years. Under the market trend, the concept of the Internet of Things has gradually matured. A large number of devices need to be connected to the network, and some of the devices require low-volume data transmission with long wait times. In this case, due to the pursuit of characteristics such as low energy consumption, low complexity, low cost, and high coverage, it may be necessary to operate in an environment with poor Signal-to-Noise Ratio (SNR) (for example, in a cell cell edge or basement), so the transmitting end (eg: base station) will help the receiving end to correctly decipher the signal by repeatedly transmitting the signal. In order to effectively improve the accuracy of demodulation, the receiving end must wait long enough to receive these repeatedly transmitted signals. However, this extended operation time will increase the power consumption.

Therefore, how to improve the bit error rate (BER) performance of the receiving end, thereby saving power consumption, reducing costs, and increasing the service life of the battery has become an important issue.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, an object of the present invention is to provide a convolutional code decoder and a convolutional code decoding method.

The invention also discloses a convolutional code decoder, which performs decoding according to a received data and an auxiliary data to obtain a target data. The convolutional code decoder includes a first error detection data generation circuit, a channel encoding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit and a second Viterbi decoding circuit. The first error detection data generating circuit performs an error detection operation on the auxiliary data to obtain error detection data. The channel encoding circuit is coupled to the first error detection data generating circuit, and is used for channel encoding the auxiliary data and the error detection data to obtain an intermediate data. The first selection circuit is coupled to the channel encoding circuit for generating a first data to be decoded according to the received data and the intermediate data. The first Viterbi decoding circuit is coupled to the first selection circuit for decoding the first data to be decoded to obtain intermediate decoded data, wherein the intermediate decoded data includes an estimated data and an intermediate error detection data. The second error detection data generating circuit is coupled to the first Viterbi decoding circuit for performing error detection operations on the estimated data to obtain a reference error detection data. The comparison circuit is coupled to the second error detection data generating circuit and the first Viterbi decoding circuit, and is used for comparing the intermediate error detection data with the reference error detection data. The second selection circuit is coupled to the channel encoding circuit, the second error detection data generation circuit and the comparison circuit, and is used for the received data and the intermediate error detection data according to one of the intermediate error detection data and the reference error detection data, the received data and the intermediate error detection data. The data generates a second data to be decoded. The second Viterbi decoding circuit is coupled to the second selection circuit for decoding the second to-be-decoded data to obtain the target data.

The invention also discloses a convolutional code decoding method, which decodes according to a received data and an auxiliary data to obtain a target data. The convolutional code decoding method includes: performing an error detection operation on the auxiliary data to obtain an error detection data; performing channel coding on the auxiliary data and the error detection data to obtain an intermediate data; and generating a data according to the received data and the intermediate data. the first data to be decoded; decode the first data to be decoded to obtain intermediate decoded data, wherein the intermediate decoded data includes an estimated data and an intermediate error detection data; perform an error detection operation on the estimated data to obtain a reference error detection data; compare the intermediate error detection data and the reference error detection data; generate a second data to be decoded according to one of the intermediate error detection data and the reference error detection data, the received data and the intermediate data; and Decode the second data to be decoded to obtain the target data.

The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predicted information. Compared with the conventional technology, the convolutional code decoder and the convolutional code decoding method of the present invention can demodulate/decode the signal faster. The early demodulation/decoding of the signal can end the operation state early to achieve the effect of power saving.

The features, implementations and technical effects of the present invention are described in detail as follows with reference to the accompanying drawings.

Description of drawings

1 is a schematic diagram of a data modulation and/or coding process and data structure of a wireless communication system;

Fig. 2 is the functional block diagram of the demodulation/decoding apparatus of the wireless communication receiving end of the present invention;

3 is a functional block diagram of an embodiment of a convolutional code decoder of the present invention;

4 is a flowchart of an embodiment of a convolutional code decoding method according to the present invention;

5 is a functional block diagram of another embodiment of the convolutional code decoder of the present invention;

6 is a flowchart of another embodiment of a convolutional code decoding method according to the present invention;

Fig. 7 is the detailed flow chart of step S610 of Fig. 6;

8 is a schematic diagram of a Viterbi algorithm;

FIG. 9 is a functional block diagram of another embodiment of the convolutional code decoder of the present invention; and

FIG. 10 is a flowchart of another embodiment of a convolutional code decoding method according to the present invention.

Symbol Description

210 Channel Estimation

220 Signal detection

230 descrambler

240 De-Rate Matching

250 convolutional code decoder

260 error detection circuit

310, 920 error detection data generation circuit

320-channel encoding circuit

330, 930 selection circuit

340, 510, 940 Viterbi decoding circuit

910, 915 data extraction circuit

950 Comparison Circuit

S410～S440, S610, S710～S760, S1010～S1090 Steps

Detailed ways

The technical terms in the following description refer to the common terms in the technical field. If this specification describes or defines some terms, the interpretation of this part of the terms shall be subject to the descriptions or definitions in this specification.

The present disclosure includes a convolutional code decoder and a convolutional code decoding method. Since some of the elements included in the convolutional code decoder of the present invention may be known elements individually, the details of the known elements will be described below without affecting the full disclosure and practicability of the invention of the device. Omit. In addition, part or all of the flow of the convolutional code decoding method of the present invention may be in the form of software and/or firmware, and may be executed by the convolutional code decoder of the present invention or an equivalent device thereof, without affecting the adequacy of the method and invention. Under the premise of disclosure and practicability, the following description of the method invention will focus on the content of the steps rather than the hardware.

The following description of the Viterbi architecture takes (2, 1, 2) convolutional code encoding and hard decision as an example, however, those skilled in the art will understand the implementation of the present invention after The present invention can be applied to different convolutional codes and soft decisions.

The demodulation and/or decoding mechanism of the receiving end of the present invention is suitable for a communication system based on a general modulation technique, such as a communication system using a convolutional code encoder/decoder. Such communication systems are, for example, Internet of Things (IoT), Machine to Machine (M2M), 802.11ah HaLow, etc. of Wireless Fidelity (Wireless Fidelity, Wi-Fi). The following description takes a NarrowBand Internet of Thing (NB-IoT) receiver as an example, but the present invention is not limited to this communication system.

In network systems, data transmission often needs to transmit duplicate data, or transmit part of the same and part of the unknown data, but all data must be processed together during demodulation, resulting in some unnecessary errors. Unnecessary power consumption. The present invention therefore proposes a mechanism that utilizes known data to assist in demodulation and/or decoding. The source of this known data is that the receiving end predicts the value of certain bits of the current signal through statistics and analysis of the previous transmission data for a long time. For the generation method of this known data, reference may be made to Taiwan Patent Application No. 107104854, but it is not limited thereto.

FIG. 1 is a schematic diagram of a data modulation and/or coding process and a data structure in a wireless communication system. The original data A is a vector with a length (number of bits) of N _A ×1. After adding error detection data (for example, adding a cyclic redundancy check (CRC)) in step S110 Then, it becomes data C (a vector of length N _C × 1). As shown in the figure, in step S110, error detection data _B (redundant bits) with a length of NB is added to the end of the original data _A to form data _C (ie, NC=NA ₊ NB). The error detection data _B of length NB is used to check the correctness of the original data A. In step S120, the data C is subjected to channel coding to combat the channel effect. It is assumed here that the channel coding is a Tail-Biting Convolutional Code (TBCC) with a code rate of 1/3, and data _Z (a vector with a length of 3NC × 1) is generated after coding. Finally, in step S130, the data Z undergoes rate matching and/or scrambling to evenly distribute the data to all available resource elements (REs) to form a post-modulation/encoding process. The to-be-transmitted data Y (a vector of length N _RM × 1 ).

Since the CRC-based error detection data B is related to any bit of the original data A, when an unknown bit of the original data A appears at the gray mark, the error detection of the last N _B bits of the data C Data B are all classified as unknown bits (again marked in grey). Next, the characteristics of the convolutional code will increase the number of unknown bits in the data Z, and the number of the unknown bits is related to the code rate and the constraint length of the convolutional code. Rate matching and scrambling will not affect the ratio of the unknown bits to the number of known bits, but only affect the position of the unknown bits in the data Y to be transmitted.

估测数据

经过解扰器(descrambler)230与解速率匹配240 后，可得接收数据

(长度为N_TB＝3N_C×1的向量)。回旋码解码器250参考 辅助数据A'解码接收数据

后输出目标数据

目标数据

为数据C的估测。 目标数据

包含估测数据

及中间误差检测数据

估测数据

为原始数据 A的估测。误差检测电路260根据中间误差检测数据

来验证估测数据

是 否为合法的码字。误差检测电路260的验证结果正确代表估测数据

等于原 始数据A。FIG. 2 is a functional block diagram of the demodulation/decoding apparatus of the wireless communication receiving end according to the present invention. After the received signal SR is subjected to the channel estimation 210, the channel effect can be compensated, and the repetition property between different subframes can be used for combining to improve the signal-to-noise ratio. The main function of signal detection 220 is demodulation. Next, after arranging all resource units of a Narrowband Physical Downlink Shared Channel (NPDSCH), an estimated data can be obtained.

estimated data

After descrambler (descrambler) 230 and descrambler rate matching 240, the received data can be obtained

(Vector of length _{N TB} = 3NC x 1). The convolutional code decoder 250 decodes the received data with reference to the auxiliary data A'

output target data

target data

is an estimate of data C. target data

Contains estimated data

and intermediate error detection data

estimated data

is an estimate of the original data A. The error detection circuit 260 detects the data based on the intermediate error

to verify the estimated data

Whether it is a valid codeword. The verification result of the error detection circuit 260 correctly represents the estimated data

is equal to the original data A.

的长度亦实质上相同。辅助数据A'中至少有一位元为已知(经 预测)，而其他的位元为未知(未经预测)。当辅助数据A'中的所有位元皆为 已知时，误差检测数据B'及中间数据Z'的所有位元亦皆为已知。当辅助数据 A'中有未知的位元时，误差检测数据B'的所有位元皆为未知，而中间数据Z' 的位元则为部分已知且部分未知。接下来选择电路330根据接收数据

及中 间数据Z'产生待解码数据E(步骤S430)。控制信号Prek指示目前输入选 择电路330的中间数据Z'为已知的位元或未知的位元。步骤S430包含子步 骤S435：选择电路330根据控制信号Prek以中间数据Z'的已知位元取代接 收数据

的相对应位元以产生待解码数据E。也就是说，经过选择电路330 后，接收数据

的部分位元(对应中间数据Z'已知的部分)被中间数据Z'中 相对应的位元取代，而其他位元(对应中间数据Z'未知的部分)则保留原数 值。在一些实施例中，当待解码数据E为软数值(soft value)时，选择电路 330及步骤S435还包含将已知位元转换成极值(extremum)。最后维特比解 码电路340利用维特比解码运算解码待解码数据E以得到目标数据

(步骤 S440)。选择电路330可用多工器实作。When performing convolutional code decoding, a Viterbi architecture is generally used. FIG. 3 is a functional block diagram of an embodiment of a convolutional code decoder of the present invention. FIG. 4 is a flowchart of an embodiment of a convolutional code decoding method according to the present invention. The convolutional code decoder 250 includes an error detection data generation circuit 310 , a channel encoding circuit 320 , a selection circuit 330 and a Viterbi decoding circuit 340 . First, the error detection data generation circuit 310 performs an error detection operation on the auxiliary data A' to generate error detection data B' (step S410). For example, the error detection data generating circuit 310 may perform a cyclic redundancy check operation on the auxiliary data A' to generate the error detection data B'. For the narrowband Internet of Things, the error detection data B' can be a 24-bit CRC code. Next, the channel coding circuit 320 performs channel coding on the auxiliary data A' and the error detection data B' to obtain the intermediate data Z' (step S420). The channel encoding circuit 320 performs channel encoding with the same encoding scheme as the transmitting end, such as convolutional code encoding. The auxiliary data A' is the prediction data of the original data A, which means that the auxiliary data A' and the original data A have substantially the same length, and the auxiliary data A' includes all or part of the original data A. That is, when the prediction is correct, the known bits (ie, predicted bits) of the auxiliary data A' are the same as the bits corresponding to the original data A'. Since the auxiliary data A' has substantially the same length as the original data A, the length of the intermediate data Z' is the same as that of the received data

are also substantially the same length. At least one bit of the auxiliary data A' is known (predicted), and the other bits are unknown (unpredicted). When all the bits in the auxiliary data A' are known, all the bits of the error detection data B' and the intermediate data Z' are also known. When there are unknown bits in the auxiliary data A', all the bits of the error detection data B' are unknown, and the bits of the intermediate data Z' are partially known and partially unknown. Next, the selection circuit 330 according to the received data

and intermediate data Z' to generate data E to be decoded (step S430). The control signal Prek indicates that the intermediate data Z' currently input to the selection circuit 330 is a known bit or an unknown bit. Step S430 includes sub-step S435: the selection circuit 330 replaces the received data with the known bits of the intermediate data Z' according to the control signal Prek

to generate the data E to be decoded. That is, after passing through the selection circuit 330, data is received

Part of the bits (corresponding to the known part of the intermediate data Z') are replaced by the corresponding bits in the intermediate data Z', while other bits (corresponding to the unknown part of the intermediate data Z') keep the original value. In some embodiments, when the data E to be decoded is a soft value, the selection circuit 330 and step S435 further include converting the known bits into extremums. Finally, the Viterbi decoding circuit 340 uses the Viterbi decoding operation to decode the data E to be decoded to obtain the target data

(step S440). Selection circuit 330 may be implemented with a multiplexer.

的全部数 据皆为未知，亦即无法确定接收数据

的位元值是否正确)，所以维特比解码 电路340可以更准确地解码出目标数据

因此，本发明的回旋码解码器250 的效能可以获得提升，有助于缩短无线通信系统的接收端的解调制和/或解码 时间，以节省无线装置的耗电量。Because part of the data E to be decoded is known (for comparison, the received data

All data for is unknown, i.e. it is not possible to determine receipt

Is the bit value of ? is correct), so the Viterbi decoding circuit 340 can decode the target data more accurately

Therefore, the performance of the convolutional code decoder 250 of the present invention can be improved, which helps to shorten the demodulation and/or decoding time of the receiving end of the wireless communication system, so as to save the power consumption of the wireless device.

(步骤S610)。图3的维特比解码电路340是对维特比 演算法中的所有分支(branch)进行计算和判断，然而图5的维特比解码电 路510是在预知位元的情况下，预先排除确定错误的分支，因此可以得到优 选的效能。FIG. 5 is a functional block diagram of another embodiment of the convolutional code decoder of the present invention. FIG. 6 is a flowchart of another embodiment of a convolutional code decoding method according to the present invention. The convolutional code decoder 250 includes an error detection data generation circuit 310 , a channel encoding circuit 320 , a selection circuit 330 and a Viterbi decoding circuit 510 . The error detection data generation circuit 310 , the channel encoding circuit 320 , the selection circuit 330 in FIG. 5 and the steps S410 - S435 in FIG. 6 have been described in detail in the disclosure of FIG. 3 and FIG. 4 , so they will not be repeated. The Viterbi decoding circuit 510 of this embodiment performs a Viterbi decoding operation on the data E to be decoded with reference to the auxiliary data A' to obtain the target data

(step S610). The Viterbi decoding circuit 340 in FIG. 3 calculates and judges all the branches in the Viterbi algorithm, while the Viterbi decoding circuit 510 in FIG. 5 excludes the branch that determines the error in advance in the case of predicting the bits , so the optimal performance can be obtained.

FIG. 7 is a detailed flowchart of step S610. FIG. 8 is a schematic diagram of the Viterbi algorithm. Fig. 8 takes the decoding of the convolutional code of (2, 1, 2) as an example, but the present invention is not limited to this. As shown in FIG. 8 , the Viterbi decoding circuit 510 processes at each stage (t=0, 1, 2, ..., k-1, k, k+1, ..., k is a positive integer, t=0 is the initial stage) Four states: S ₀₀ , S ₀₁ , S ₁₀ , S ₁₁ . When the Viterbi decoding circuit 510 processes the target state of a certain stage (eg, the state S ₀₁ of the processing stage k), it will first find two branches connected to the target state (that is, the two branches b0 that enter the target state S ₀₁ ). and b1), and determine whether the previously accumulated metric (previously accumulated metric) m _prev corresponding to each branch is the preset value m _preset (step S710 ). Each branch has a current process metric (current metric), and the calculation method of the current process metric is well known to those skilled in the art, so it will not be repeated here. The accumulated metric m _accum,0 corresponding to the branch b0 and the accumulated metric m _accum,1 corresponding to the branch b1 can be obtained by the following equations (1) and (2), respectively.

m _accum,0 =m _prev,0 +m _cur,0 (1)

m _accum,1 =m _prev,1 +m _cur,1 (2)

Wherein m _cur,0 and m _cur,1 are the current process metrics corresponding to the branch b0 and the branch b1, respectively, and m _prev,0 and m _prev,1 are the pre-accumulated metrics corresponding to the branch b0 and the branch b1, respectively.

The preset value m _preset is related to how the Viterbi decoding circuit 510 decides the branch (step S760). In step S760, the Viterbi decoding circuit 510 selects one of the two branches of the target state as the survivor path, and records the source of this branch (for example, represented by a bit 0 or a bit 1), and finally Update the cumulative metric to the preceding cumulative metric for the next stage. If the preset value m _preset is a maximum value (for example, +2 ^N-1 , N is the number of bits of the preset value m _preset ), the Viterbi decoding circuit 510 selects the branch corresponding to the smaller cumulative metric in step S760 On the contrary, if the preset value m _preset is a minimum value (for example, -2 ^N-1 ), the Viterbi decoding circuit 510 selects the branch with a larger corresponding accumulated metric in step S760.

As shown in FIG. 8 , if m _prev,0 or m _prev,1 is equal to the preset value m _preset (that is, step S710 is Yes), it means that the corresponding branch b0 or b1 will not be selected, so the Viterbi decoding circuit 510 Further set the accumulated metric (ie m _accum,0 or m _accum,1 ) corresponding to the target branch (the target branch is one of all branches b0 and b1 in the target state) as the preset value m _preset ( Step S715), and then decide to branch (step S760). If there is only one branch equal to the above preset value m _preset , the Viterbi decoding circuit 510 will select another branch in step S760; if the accumulated metrics corresponding to the two branches are equal, the Viterbi decoding circuit 510 can select any branch in step S760. a branch.

When step S710 is NO, the flow goes to step S720. Step S720 determines whether the information bits of the auxiliary data A' are known. For example, assuming that the auxiliary data A' has multiple information bits (A' ₀ , A' ₁ , A' ₂ ,..., A' _k-1 , A' _k , A' _k+1 ,...), branch Whether b0 and branch b1 are likely to be selected is closely related to the value of the information bit A' _k-1 .

When the information bit A'k _-1 is unknown (No in step S720), the Viterbi decoding circuit 510 calculates the current process metric of each branch (step S740), and then calculates the cumulative metric according to the formula (1) and the formula (2). (step S750), and then decide to branch (step S760). After step S760 ends, the Viterbi decoding circuit 510 executes the flow of FIG. 7 again to process the unprocessed state of the same stage, or to proceed to the next stage.

When the information bit A' _k-1 is known (Yes in step S720), the Viterbi decoding circuit 510 determines whether the target state is a candidate state (step S730). Assuming that the dotted line branch in FIG. 8 corresponds to the logic value 0 and the solid line branch corresponds to the logic value 1, then when the information bit A′ _k-1 is the logic value ₀ , the states S00 and _S01 are candidate states (Yes in step S730 ) , because the current target state is the state S ₀₁ ), and when the information bit A′ _k-1 is the logical value 1, the states S ₁₀ and S ₁₁ are candidate states (No in step S730 because the current target state is the state S ₀₁ ). That is, the Viterbi decoding circuit 510 can exclude half of the states in a certain stage according to the value of the information bit of the auxiliary data A'.

When the target state is a candidate state (Yes in step S730), the Viterbi decoding circuit 510 executes steps S740-S760; when the target state is not a candidate state (No in step S730), the Viterbi decoding circuit 510 executes step S715 . More specifically, when the Viterbi decoding circuit 510 determines that the target state will not be selected (ie, the target state is not a candidate state), the Viterbi decoding circuit 510 will correspond to the target branch (at this time, the target branch is all branches b0 and b0 of the target state). The accumulated metric of b1) is set to a preset value m _preset (step S715), and then in step S760 the Viterbi decoding circuit 510 can select branch b0 or b1 as the branch of the target state S ₀₁ of state k. Regardless of whether the Viterbi decoding circuit 510 selects the branch b0 or b1 in step S760, because the cumulative metrics of all branches of the target state S ₀₁ have been set to the preset value m _preset , the final Viterbi algorithm will not choose to include the state S ₀₁ (that is, the two branches b0 and b1 of this state _S01 can be regarded as having been excluded).

In the embodiments of FIGS. 5-7 , the Viterbi decoding circuit 510 performs decoding with reference to the auxiliary data A'. When the information bits of the auxiliary data A' are known, the Viterbi decoding circuit 510 has the opportunity (depending on whether the target state is a candidate state) to directly set the cumulative metrics of all branches of the target state as a preset according to the information bits The value m _preset (ie, step S715 is executed) to reduce the amount of calculation (ie, steps S740 to S760 are skipped). For comparison, the Viterbi decoding circuit 340 of FIG. 3 needs to perform steps S740 - S760 for each state. Because steps S710 , S715 , S720 and S730 of FIG. 7 are operations to perform simple discrimination or setting values, the complexity of the convolutional code decoder 250 of FIG. 5 is similar to that of the convolutional code decoder 250 of FIG. 3 . Compared with the embodiments of FIGS. 3 to 4 , the embodiments of FIGS. 5 to 7 can further improve the performance of the convolutional code decoder 250 to further shorten the demodulation and/or decoding time at the receiving end of the wireless communication system.

包含估测数据

及中间误差检测数据

中间误差检测数据

可以用来验 证估测数据

是否为合法的码字。数据抽取电路910及数据抽取电路915分 别从中间解码数据

中取出估测数据

及中间误差检测数据

(步骤S1050)。 因为中间误差检测数据

具有预设的长度且添加于估测数据

的尾端，所以 数据抽取电路910及数据抽取电路915可以简单地通过分割中间解码数据

即可完成步骤S1050。FIG. 9 is a functional block diagram of another embodiment of the convolutional code decoder of the present invention. FIG. 10 is a flowchart of another embodiment of a convolutional code decoding method according to the present invention. The convolutional code decoder 250 includes an error detection data generation circuit 310, a channel encoding circuit 320, a selection circuit 330, a Viterbi decoding circuit 340, a data extraction circuit 910, a data extraction circuit 915, an error detection data generation circuit 920, a selection circuit 930, and a Viterbi decoding circuit 910. than the decoding circuit 940 and the comparison circuit 950 . The error detection data generation circuit 310, the channel encoding circuit 320, the selection circuit 330 and the Viterbi decoding circuit 340 execute steps S1010, S1020, S1030 and S1040 respectively; the details of the components and the steps are shown in FIGS. 3 and 4 . It has been described in the embodiment, so it will not be repeated. Intermediate decoded data generated by the Viterbi decoding circuit 340

Contains estimated data

and intermediate error detection data

Intermediate error detection data

Can be used to verify estimated data

Whether it is a valid codeword. The data extraction circuit 910 and the data extraction circuit 915 decode the data from the intermediate

extract the estimated data

and intermediate error detection data

(step S1050). Because of the intermediate error detection data

Has a preset length and is added to the estimated data

, so the data extraction circuit 910 and the data extraction circuit 915 can simply divide the intermediate decoded data by dividing

Step S1050 can be completed.

相比，中间误差检测数据

的误码率较高。也就是说，可以利用估测数据

的较高的正确性来帮助误差 检测数据的解码。所以接下来误差检测数据产生电路920对估测数据

进行 误差检测运算以产生参考误差检测数据

(步骤S1060)。误差检测数据产 生电路920的功能与误差检测数据产生电路310相同，故不再赘述。由于参 考误差检测数据

是根据估测数据

重建(rebuild)所得，所以一般而言参 考误差检测数据

的正确率比中间误差检测数据

高。参考误差检测数 据

与中间误差检测数据

具有相同的位元数。Since the bits corresponding to the error detection data in the first to-be-decoded data E are unknown bits (unless all the bits of the auxiliary data A' are known), and are continuously distributed, the Viterbi architecture does not Errors are less resistant to errors, so with estimated data

compared to the intermediate error detection data

The bit error rate is higher. That is, the estimated data can be used

higher correctness to help the decoding of error detection data. Therefore, the error detection data generating circuit 920 then performs the estimation data

Perform error detection operations to generate reference error detection data

(step S1060). The function of the error detection data generation circuit 920 is the same as that of the error detection data generation circuit 310 , and thus will not be repeated here. Due to reference error detection data

based on estimates

Rebuild (rebuild), so generally refer to error detection data

The correct rate is higher than the intermediate error detection data

high. Reference error detection data

with intermediate error detection data

have the same number of bits.

及中间误差检测数据

并 且产生控制信号Ctrl。在一个实施例中，控制信号Ctrl的位元数与参考误差 检测数据

及中间误差检测数据

的位元数相同，而比较电路950可以 将参考误差检测数据

及中间误差检测数据

相同数值的位元设定成已 知的信息位元(例如将控制信号Ctrl中对应的位元设为逻辑值1)，以及将不 同数值的位元设定成未知的信息位元(例如将控制信号Ctrl中对应的位元设 为逻辑值0)(步骤S1070)。当参考误差检测数据

与中间误差检测数据

的相异的位元数小于某个阈值时(例如控制信号Ctrl中逻辑值为0的位元数 小于该阈值)，代表维特比解码电路340解码中间误差检测数据

时可能因 为噪声而产生了错误，因此接下来选择电路930参考控制信号Ctrl及控制信 号Prek，并根据中间误差检测数据

与参考误差检测数据

的其中之一、 接收数据

及中间数据Z'产生第二待解码数据E'(步骤S1080)。而当参考误 差检测数据

与中间误差检测数据

的相异的位元数不小于该阈值时(例如控制信号Ctrl中逻辑值为0的位元数不小于该阈值)，选择电路930 仅根据接收数据

及中间数据Z'产生第二待解码数据E'。The comparison circuit 950 compares the reference error detection data

and intermediate error detection data

And the control signal Ctrl is generated. In one embodiment, the number of bits of the control signal Ctrl is related to the reference error detection data

and intermediate error detection data

The number of bits is the same, and the comparison circuit 950 can compare the reference error detection data

and intermediate error detection data

Bits with the same value are set as known information bits (for example, setting the corresponding bit in the control signal Ctrl to logic value 1), and bits with different values are set as unknown information bits (for example, setting the corresponding bit in the control signal Ctrl to logic value 1) The corresponding bit in the control signal Ctrl is set to logic value 0) (step S1070). When referencing error detection data

with intermediate error detection data

When the number of different bits of , is less than a certain threshold (for example, the number of bits with a logic value of 0 in the control signal Ctrl is less than the threshold), it means that the Viterbi decoding circuit 340 decodes the intermediate error detection data

Errors may occur due to noise, so the selection circuit 930 refers to the control signal Ctrl and the control signal Prek, and detects the data according to the intermediate error

Error detection data with reference

One of them, receive data

and the intermediate data Z' to generate the second to-be-decoded data E' (step S1080). And when the reference error detection data

with intermediate error detection data

When the number of different bits is not less than the threshold (for example, the number of bits whose logic value is 0 in the control signal Ctrl is not less than the threshold), the selection circuit 930 only selects the received data according to the received data.

and the intermediate data Z' to generate the second to-be-decoded data E'.

具有相同的位元数。控制信号Prek以逻辑值1代表中间数据Z'中对应的 位元为已知，以逻辑值0代表中间数据Z'中对应的位元为未知。控制信号Ctrl 以逻辑值1代表中间误差检测数据

及参考误差检测数据

中对应的位 元为已知，以逻辑值0代表中间误差检测数据

及参考误差检测数据

中 对应的位元为未知。更明确地说，根据控制信号Prek及控制信号Ctrl的内容 (例如根据两者的逐位元(bitwise)或运算(OR operation)的结果)，对接 收数据

中对应误差检测数据的位元而言，选择电路930以中间误差检测数 据

及参考误差检测数据

的相同位元取代接收数据

的相对应位元；对 接收数据

中非对应误差检测数据的位元而言，选择电路930以中间数据Z' 的已知位元取代接收数据

的相对应位元。最后选择电路930产生第二待解 码数据E'。换句话说，如果控制信号Ctrl和/或控制信号Prek指示接收数据

的 部分位元为已知，则选择电路930以已知的数值0或1取代接收数据

中的 相对应位元；如果控制信号Ctrl和/或控制信号Prek指示接收数据

的部分位 元为未知，则选择电路930选择接收数据

的数值。In some embodiments, the control signal Prek, the control signal Ctrl, the intermediate data Z' and the received data

have the same number of bits. In the control signal Prek, a logic value of 1 indicates that the corresponding bit in the intermediate data Z' is known, and a logic value of 0 indicates that the corresponding bit in the intermediate data Z' is unknown. The control signal Ctrl represents the intermediate error detection data with a logic value of 1

and reference error detection data

The corresponding bits in are known, and the logic value 0 represents the intermediate error detection data

and reference error detection data

The corresponding bit in is unknown. More specifically, according to the content of the control signal Prek and the control signal Ctrl (for example, according to the result of a bitwise OR operation of the two), the received data is

For the bits corresponding to the error detection data in the middle, the selection circuit 930 uses the middle error detection data

and reference error detection data

The same bits of the received data are replaced

The corresponding bit of the received data;

For the bits that do not correspond to the error detection data, the selection circuit 930 replaces the received data with the known bits of the intermediate data Z'

the corresponding bits of . Finally, the selection circuit 930 generates the second data E' to be decoded. In other words, if the control signal Ctrl and/or the control signal Prek indicate to receive data

If some of the bits are known, the selection circuit 930 replaces the received data with the known value 0 or 1

The corresponding bit in

part of the bits is unknown, then the selection circuit 930 selects the received data

value of .

(步骤S1090)。选择电路930可用多工器实作。请注意，在其他的实施例中 可采用分时的技术，使得图9的回旋码解码器250可以只使用一个误差检测 数据产生电路、一个选择电路及一个维特比解码电路。Finally, the Viterbi decoding circuit 940 decodes the second to-be-decoded data E' to obtain target data

(step S1090). Selection circuit 930 may be implemented with a multiplexer. Please note that in other embodiments, a time-sharing technique can be used, so that the convolutional code decoder 250 in FIG. 9 can only use one error detection data generation circuit, one selection circuit and one Viterbi decoding circuit.

具有较高的正确率，所以图9及图10 的实施例可以利用此特征减少待解码数据中的连续错误位元。因此，维特比 演算法的解码效能可以获得提升，有助于缩短无线通信系统的接收端的解调 制和/或解码时间。Because of the reconstructed reference error detection data

It has a higher accuracy rate, so the embodiments of FIG. 9 and FIG. 10 can use this feature to reduce consecutive erroneous bits in the data to be decoded. Therefore, the decoding performance of the Viterbi algorithm can be improved, which helps to shorten the demodulation and/or decoding time of the receiving end of the wireless communication system.

The aforementioned circuits (namely, the functional blocks of Fig. 3, Fig. 5 and Fig. 9) can also be implemented by a digital signal processor (DSP). In this case, the digital signal processor implements the functions of the aforementioned circuits with a plurality of functional modules, and the digital signal processor performs the functions of the functional modules by executing the program codes or program instructions stored in the storage memory. The present invention may also be a combination of hardware and software/firmware.

Since those skilled in the art can understand the implementation details and changes of the method invention of the present disclosure through the disclosure of the device invention of the present disclosure, in order to avoid redundant repetition, the disclosure requirements and practicability of the method invention are not affected. On the premise, repeated descriptions are omitted here. Please note that the shapes, sizes, ratios and steps of the components in the preceding figures are only for illustration, and are for those skilled in the art to understand the present invention, and are not intended to limit the present invention. Furthermore, although the narrow-band Internet of Things is used as an example in the foregoing embodiments, this is not a limitation of the present invention, and those skilled in the art can appropriately apply the present invention to other types of communication systems according to the disclosure of the present invention.

Although the embodiments of the present invention are described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention. Changes may all belong to the scope of patent protection sought by the present invention, in other words, the scope of patent protection of the present invention shall be determined by the claims in this specification.

Claims (8)

1. A convolutional code decoder for decoding according to a received data and an auxiliary data to obtain a target data, the convolutional code decoder comprising:

a first error detection data generation circuit for performing error detection operation on the auxiliary data to obtain an error detection data;

a channel coding circuit coupled to the first error detection data generating circuit for performing channel coding on the auxiliary data and the error detection data to obtain an intermediate data;

a first selection circuit, coupled to the channel coding circuit, for generating a first data to be decoded according to the received data and the intermediate data;

a first viterbi decoding circuit, coupled to the first selection circuit, for decoding the first data to be decoded to obtain an intermediate decoded data, wherein the intermediate decoded data includes an estimated data and an intermediate error detection data;

a second error detection data generating circuit coupled to the first Viterbi decoding circuit for performing error detection operation on the estimated data to obtain a reference error detection data;

a comparison circuit coupled to the second error detection data generation circuit and the first Viterbi decoding circuit for comparing the intermediate error detection data with the reference error detection data;

a second selection circuit, coupled to the channel coding circuit, the second error detection data generation circuit and the comparison circuit, for generating a second data to be decoded according to one of the intermediate error detection data and the reference error detection data, the received data and the intermediate data; and

a second viterbi decoding circuit, coupled to the second selection circuit, for decoding the second data to be decoded to obtain the target data, wherein the error detection data is a first error detection data, the received data is a data obtained by performing convolutional coding on an original data and a second error detection data, the second error detection data is used for checking the correctness of the original data, and a plurality of known bits of the auxiliary data are the same as corresponding bits of the original data.

2. The convolutional code decoder of claim 1, wherein the length of the intermediate data is the same as the length of the received data.

3. The convolutional code decoder of claim 1, wherein the intermediate data comprises a plurality of known bits, and the first selection circuit replaces corresponding bits of the received data with the known bits to generate the first data to be decoded.

4. The convolutional code decoder of claim 1, wherein the middle error detection data and the reference error detection data have the same number of bits, and when the number of bits of the middle error detection data and the reference error detection data different from each other is less than a predetermined value, the second selection circuit replaces the corresponding bits of the received data with bits of the same value of the middle error detection data and the reference error detection data to generate the second data to be decoded.

5. A convolutional code decoding method for decoding according to a received data and an auxiliary data to obtain a target data, the convolutional code decoding method comprising:

performing error detection operation on the auxiliary data to obtain error detection data;

performing channel coding on the auxiliary data and the error detection data to obtain intermediate data;

generating a first data to be decoded according to the received data and the intermediate data;

decoding the first data to be decoded to obtain intermediate decoded data, wherein the intermediate decoded data comprises estimation data and intermediate error detection data;

performing error detection operation on the estimated data to obtain reference error detection data;

comparing the intermediate error detection data with the reference error detection data;

generating second data to be decoded according to the received data, the intermediate data and one of the intermediate error detection data and the reference error detection data; and

decoding the second data to be decoded to obtain the target data, wherein the error detection data is a first error detection data, the received data is a data obtained by performing convolutional coding on an original data and a second error detection data, the second error detection data is used for checking the correctness of the original data, and a plurality of known bits of the auxiliary data are the same as corresponding bits of the original data.

6. The convolutional code decoding method of claim 5, wherein the length of the intermediate data is the same as the length of the received data.

7. The convolutional code decoding method of claim 5, wherein the intermediate data comprises a plurality of known bits, and the step of generating the first data to be decoded according to the received data and the intermediate data replaces corresponding bits of the received data with the known bits to generate the first data to be decoded.

8. The convolutional code decoding method of claim 5, wherein the middle error detection data and the reference error detection data have the same number of bits, and when the number of bits of the middle error detection data and the reference error detection data different from each other is less than a predetermined value, the step of generating the second data to be decoded replaces the corresponding bits of the received data with the same number of bits of the middle error detection data and the reference error detection data to generate the second data to be decoded.

Images