CN110767602B - Contact hole forming method - Google Patents
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- CN110767602B CN110767602B CN201910986189.9A CN201910986189A CN110767602B CN 110767602 B CN110767602 B CN 110767602B CN 201910986189 A CN201910986189 A CN 201910986189A CN 110767602 B CN110767602 B CN 110767602B
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- 239000010410 layer Substances 0.000 claims abstract description 92
- 239000011229 interlayer Substances 0.000 claims abstract description 87
- 238000005530 etching Methods 0.000 claims abstract description 52
- 238000001259 photo etching Methods 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000001459 lithography Methods 0.000 claims description 13
- 238000010586 diagram Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- G—PHYSICS
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70058—Mask illumination systems
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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Abstract
The invention relates toAnd a contact hole forming method, which relates to the semiconductor integrated circuit manufacturing technology, and obtains a relational expression of the shape critical dimension change Delta D1 of the contact hole after photoetching and the critical dimension change Delta D2 of the contact hole after etching and the thickness H of an interlayer dielectric layer through a plurality of testsILDAnd the critical dimension D2 of the contact hole after etching, thereby obtaining the critical dimension D1 of the contact hole morphology and the thickness H of the interlayer dielectric layer after photoetchingILDAccording to the relationship between the contact hole feature critical dimension D1 after photoetching and the exposure strength of the photoetching machine, the compensation relationship between the exposure strength and the interlayer dielectric layer thickness HILD is obtained, the exposure strength of an exposure unit on the wafer is further compensated, namely, the contact hole with the contact hole feature critical dimension D1 after different photoetching in the interlayer dielectric layer thickness area is exposed, and finally the critical dimension of the contact hole formed after etching in the exposure unit is close to the target critical dimension of the contact hole.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing technology, and more particularly, to a contact hole forming method.
Background
In semiconductor integrated circuit fabrication technology, the HKMG process is a common process for forming semiconductor devices. The HKMG requires the simultaneous formation of a high dielectric constant (HK) gate dielectric layer and the formation of a Metal Gate (MG), such as a 28nm HKMG.
In the semiconductor integrated circuit manufacturing technology, a grid electrode, a source electrode and a drain electrode of a semiconductor device are formed after the HKMG process is completed, and then the grid electrode, the source electrode and the drain electrode of the semiconductor device are led out by a contact hole process. Referring to fig. 1, fig. 1 is a schematic view illustrating one of the manufacturing processes of a semiconductor device, as shown in fig. 1, after electrodes (gate, source, and drain) 110 are formed on a semiconductor substrate, contact holes 120 are formed through a contact hole process to lead out the electrodes 110. Typically, the contact hole 120 is formed in an interlayer dielectric layer (ILD)130, the ILD 130 serves as a dielectric material between each metal layer and between the first metal layer and silicon in the semiconductor integrated circuit, a contact hole feature is first formed in the ILD 130 through a photolithography process, then the contact hole 120 is formed through an etching process, and a metal (such as tungsten, which is called a tungsten plug) is filled in the contact hole to provide an electrical path between adjacent metal layers. The Critical Dimension (CD) of the contact hole 120 and whether it is open directly affect the yield of the semiconductor device.
In the contact hole process, etching programs in a photoetching process and an etching process are generally fixed, the thickness of an interlayer dielectric layer is an important factor influencing the performance of the contact hole, and the sizes of the contact holes formed in different interlayer dielectric layer thickness areas on the same wafer after the etching process are different, so that the critical size of part of the contact holes deviates from the target critical size, and the electrical performance and the yield of a semiconductor device are influenced.
Disclosure of Invention
The invention aims to provide a contact hole forming method, so that the critical dimension of a contact hole formed after etching in an exposure unit is close to the target critical dimension of the contact hole.
The contact hole forming method provided by the invention comprises the following steps: s1: obtaining a relational expression of the change delta D1 of the feature critical dimension of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching; s2: obtaining the thickness H of the interlayer dielectric layerILDAnd the critical dimension D2 of the etched contact hole; s3: according to the relational expression of the change delta D1 of the feature critical dimension of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching obtained in the step S1 and the thickness H of the interlayer dielectric layer obtained in the step S2ILDObtaining the shape critical dimension D1 of the contact hole after photoetching and the thickness H of the interlayer dielectric layer according to a relational expression of the shape critical dimension D2 of the contact hole after photoetching and the critical dimension D2 of the contact hole after etchingILDThe relationship of (1); s4: obtaining the exposure intensity and the thickness H of the interlayer dielectric layer according to the relationship between the critical dimension D1 of the contact hole morphology after photoetching by the photoetching machine and the exposure intensityILDA compensation relationship therebetween; and S5: providing a wafer, forming an interlayer dielectric layer on the wafer substrate, wherein the thickness of the interlayer dielectric layer is not consistent in the wafer surface, detecting to obtain an interlayer dielectric layer thickness distribution diagram in the wafer surface, and obtaining the exposure intensity and the interlayer dielectric layer thickness H according to the step S4ILDThe compensation relationship between the two contact holes compensates the exposure intensity of an exposure unit on the wafer to obtain the shape of the contact hole after photoetching in the exposure unit, so that the key size of the contact hole formed after etching in the exposure unit is close to the target key size of the contact hole.
Further, in step S1, under the condition of the same interlayer dielectric layer thickness, the critical dimension D1 of the contact hole feature formed under different lithography conditions and the critical dimension D2 of the contact hole formed by using the same etching process under each lithography condition are obtained, and the relational expression between the critical dimension change Δ D1 of the contact hole feature after lithography and the critical dimension change Δ D2 of the contact hole after etching is obtained according to the critical dimension D1 of the contact hole features and the critical dimension D2 of the contact holes.
Furthermore, the relation between the change Δ D1 in the feature critical dimension of the contact hole after the lithography and the change Δ D2 in the critical dimension of the contact hole after the etching is Δ D2 ═ k1 Δ D1, and k1 is a coefficient obtained by fitting according to multiple tests.
Further, k1 can vary anywhere between 1 and 1.5.
Furthermore, in step S2, different thicknesses H of the interlayer dielectric layer are obtained under the same photolithography conditionILDThe critical dimension D2 of the etched contact hole formed by the next etching process is determined according to the thickness H of the multiple interlayer dielectric layersILDObtaining the thickness H of the interlayer dielectric layer corresponding to the critical dimension D2 of the contact holesILDAnd the post-etch contact hole critical dimension D2.
Further, the thickness H of the interlayer dielectric layerILDThe relation between the critical dimension D2 of the contact hole after etching is D2 ═ k2HILDAnd k2 is a coefficient obtained by fitting a plurality of tests.
Further, k2 can vary anywhere from-0.5 to-0.08.
Further, the exposure intensity is compensated in step S5 by no more than 15% of the standard exposure intensity of the lithography machine.
Further, there is a deviation of the 15%.
Further, the deviation is within 20%.
Further, the deviation is within 10%.
Further, the deviation is within 5%.
Furthermore, the interlayer dielectric layer is made of SiO2 or SiCO material.
Further, the contact hole forming method is suitable for the contact hole forming process in the semiconductor device formed by the HKMG process.
Further, the semiconductor device formed by the HKMG process includes a gate electrode, a source electrode, and a drain electrode, which are led out respectively according to the contact holes formed by the contact hole forming method.
Further, the contact hole forming method is suitable for the contact hole forming process in the semiconductor device formed by the 28HKMG process.
Further, tungsten metal is filled in the contact hole.
According to the contact hole forming method provided by the invention, the relational expression of the feature critical dimension change delta D1 of the contact hole after photoetching and the critical dimension change delta D2 of the contact hole after etching and the thickness H of the interlayer dielectric layer are obtained through multiple testsILDAnd the critical dimension D2 of the contact hole after etching, thereby obtaining the critical dimension D1 of the contact hole morphology and the thickness H of the interlayer dielectric layer after photoetchingILDAccording to the relationship between the contact hole feature critical dimension D1 after photoetching and the exposure strength of the photoetching machine, the compensation relationship between the exposure strength and the interlayer dielectric layer thickness HILD is obtained, the exposure strength of an exposure unit on the wafer is further compensated, namely, the contact hole with the contact hole feature critical dimension D1 after different photoetching in the interlayer dielectric layer thickness area is exposed, and finally the critical dimension of the contact hole formed after etching in the exposure unit is close to the target critical dimension of the contact hole.
Drawings
Fig. 1 is a schematic diagram of one of the semiconductor device fabrication processes.
FIG. 2 is a schematic diagram showing the effect of the thickness of an interlayer dielectric layer on the critical dimension of a contact hole after etching.
FIG. 3 is a schematic diagram showing the influence of the thickness of an interlayer dielectric layer on the open circuit of an etched contact hole.
FIG. 4a is a schematic diagram of the distribution of the thickness of the interlayer dielectric layer in the wafer plane.
FIG. 4b is a schematic diagram illustrating the exposure intensity compensation of the thickness distribution of the interlayer dielectric layer in the wafer plane shown in FIG. 4a according to the contact hole forming method of the present invention.
Fig. 5a is a schematic view of a contact hole formed after an etching process without performing exposure intensity compensation on the thickness distribution of the interlayer dielectric layer in the wafer surface as shown in fig. 4 a.
Fig. 5b is a schematic view of a contact hole formed after an etching process under the condition that the exposure intensity is compensated for the thickness distribution of the interlayer dielectric layer in the wafer surface as shown in fig. 4 a.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating an effect of an interlayer dielectric layer thickness on a critical dimension of a contact hole after etching. As shown in fig. 2, the contact hole formed under the same photolithography process has a feature size of 0.065 μm, i.e., the photolithography process is the same, and the target critical dimension of the contact hole is 0.04 μm. When the thickness H1 of the interlayer dielectric layer (ILD) is larger than a standard value H, the size of the contact hole formed under the same etching process is reduced; when the thickness H2 of the interlayer dielectric layer (ILD) is smaller than the standard value H, the size of the contact hole formed by the same etching process becomes larger, i.e. deviates from the target critical dimension, so that the thickness of the ILD directly affects the size of the contact hole.
Further, referring to fig. 3, fig. 3 is a schematic diagram illustrating the influence of the thickness of the interlayer dielectric layer on the open circuit of the etched contact hole. According to the above description, the thicker the interlayer dielectric layer (ILD), the smaller the contact hole size, which may later cause the problem of contact hole open when the thickness of the ILD is too thick. As shown in fig. 3, under the same photolithography and etch recipe, as the thickness of the interlayer dielectric layer (ILD) increases from 1600 to 1800 and then to 2000, the number of open contact holes in the wafer increases, which affects the wafer yield. Therefore, under the condition that the thicknesses of the interlayer dielectric layers are different, how to make the critical dimension of the etched contact hole close to the target critical dimension becomes a problem to be solved urgently so as to ensure the stable electrical performance and the yield of the semiconductor device.
In an embodiment of the present invention, a method for forming a contact hole is provided, the method for forming a contact hole includes:
s1: and obtaining a relational expression of the change delta D1 of the feature critical dimension of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching.
Specifically, in an embodiment of the present invention, under the condition of the same interlayer dielectric layer (ILD) thickness, the critical dimension D1 of the contact hole feature formed under different lithography conditions and the critical dimension D2 of the contact hole formed by using the same etching process under each lithography condition are obtained, and the relational expression between the critical dimension change Δ D1 of the contact hole feature after lithography and the critical dimension change Δ D2 of the contact hole feature after etching is obtained according to the critical dimensions D1 of the contact hole features and the critical dimensions D2 of the contact holes corresponding to the contact holes.
Specifically, in an embodiment of the present invention, a relation between the post-lithography contact hole feature critical dimension change Δ D1 and the post-etching contact hole critical dimension change Δ D2 is Δ D2 — k1 Δ D1, and k1 is a coefficient obtained by fitting multiple tests. Specifically, in an embodiment of the present invention, k1 may vary from 1 to 1.5.
S2: obtaining the thickness H of the interlayer dielectric layerILDAnd the post-etch contact hole critical dimension D2.
Specifically, in an embodiment of the present invention, different thicknesses H of the interlayer dielectric layer are obtained under the same photolithography conditionILDThe critical dimension D2 of the etched contact hole formed by the next etching process is determined according to the thickness H of the multiple interlayer dielectric layersILDObtaining the thickness H of the interlayer dielectric layer corresponding to the critical dimension D2 of the contact holesILDAnd the post-etch contact hole critical dimension D2.
Specifically, in an embodiment of the present invention, the thickness H of the interlayer dielectric layerILDThe relation between the critical dimension D2 of the contact hole after etching is D2 ═ k2HILDAnd k2 is a coefficient obtained by fitting a plurality of tests. Specifically, in one embodiment of the present invention, k2 may vary anywhere from-0.5 to-0.08.
S3: according to the relational expression of the change delta D1 of the feature critical dimension of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching obtained in the step S1 and the interlayer dielectric layer obtained in the step S2Thickness HILDObtaining the shape critical dimension D1 of the contact hole after photoetching and the thickness H of the interlayer dielectric layer according to a relational expression of the shape critical dimension D2 of the contact hole after photoetching and the critical dimension D2 of the contact hole after etchingILDThe relationship (2) of (c).
S4: obtaining the exposure intensity and the thickness H of the interlayer dielectric layer according to the relationship between the critical dimension D1 of the contact hole morphology after photoetching by the photoetching machine and the exposure intensityILDThe compensation relationship between them.
S5: providing a wafer, forming an interlayer dielectric layer on the wafer substrate, wherein the thickness of the interlayer dielectric layer is not consistent in the wafer surface, detecting to obtain an interlayer dielectric layer thickness distribution diagram in the wafer surface, and obtaining the exposure intensity and the interlayer dielectric layer thickness H according to the step S4ILDThe compensation relationship between the two contact holes compensates the exposure intensity of an exposure unit on the wafer to obtain the shape of the contact hole after photoetching in the exposure unit, so that the key size of the contact hole formed after etching in the exposure unit is close to the target key size of the contact hole.
Specifically, referring to fig. 4a, fig. 4a is a schematic diagram illustrating the distribution of the thicknesses of the interlayer dielectric layers in the wafer plane, as shown in fig. 4a, the average thickness of the interlayer dielectric layers in the wafer plane is 1488 angstroms, the thickness of the interlayer dielectric layer of a part of the exposure units is close to the average thickness of the interlayer dielectric layers, the thickness of the interlayer dielectric layer of a part of the exposure units is thicker than the average thickness of the interlayer dielectric layers, for example, the thickness of the exposure unit 410 is 1587 angstroms, the thickness of the interlayer dielectric layer of a part of the exposure units is thinner than the average thickness of the interlayer dielectric layers, for example, the thickness of the exposure unit 420 is 1450 angstroms, that is, the thicknesses of the interlayer dielectric layers are not the same in the wafer plane. The thicker or thinner interlayer dielectric layer can cause the size of the contact hole formed after photoetching to deviate from the target critical size, and particularly the thicker interlayer dielectric layer is easy to cause the open circuit of the contact hole, and the electrical performance of the semiconductor device is stable and the yield is high. In the steps, a relational expression of the change delta D1 of the critical dimension of the shape of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching and the thickness H of the interlayer dielectric layer are obtained through a plurality of testsILDAnd the critical dimension D2 of the contact hole after etching, thereby obtaining the critical dimension D1 of the contact hole morphology and the thickness H of the interlayer dielectric layer after photoetchingILDAccording to the relationship between the contact hole feature critical dimension D1 after photoetching and the exposure strength of the photoetching machine, the compensation relationship between the exposure strength and the interlayer dielectric layer thickness HILD is obtained, the exposure strength of an exposure unit on the wafer is further compensated, namely, the contact hole with the contact hole feature critical dimension D1 after different photoetching in the interlayer dielectric layer thickness area is exposed, and finally the critical dimension of the contact hole formed after etching in the exposure unit is close to the target critical dimension of the contact hole. Specifically, please refer to fig. 4b, wherein fig. 4b is a schematic diagram illustrating exposure intensity compensation of the interlayer dielectric layer thickness distribution in the wafer plane shown in fig. 4a according to the contact hole forming method of the present invention. Specifically, referring to fig. 5a and 5b, fig. 5a is a schematic view of a contact hole formed after an etching process without exposure intensity compensation on the thickness distribution of the interlayer dielectric layer in the wafer plane as shown in fig. 4a, and fig. 5b is a schematic view of a contact hole formed after an etching process with exposure intensity compensation on the thickness distribution of the interlayer dielectric layer in the wafer plane as shown in fig. 4a, and as shown in fig. 5a and 5b, the number of open circuits of the contact hole formed by the contact hole forming method of the present invention is significantly reduced.
In one embodiment of the present invention, the compensation amount of the exposure intensity in step S5 is not more than 15% of the standard exposure intensity of the lithography machine. In an embodiment of the invention, there is a deviation of said 15%. In an embodiment of the present invention, the deviation is within 20%; preferably, the deviation is within 10%; more preferably, the deviation is within 50%.
In an embodiment of the present invention, the interlayer dielectric layer is made of SiO2 or SiCO.
In an embodiment of the invention, the substrate is a silicon substrate.
In one embodiment of the invention, the contact hole forming method is suitable for a contact hole forming process in a semiconductor device formed by an HKMG process. In one embodiment of the present invention, the HKMG process forms a semiconductor device having a gate electrode comprising a high dielectric constant (HK) gate dielectric layer and a Metal Gate (MG) formed thereon. In one embodiment of the invention, the contact hole forming method is suitable for the contact hole forming process in the semiconductor device formed by the 28HKMG process. In one embodiment of the invention, the semiconductor device formed by the HKMG process comprises a gate electrode, a source electrode and a drain electrode, wherein the gate electrode, the source electrode and the drain electrode are respectively led out according to contact holes formed by the contact hole forming method. In an embodiment of the present invention, the contact hole is filled with a metal (e.g., tungsten, referred to as a tungsten plug).
In summary, the relational expression of the feature critical dimension change Δ D1 of the contact hole after the lithography and the critical dimension change Δ D2 of the contact hole after the etching and the thickness H of the interlayer dielectric layer are obtained through a plurality of testsILDAnd the critical dimension D2 of the contact hole after etching, thereby obtaining the critical dimension D1 of the contact hole morphology and the thickness H of the interlayer dielectric layer after photoetchingILDAccording to the relationship between the contact hole feature critical dimension D1 after photoetching and the exposure strength of the photoetching machine, the compensation relationship between the exposure strength and the interlayer dielectric layer thickness HILD is obtained, the exposure strength of an exposure unit on the wafer is further compensated, namely, the contact hole with the contact hole feature critical dimension D1 after different photoetching in the interlayer dielectric layer thickness area is exposed, and finally the critical dimension of the contact hole formed after etching in the exposure unit is close to the target critical dimension of the contact hole.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. A method for forming a contact hole, comprising:
s1: obtaining a relational expression of the change delta D1 of the feature critical dimension of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching;
s2: obtaining the thickness H of the interlayer dielectric layerILDCritical dimension D2 of contact hole after etchingIs represented by the formula;
s3: according to the relational expression of the change delta D1 of the feature critical dimension of the contact hole after photoetching and the change delta D2 of the critical dimension of the contact hole after etching obtained in the step S1 and the thickness H of the interlayer dielectric layer obtained in the step S2ILDObtaining the shape critical dimension D1 of the contact hole after photoetching and the thickness H of the interlayer dielectric layer according to a relational expression of the shape critical dimension D2 of the contact hole after photoetching and the critical dimension D2 of the contact hole after etchingILDThe relationship of (1);
s4: obtaining the exposure intensity and the thickness H of the interlayer dielectric layer according to the relationship between the critical dimension D1 of the contact hole morphology after photoetching by the photoetching machine and the exposure intensityILDA compensation relationship therebetween; and
s5: providing a wafer, forming an interlayer dielectric layer on the wafer substrate, wherein the thickness of the interlayer dielectric layer is not consistent in the wafer surface, detecting to obtain an interlayer dielectric layer thickness distribution diagram in the wafer surface, and obtaining the exposure intensity and the interlayer dielectric layer thickness H according to the step S4ILDThe compensation relationship between the critical dimension D1 of the contact hole morphology after photoetching and the critical dimension D2 of the contact hole formed by adopting the same etching process under each photoetching condition is obtained according to the critical dimension D1 of the contact hole morphology after photoetching and the critical dimension D2 of the contact hole morphology after etching and the relational expression of the critical dimension change Delta D1 of the contact hole morphology after etching and the critical dimension change Delta D2 of the contact hole after etching; in step S2, different thicknesses H of the interlayer dielectric layer are obtained under the same photoetching conditionILDThe critical dimension D2 of the etched contact hole formed by the next etching process is determined according to the thickness H of the multiple interlayer dielectric layersILDObtaining the thickness H of the interlayer dielectric layer corresponding to the critical dimension D2 of the contact holesILDAnd the post-etch contact hole critical dimension D2.
2. The method of claim 1, wherein the relationship between the post-lithography contact hole profile critical dimension change Δ D1 and the post-etch contact hole critical dimension change Δ D2 is Δ D2 ═ k1 Δ D1, and k1 is a coefficient obtained by fitting multiple tests.
3. The contact hole forming method according to claim 2, wherein the variation range of k1 is any value between 1 and 1.5.
4. The method of claim 1, wherein the thickness of the interlayer dielectric layer is HILDThe relation between the critical dimension D2 of the contact hole after etching is D2 ═ k2HILDAnd k2 is a coefficient obtained by fitting a plurality of tests.
5. The method of claim 4, wherein k2 is varied to any value between-0.5 and-0.08.
6. The method of claim 1, wherein the exposure intensity is compensated in step S5 by no more than 15% of the standard exposure intensity of the lithography machine.
7. The method of claim 6, wherein the 15% has a certain deviation.
8. The method of claim 7, wherein the deviation is within 20%.
9. The method of claim 7, wherein the deviation is within 10%.
10. The method of claim 7, wherein the deviation is within 5%.
11. The method of claim 1, wherein said interlayer dielectric layer is made of SiO2 or SiCO.
12. The contact hole forming method according to claim 1, wherein the contact hole forming method is applied to a contact hole forming process in a semiconductor device formed by an HKMG process.
13. The contact hole forming method according to claim 1, wherein the semiconductor device formed by the HKMG process includes a gate electrode, a source electrode, and a drain electrode, which are led out respectively according to the contact hole formed by the contact hole forming method.
14. The method of claim 1, wherein the method is suitable for a contact hole formation process in a semiconductor device formed by a 28HKMG process.
15. The method of claim 13, wherein the contact hole is filled with tungsten metal.
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