CN110764028B - Integrated circuit pin clamping abnormity detection and protection device - Google Patents
Integrated circuit pin clamping abnormity detection and protection device Download PDFInfo
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- CN110764028B CN110764028B CN201910956350.8A CN201910956350A CN110764028B CN 110764028 B CN110764028 B CN 110764028B CN 201910956350 A CN201910956350 A CN 201910956350A CN 110764028 B CN110764028 B CN 110764028B
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- 238000001514 detection method Methods 0.000 title abstract description 40
- 238000012360 testing method Methods 0.000 abstract description 28
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 230000005856 abnormality Effects 0.000 abstract description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 abstract description 3
- 238000001914 filtration Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
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- General Physics & Mathematics (AREA)
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Abstract
The invention discloses an integrated circuit pin clamping abnormity detection and protection device, which comprises a detection relay, an alternating current signal generation circuit, a rectification filter circuit, an adjustable voltage reference circuit, a comparison circuit, a self-locking circuit, a clamping abnormity driving circuit, a clamping abnormity alarm circuit, a clamping normal driving circuit, a clamping normal indicating circuit, a test power supply, a power supply relay and a power supply delay driving circuit, wherein the detection relay is connected with the alternating current signal generation circuit; when the integrated circuit pin is clamped normally and abnormally, the reactance between the pins is different, and the influence of different reactances on the detection signal is different, so that the influence of the reactance between the integrated circuit pins on the detection signal is used for detecting the clamping condition of the test fixture on the integrated circuit pin, the clamping abnormal condition is judged and detected, and when the abnormality occurs, the test power supply applied to the integrated circuit is cut off, so that the integrated circuit is protected.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to a device for detecting and protecting clamping abnormality of an integrated circuit pin.
Background
The integrated circuit test has very important function in the development, production and use processes of the integrated circuit, and the realization of the reliable test of the integrated circuit is very necessary.
When an integrated circuit is tested, if the contact between the pins of the integrated circuit and a test fixture is poor, the test result is unreliable if the pins of the integrated circuit and the test fixture are light, and the integrated circuit is damaged if the pins of the integrated circuit and the test fixture are heavy. The situation that the test fixture clamps the pins of the integrated circuit does not have a technical judgment method at present, and the situation is judged according to a test result after the integrated circuit is plugged in and pulled out from the test fixture for many times.
Disclosure of Invention
The invention aims to provide an integrated circuit pin clamping abnormity detection and protection device, which can judge and detect the clamping condition of a pin during integrated circuit test, and protect the integrated circuit when the clamping is abnormal, so as to avoid the damage of the integrated circuit.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a device for detecting and protecting clamping abnormity of an integrated circuit pin comprises a detection relay, an alternating current signal generating circuit, a rectifying filter circuit, an adjustable voltage reference circuit, a comparison circuit, a self-locking circuit, a clamping abnormity driving circuit, a clamping abnormity alarming circuit, a clamping normal driving circuit, a clamping normal indicating circuit, a test power supply, a power supply relay and a power supply delay driving circuit;
the output end of the power supply delay driving circuit is connected with a coil of a power supply relay, and a test power supply is applied to the integrated circuit through a normally open contact of the power supply relay;
the AC signal output by the AC signal generating circuit passes through any two clamping pins of the detection relay normally-closed contact series integrated circuit and is input into the rectifying and filtering circuit, the input end of the rectifying and filtering circuit is grounded through a resistor, the output end of the rectifying and filtering circuit is connected with the in-phase input end of the comparison circuit, the output end of the adjustable voltage reference circuit is connected with the reverse-phase input end of the comparison circuit, the output end of the comparison circuit outputs a detection signal, the detection signal is fed back to the in-phase input end of the comparison circuit through the self-locking circuit, and the detection signal is also respectively used as the input ends of the clamping abnormal driving circuit, the clamping normal driving circuit and the power supply delay driving circuit; the output end of the clamping abnormal driving circuit is connected with the clamping abnormal alarming circuit, and the output end of the clamping normal driving circuit is respectively connected with the clamping normal indicating circuit and the coil of the detection relay.
The invention has the advantages that when the integrated circuit pin is clamped normally and abnormally, the reactance between the pins is different, and the influence of different reactances on the detection signal is different, so the influence of the reactance between the integrated circuit pins on the detection signal is used for detecting the clamping condition of the test fixture on the integrated circuit pin, thereby realizing the judgment and detection of the clamping condition, and when the abnormality occurs, a test power supply is not applied to the integrated circuit, thereby realizing the protection of the integrated circuit.
Drawings
The invention is further illustrated with reference to the following figures and examples:
fig. 1 is an electrical schematic block diagram of the present invention.
Detailed Description
As shown in fig. 1, the present invention provides an integrated circuit pin clamping abnormality detection and protection device, which includes a detection relay 1, an alternating current signal generation circuit 2, a rectification filter circuit 3, an adjustable voltage reference circuit 4, a comparison circuit 5, a self-locking circuit 6, a clamping abnormality driving circuit 7, a clamping abnormality alarm circuit 8, a clamping normal driving circuit 9, a clamping normal indication circuit 10, a test power supply 11, a power supply relay 12, and a power supply delay driving circuit 13.
The output end of the power supply delay driving circuit 13 is connected with the coil of the power supply relay 12, and the test power supply 11 is applied to the integrated circuit 15 through the normally open contact of the power supply relay 12.
The alternating current signal that alternating current signal generating circuit 2 output passes through two arbitrary centre gripping pins of the normally closed contact series integrated circuit 15 of detection relay 1, and with alternating current signal input rectification filter circuit 3, rectification filter circuit 3 input still passes through resistance R1 ground connection, the homophase input of comparison circuit 5 is connected to rectification filter circuit 3's output, the inverting input of comparison circuit 5 is connected to adjustable voltage reference circuit 4's output, comparison circuit 5's output test signal V1, test signal V1 feeds back the homophase input of comparison circuit 5 through self-locking circuit 6.
For other clamping pins needing to be detected, an alternating current signal generating circuit, a detection relay, a rectification filter circuit and a comparison circuit are also arranged, and corresponding detection signals are obtained through the comparison circuit; therefore, the and logic circuit 14 is provided, and the and logic circuit 14 and the detection signals V1 to Vn perform the and operation, so that if at least one of the detection signals V1 to Vn is at the low level when there is a pin clamping abnormality, the logic detection signal V output from the output terminal of the and logic circuit 14 is at the low level.
The logic detection signal V is also respectively used as the input ends of the clamping abnormal drive circuit 7, the clamping normal drive circuit 9 and the power supply delay drive circuit 13; the output end of the clamping abnormity driving circuit 7 is connected with a clamping abnormity warning circuit 8, and the output end of the clamping normal driving circuit 9 is respectively connected with a clamping normal indicating circuit 10 and a coil of the detection relay 1.
In this embodiment, the reactance between the two pins m and n of the integrated circuit is X, the ac signal is converted into a dc signal through the rectifying and filtering circuit 3, and when the pin of the integrated circuit is clamped abnormally, the amplitude of the signal at the point B is reduced or zero (when the pin is clamped open), and the dc voltage at the point C is reduced or zero. The voltage reference of the adjustable voltage reference circuit 4 is set to be slightly smaller than the potential at the point C when the clamp is normal, and at this time, the output of the comparison circuit 5 is low level, that is, the detection signal V1 is low level, so that the logic detection signal V output by the output terminal of the and logic circuit 14 is low level. The clamp abnormity driving circuit 7 is conducted to work, and the clamp abnormity alarming circuit 8 is driven to carry out sound and light alarming.
When the logic detection signal V output from the output terminal of the and logic circuit 14 is at a low level, the power supply delay driving circuit 13 is turned off, so that the normally open contact of the power supply relay 12 maintains the off state, and the test power supply 11 does not supply power to the integrated circuit 15. Therefore, the situation that the test result is unreliable and even the integrated circuit is damaged when the integrated circuit pin is abnormally clamped and the power supply test is carried out on the integrated circuit is avoided.
When the pins of the integrated circuit are clamped normally, the amplitude of the signal at the point B is large, the output of the comparison circuit 5 is at a high level, that is, the detection signal V1 is at a high level, when all the pins are clamped normally, the logic detection signal V output by the output end of the logic circuit 14 is at a high level, at this time, the clamping abnormal driving circuit 7 is turned off, and the clamping normal driving circuit 9 is turned on to work, so that the clamping normal indicating circuit 10 emits light for indication. Meanwhile, the coil of the detection relay 1 is electrified by the logic detection signal V, and the normally closed contact is disconnected, so that the detection circuit is prevented from influencing the normal test of the integrated circuit. And the detection signal V1 is fed back to the non-inverting input end of the comparison circuit 5 through the self-locking circuit 6, even if the normally closed contact of the detection relay 1 is disconnected, the output of the comparison circuit 5 can still be ensured to be high level.
The logic detection signal V output by the output terminal of the logic circuit 14 is at a high level, so that the power supply delay driving circuit 13 is turned on in a delay manner, the normally open contact of the power supply relay 12 is closed, the test power supply 11 is applied to the integrated circuit 15, and the integrated circuit is tested normally. The power supply delay driving circuit 13 is turned on in a delayed manner, so as to ensure that the whole detection circuit is disconnected with the integrated circuit when the integrated circuit is powered on, and prevent the detection circuit from influencing the test of the integrated circuit.
The invention adopts the alternating current signal output by the alternating current signal generating circuit, and can ensure that the invention can still work normally when the pins of the integrated circuit are pure capacitive reactance. The alternating current signal at the point B is rectified and filtered and converted into a direct current signal, so that a subsequent processing circuit can be simplified.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention.
Claims (1)
1. A device for detecting and protecting clamping abnormity of an integrated circuit pin is characterized by comprising a detection relay, an alternating current signal generating circuit, a rectifying and filtering circuit, an adjustable voltage reference circuit, a comparison circuit, a self-locking circuit, a logical circuit, a clamping abnormity driving circuit, a clamping abnormity warning circuit, a clamping normal driving circuit, a clamping normal indicating circuit, a test power supply, a power supply relay and a power supply delay driving circuit;
the output end of the power supply delay driving circuit is connected with a coil of a power supply relay, and a test power supply is applied to the integrated circuit through a normally open contact of the power supply relay;
the AC signal output by the AC signal generating circuit passes through any two clamping pins of the detection relay normally-closed contact series integrated circuit and is input into the rectification filter circuit, the input end of the rectification filter circuit is grounded through a resistor, the output end of the rectification filter circuit is connected with the in-phase input end of the comparison circuit, the output end of the adjustable voltage reference circuit is connected with the reverse-phase input end of the comparison circuit, the output end of the comparison circuit outputs a detection signal, the detection signal is fed back to the in-phase input end of the comparison circuit through the self-locking circuit, and the detection signal is subjected to AND operation through the AND logic circuit, and the logic detection signal is also respectively used as the input end of the clamping abnormal driving circuit, the clamping normal driving circuit and the power supply delay driving circuit; the output end of the clamping abnormal driving circuit is connected with the clamping abnormal alarming circuit, and the output end of the clamping normal driving circuit is respectively connected with the clamping normal indicating circuit and the coil of the detection relay.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910956350.8A CN110764028B (en) | 2019-10-10 | 2019-10-10 | Integrated circuit pin clamping abnormity detection and protection device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910956350.8A CN110764028B (en) | 2019-10-10 | 2019-10-10 | Integrated circuit pin clamping abnormity detection and protection device |
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| CN110764028A CN110764028A (en) | 2020-02-07 |
| CN110764028B true CN110764028B (en) | 2021-11-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113341344B (en) * | 2021-05-11 | 2023-02-17 | Tcl王牌电器(惠州)有限公司 | Circuit on-off detection device |
| CN115691015A (en) * | 2022-10-24 | 2023-02-03 | 佛山市新东方电子技术工程有限公司 | Capacitive anti-theft detection circuit and anti-theft and anti-robbery device |
| CN116540088B (en) * | 2023-06-26 | 2023-09-12 | 深圳市优界科技有限公司 | Automatic detection device for relay |
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| WO2011055611A1 (en) * | 2009-11-05 | 2011-05-12 | ローム株式会社 | Signal transmission circuit device, semiconductor device, method and apparatus for inspecting semiconductor device, signal transmission device, and motor drive apparatus using signal transmission device |
| US9506961B2 (en) * | 2014-12-04 | 2016-11-29 | Chicony Power Technology Co., Ltd. | Power supply detection apparatus and detecting method thereof |
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- 2019-10-10 CN CN201910956350.8A patent/CN110764028B/en active Active
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| CN104698334A (en) * | 2015-02-11 | 2015-06-10 | 友达光电股份有限公司 | Integrated circuit and method for judging pin connection condition of integrated circuit |
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