CN110752215A - Manufacturing method of SONOS memory - Google Patents
Manufacturing method of SONOS memory Download PDFInfo
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a manufacturing method of an SONOS memory, which comprises the steps of providing a semiconductor substrate, covering a pad oxide layer on the surface of the semiconductor substrate, generating a sacrificial layer with the thickness larger than that of the pad oxide layer on the surface of the semiconductor substrate after removing the pad oxide layer, removing the sacrificial layer in a storage tube area, then sequentially depositing a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate, removing the second oxide layer, and removing the nitride layer and the first oxide layer from the parts of a selection tube area and a peripheral logic area. When the etching process is used for removing the parts of the nitride layer, which are positioned in the selection tube area and the peripheral logic area, the first oxide layer and the sacrificial layer below are used as etching stop layers, and the sacrificial layer is thick, so that the problem that the nitride layer is etched through during etching can be effectively avoided, the damage of the nitride layer to the semiconductor substrate can be reduced, the reliability of the SONOS memory is improved, and meanwhile, the etching process window of the nitride layer can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an SONOS memory.
Background
The SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory has the characteristics of small unit size, good storage retentivity, low operating voltage and the like, and is widely applied to computers and other equipment. In the manufacturing process of the SONOS memory, a storage tube region, a selection tube region and a peripheral logic region are arranged on a semiconductor substrate, wherein an Oxide-Nitride-Oxide (ONO) layer is required to be generated on the surface of the storage tube region, and when the SONOS memory is manufactured, a first Oxide layer, a Nitride layer and a second Oxide layer which are sequentially overlapped and cover the whole surface of the semiconductor substrate are usually formed, and then the parts of the three layers outside the storage tube region are removed.
As the size of SONOS memory devices is reduced, such as 40nm process node SONOS memory devices, the devices employ shallow junctions, and the pad oxide layer covering the surface of the semiconductor substrate during ion implantation is usually set to be thinner in order to ensure better uniformity of the devices. In addition, before the first oxide layer, the nitride layer and the second oxide layer are sequentially deposited on the surface of the semiconductor substrate, the native oxide layer on the surface of the storage tube region is usually removed by surface cleaning, and the pad oxide layers on the surfaces of the select tube region and the peripheral logic region are also further thinned in the surface cleaning process.
At present, the following problems exist in the process of removing the nitride layer in the selection pipe area and the peripheral logic area: firstly, etching a nitride layer needs to use a first oxide layer and a pad oxide layer below the nitride layer as an etching stop layer (stop layer), and because the pad oxide layer has little residue after previous processes, the nitride layer is easy to etch through during etching, a semiconductor substrate below the pad oxide layer is easy to damage, and defects such as pits on the surface of the substrate are formed, so that the reliability problem of a device is caused; secondly, if the damage to the semiconductor substrate is reduced by adjusting the etching amount of the silicon nitride, the silicon nitride residue is easy to generate, and the etching process window is insufficient.
Disclosure of Invention
The invention provides a manufacturing method of an SONOS memory, which aims to solve the problems of poor device reliability and insufficient etching process window caused by over-thin pad oxide layer at the lower layer when nitride layers of a storage tube region and a peripheral circuit region are removed.
In order to solve the above problems, the present invention provides a method for manufacturing a SONOS memory, including:
providing a semiconductor substrate, wherein a shallow trench isolation structure and an active area limited by the shallow trench isolation structure are arranged in the semiconductor substrate, the active area comprises a storage tube area, a selection tube area and a peripheral logic area, well injection is performed on the storage tube area, the selection tube area and the peripheral logic area, and a pad oxide layer covers the surface of the semiconductor substrate;
removing the pad oxide layer, and generating a sacrificial layer on the surface of the semiconductor substrate, wherein the thickness of the sacrificial layer is greater than that of the pad oxide layer;
removing the sacrificial layer in the storage tube region;
depositing a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate in sequence, wherein the first oxide layer covers the remaining sacrificial layer and the semiconductor substrate exposed out of the storage tube region, the nitride layer covers the first oxide layer, and the second oxide layer covers the nitride layer;
removing the second oxide layer; and
and removing the nitride layer and the first oxide layer from the selection pipe area and the peripheral logic area, and removing the rest of the sacrificial layer.
Optionally, the sacrificial layer is formed on the surface of the semiconductor substrate by a low-pressure base oxidation process, a chemical vapor deposition process or a furnace tube oxidation process.
Optionally, before removing the pad oxide layer, the manufacturing method further includes performing a device well implantation process, and performing an ion implantation process for adjusting a threshold voltage in the peripheral logic region.
Optionally, after the sacrificial layer is generated on the surface of the semiconductor substrate and before the sacrificial layer in the storage tube region is removed, the manufacturing method further includes: and performing an ion implantation process for adjusting the threshold voltage of the control gate in the storage tube region.
Optionally, the method for removing the nitride layer and the first oxide layer from the portion of the select tube region and the peripheral logic region includes:
forming a mask covering the storage tube region on the semiconductor substrate;
performing an etching process to remove the portions of the nitride layer located in the select transistor region and the peripheral logic region, wherein the first oxide layer and the remaining sacrificial layer are used as an etching stop layer; and
and removing the first oxide layer and the remaining sacrificial layer.
Optionally, removing the portions of the nitride layer located in the select tube region and the peripheral logic region by successively performing a wet etching process and a dry etching process; and removing the first oxide layer and the rest sacrificial layer by adopting a wet etching process.
Optionally, the method for removing the sacrificial layer in the storage tube region includes:
sequentially forming a bottom anti-reflection layer and a photoresist layer on the semiconductor substrate;
carrying out patterning treatment on the photoresist layer to expose the bottom anti-reflection layer of the storage tube region;
removing the exposed bottom anti-reflection layer to expose the sacrificial layer of the storage tube region; and
removing the sacrificial layer in the region of the storage tube.
Optionally, after removing the sacrificial layer in the storage tube region and before depositing the first oxide layer, the nitride layer, and the second oxide layer, the manufacturing method further includes:
and pre-cleaning the surface of the semiconductor substrate, and removing a natural oxidation layer on the surface of the semiconductor substrate in the storage tube area.
Optionally, the thickness of the sacrificial layer is
The sacrificial layer is silicon oxide.
Optionally, the pad oxide layer is removed by using a BOE solution or a hydrofluoric acid solution.
The manufacturing method of the SONOS memory comprises the steps that a pad oxide layer covers the surface of a semiconductor substrate, after the pad oxide layer is removed, a sacrificial layer larger than the thickness of the pad oxide layer is generated on the surface of the semiconductor substrate, the sacrificial layer in a storage tube area is removed, then a first oxide layer, a nitride layer and a second oxide layer are sequentially deposited on the semiconductor substrate, all the second oxide layer is removed, and the nitride layer and the first oxide layer are removed from the selection tube area and the peripheral logic area. When the etching process is used for removing the parts of the nitride layer, which are positioned in the selection tube area and the peripheral logic area, the first oxide layer and the sacrificial layer below are used as etching stop layers, and the sacrificial layer is thick, so that the problem that the nitride layer is etched through during etching can be effectively avoided, the damage of the nitride layer to the semiconductor substrate can be reduced, the reliability of the SONOS memory is improved, and meanwhile, the etching process window of the nitride layer can be improved.
Drawings
Fig. 1a to 1d are schematic cross-sectional views of a SONOS memory device during a manufacturing process.
Fig. 2 is a flowchart of a method for fabricating a SONOS memory device according to an embodiment of the invention.
Fig. 3a to fig. 3e are schematic cross-sectional views illustrating a SONOS memory fabricated by a method for fabricating a SONOS memory according to an embodiment of the invention.
Description of reference numerals:
100-a semiconductor substrate; 101-a storage tube region; 102-selecting a tube region; 103-peripheral logic area; 104-shallow trench isolation structure; 110-pad oxide layer; 120-a first oxide layer; 130-a nitride layer; 140-a second oxide layer; 150-sacrificial layer.
Detailed Description
The method for fabricating the SONOS memory device according to the present invention is described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1a to 1d are schematic cross-sectional views of a SONOS memory device during a manufacturing process. As shown in fig. 1a to 1d, in order to more clearly illustrate the characteristics of the method for fabricating a SONOS memory according to the present invention, a method for fabricating a SONOS memory is first described below.
As shown in fig. 1a, the method for fabricating the SONOS memory device includes a first step: providing a semiconductor substrate 100, wherein the semiconductor substrate 100 is provided with a shallow trench isolation structure 104 and an active area defined by the shallow trench isolation structure 104, the active area comprises a storage tube area 101 in which ion implantation is performed, a selection tube area 102 and a peripheral logic area 103, and the surface of the semiconductor substrate 100 is further covered with a pad oxide layer 110.
Wherein, in order to ensure that the device has better uniform performance, the pad oxide layer needs to be thinner during ion implantation, and as an example, the thickness of the pad oxide layer deposited on the surface of the semiconductor substrate isAfter performing shallow trench isolation polishing (STI CMP) and removing the SiN layer (as a hard mask layer) covering the pad oxide layer 110, the thickness of the pad oxide layer is
On the left and right, the thinner pad oxide layer facilitates ion implantation of the semiconductor substrate in the active region.
As shown in fig. 1b, the method for manufacturing the SONOS memory device includes a second step: sequentially forming a bottom anti-reflection layer (BARC) and a photoresist layer on the semiconductor substrate 100, performing patterning on the photoresist layer to expose the bottom anti-reflection layer of the storage tube region 101, and removing the exposed bottom anti-reflection layer to expose the pad oxide layer 110 of the storage tube region; performing storage tube region adjustment control gate threshold voltage ion implantation (SONOS CG Vt IMP); and then removing the pad oxide layer in the storage tube area, and then removing the photoresist layer and the anti-reflection layer.
As shown in fig. 1c, the method for manufacturing the SONOS memory device includes a third step: in order to improve the stability of the SONOS structure, the surface of the semiconductor substrate 100 is cleaned, and the natural oxide layer on the surface of the storage tube region 101 is removed. Then, an In-situ (In-situ) method is used to sequentially deposit a first oxide layer 120, a nitride layer 130 and a second oxide layer 140 on the surface of the semiconductor substrate 100, wherein the first oxide layer 120 covers the exposed semiconductor substrate of the storage tube region 101 and the rest of the pad oxide layer 110, the nitride layer 130 covers the first oxide layer 120, and the second oxide layer 140 covers the nitride layer 130.
Wherein, when surface cleaning is carried out, the pad oxide layer on the surfaces of the selection tube area and the peripheral logic area can be further thinned, and the etching amount of the surface cleaning is, as an exampleLeft and right, the thickness of the pad oxide layer after surface cleaning is
Left and right.
As shown in fig. 1d, the method for manufacturing the SONOS memory device includes a fourth step: removing the second oxide layer 140 by wet etching; coating and developing photoresist on the surface of the semiconductor substrate to expose the select transistor region 102 and the peripheral logic region 130; then, removing the portions of the nitride layer 130 in the select tube region 102 and the peripheral logic region 103 by dry etching, wherein the first oxide layer 120 and the remaining pad oxide layer 110 are used as an etching stop layer; then, the first oxide layer 120 and the remaining pad oxide layer 110 on the surfaces of the select transistor region 102 and the peripheral logic region 103 are removed, and the photoresist on the surface of the semiconductor substrate is removed.
Although the method for manufacturing the SONOS memory can manufacture the SONOS memory, the method still has a plurality of problems. In particular, in order to ensure the device has better uniformity, the pad oxide layer needs to be thinner during ion implantation, and the thickness of the pad oxide layer deposited on the surface of the semiconductor substrate before forming the shallow trench is, for example, the thickness
In performing shallow trench isolationAfter the separation polishing (STI CMP) and the removal of the SiN layer covering the pad oxide layer, the thickness of the pad oxide layer is
On the other hand, the pad oxide layer with this thickness has substantially no influence on the ion implantation performed later, and contributes to obtaining better uniformity. After ion implantation is finished, when the surface of the storage tube area is cleaned and the natural oxide layer on the surface of the storage tube area is removed, the pad oxide layers on the surfaces of the selection tube area and the peripheral logic area are further thinned, and the thickness of the pad oxide layer after surface cleaning is equal to that of the pad oxide layer
Left and right. When the nitride layers of the selection tube area and the peripheral logic area are etched in the fourth step, the first oxide layer and the pad oxide layer below the selection tube area and the nitride layer serve as etching stop layers, but the pad oxide layer is less in residue, thin and poor in etching stop effect, excessive etching is easy to occur when the nitride layer is etched, and then the semiconductor substrate below the pad oxide layer is easily damaged, and defects such as pits on the surface of the semiconductor substrate are formed, so that the reliability problem of the device is caused. In addition, if the amount of silicon nitride etching is adjusted to reduce the damage to the semiconductor substrate, silicon nitride residue is likely to be generated, which results in a lack of etching process window. The method for manufacturing the SONOS memory according to the embodiment of the present invention is mainly proposed to solve the problems. Next, a method for manufacturing the SONOS memory according to the embodiment of the present invention will be described in detail.
Fig. 2 is a flowchart of a method for fabricating a SONOS memory device according to an embodiment of the invention. As shown in fig. 2, in order to overcome the above-mentioned drawbacks of the method for manufacturing a SONOS memory, the present invention provides a method for manufacturing a SONOS memory, which includes the following steps:
s1: providing a semiconductor substrate, wherein a shallow trench isolation structure and an active area limited by the shallow trench isolation structure are arranged in the semiconductor substrate, the active area comprises a storage tube area, a selection tube area and a peripheral logic area, well injection is performed on the storage tube area, the selection tube area and the peripheral logic area, and a pad oxide layer covers the surface of the semiconductor substrate;
s2: removing the pad oxide layer, and generating a sacrificial layer on the surface of the semiconductor substrate, wherein the thickness of the sacrificial layer is greater than that of the pad oxide layer;
s3: removing the sacrificial layer in the storage tube region;
s4: depositing a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate in sequence, wherein the first oxide layer covers the remaining sacrificial layer and the semiconductor substrate exposed out of the storage tube region, the nitride layer covers the first oxide layer, and the second oxide layer covers the nitride layer;
s5: removing the second oxide layer;
s6: and removing the nitride layer and the first oxide layer from the selection pipe area and the peripheral logic area, and removing the rest of the sacrificial layer.
In the method for manufacturing the SONOS memory in this embodiment, after the pad oxide layer is removed, a sacrificial layer is first generated on the surface of the semiconductor substrate, and the thickness of the sacrificial layer is greater than that of the pad oxide layer, so that the problem that the remaining pad oxide layer after ion implantation is small due to the thinness of the pad oxide layer can be avoided. After forming the sacrificial layer with a larger thickness, when further etching and removing the nitride layer at the select transistor region and the peripheral logic region, the sacrificial layer covers the surface of the semiconductor substrate, so that the sacrificial layer can be used as an etching stop layer together with the first oxide layer, and because the sacrificial layer is thicker, the problem that the nitride layer directly penetrates the semiconductor substrate due to over-etching during etching can be effectively avoided.
In this embodiment, the semiconductor substrate may be a silicon substrate. However, in other embodiments, the semiconductor substrate may also be a Germanium substrate, a Silicon Germanium substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc., and a certain doping particle may be implanted into the semiconductor substrate according to design requirements to change electrical parameters.
Fig. 3a to fig. 3e are schematic cross-sectional views illustrating a SONOS memory fabricated by a method for fabricating a SONOS memory according to an embodiment of the invention. Specifically, as shown in fig. 1a, fig. 3a and fig. 3b, the surface of the semiconductor substrate 100 is covered with the pad oxide layer 110, and since the semiconductor substrate 100 has performed the shallow trench isolation polishing and removed the SiN layer covering the pad oxide layer, the thickness of the pad oxide layer 110 is thinner, in this embodiment, the pad oxide layer 110 is removed first, the semiconductor substrate 110 exposes a clean surface, and then the sacrificial layer 150 is formed on the surface of the semiconductor substrate, and the thickness of the sacrificial layer 150 is greater than the thickness of the pad oxide layer 110.
More specifically, in this embodiment, the pad oxide layer may be removed by wet etching, and the wet etching may use a BOE solution (buffered oxide etching solution) or a hydrofluoric acid solution. After the pad oxide layer 110 is removed by etching, the sacrificial layer 150 may be formed on the surface of the semiconductor substrate 100 by a Low Pressure Radical Oxidation (LPRO) process, a Chemical Vapor Deposition (CVD) process, or a furnace oxidation process. The thickness of the sacrificial layer can be adjusted according to the process requirement of removing the nitride layer by etching, and the thickness of the sacrificial layer can be within the range of
Or
In order not to increase the fabrication steps of the SONOS memory device, the sacrificial layer and the first oxide layer deposited subsequently may be removed at the same time after the nitride layer is etched, and thus, in this embodiment, the sacrificial layer and the first oxide layer may be made of the same material, and may both be made of silicon oxide. However, in other implementations, the sacrificial layer and the first oxide layer may be different materials or both materials other than silicon oxide.
In this embodiment, the method for manufacturing the SONOS memory may further include: and before removing the pad oxide layer, performing a device trap implantation process, and performing an ion implantation process for adjusting the threshold voltage in the peripheral logic region.
As shown in fig. 3c, in this embodiment, after the sacrificial layer is formed on the surface of the semiconductor substrate, in order to form the SONOS structure in the memory tube region, the sacrificial layer in the memory tube region needs to be removed, so that the first oxide layer formed by subsequent deposition directly covers the surface of the semiconductor substrate in the memory tube region. The method of removing the sacrificial layer of the storage tube region may comprise: sequentially forming a bottom anti-reflection layer and a photoresist layer on the semiconductor substrate, performing patterning treatment on the photoresist layer to expose the bottom anti-reflection layer in the storage tube area, removing the exposed bottom anti-reflection layer to expose the sacrificial layer in the storage tube area, and removing the sacrificial layer in the storage tube area.
In order to improve the precision of the pattern formed by the patterning treatment of the photoresist layer, an anti-reflection layer is firstly generated on the surface of the semiconductor substrate before the photoresist layer is formed. After the generating the sacrificial layer on the surface of the semiconductor substrate and before removing the sacrificial layer in the storage tube region, the manufacturing method may further include: and after the anti-reflection layer of the storage tube region is etched on the semiconductor substrate, adjusting and controlling the gate threshold voltage ion implantation process in the storage tube region. The storage tube region antireflection layer etching can adopt dry etching.
After removing the sacrificial layer on the surface of the storage tube region, the surface of the storage tube region of the semiconductor substrate 100 is exposed in the air and is easily oxidized to generate a natural oxide layer, and in order to improve the stability of the SONOS structure, the manufacturing method may further include: after removing the sacrificial layer in the storage tube area and before depositing the first oxide layer, the nitride layer and the second oxide layer, pre-cleaning the surface of the semiconductor substrate, and removing the natural oxide layer on the surface of the semiconductor substrate in the storage tube area. As an example, in this embodiment, a hydrofluoric acid solution is used to clean the surface of the semiconductor substrate to remove the native oxide layer.
As shown in fig. 3d, after removing the native oxide layer on the surface of the storage tube region, a first oxide layer 120, a nitride layer 130, and a second oxide layer 140 are sequentially deposited on the semiconductor substrate 100, the first oxide layer 120 covers the remaining sacrificial layer and the semiconductor substrate exposed in the storage tube region, the nitride layer 130 covers the first oxide layer 120, and the second oxide layer 140 covers the nitride layer 130.
Specifically, In the embodiment, an In-situ method (In-situ) is adopted to sequentially deposit the first oxide layer 120, the nitride layer 130 and the second oxide layer 140 on the semiconductor substrate 100, wherein the first oxide layer may be formed by a low-pressure-based oxidation (LPRO) process, a Chemical Vapor Deposition (CVD) process or a furnace oxidation process, the nitride layer may be formed by an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma-assisted chemical vapor deposition (PECVD) process or an electron cyclotron resonance sputtering process, and the second oxide layer may be formed by a low-pressure furnace (HTO) process.
As shown in fig. 3e, after depositing the first oxide layer 120, the nitride layer 130 and the second oxide layer 140 on the semiconductor substrate in sequence, wet etching may be used to remove all of the second oxide layer 140, and then removing the nitride layer 130 and the first oxide layer 120 at the select transistor region 102 and the peripheral logic region 103, and removing the remaining sacrificial layer. The method for removing the nitride layer and the first oxide layer from the portions of the select tube region and the peripheral logic region may include: forming a mask covering the storage tube region on the semiconductor substrate, and performing an etching process to remove the portions of the nitride layer located in the selection tube region and the peripheral logic region, wherein the first oxide layer and the remaining sacrificial layer are used as etching stop layers, and then the first oxide layer and the remaining sacrificial layer are removed. Because the sacrificial layer is thicker, the first oxide layer and the rest sacrificial layer are used as the stop layer for etching the nitride layer, the problem that the nitride layer is etched and directly penetrates through the semiconductor substrate can be avoided, the damage of the nitride layer to the semiconductor substrate caused by etching is reduced, and meanwhile, the process window for etching the nitride layer can be improved.
Specifically, in this embodiment, the removal of the portions of the nitride layer located in the select transistor region and the peripheral logic region may be performed by a wet etching process and a dry etching process, which are performed in sequence, and the wet etching process may be first used to clean the surface of the nitride layer, and then the dry etching process is performed to remove the nitride layer; the first oxide layer and the remaining sacrificial layer may be removed by a wet etching process. However, in other embodiments, other etching methods in the art may be used by those skilled in the art, as long as the nitride layer, the first oxide layer and the sacrificial layer in the select transistor region and the peripheral logic region can be removed.
The method for manufacturing the SONOS memory comprises providing a semiconductor substrate, wherein the semiconductor substrate is provided with a shallow trench isolation structure and an active region defined by the shallow trench isolation structure, the active region comprises a storage tube region, a selection tube region and a peripheral logic region, wherein well injection is performed on the storage tube region, the selection tube region and the peripheral logic region, the surface of the semiconductor substrate is covered with a pad oxide layer, after removing the pad oxide layer, generating a sacrificial layer on the surface of the semiconductor substrate, wherein the thickness of the sacrificial layer is greater than that of the pad oxide layer, and then removing the sacrificial layer in the storage tube region, and sequentially depositing a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate, removing the second oxide layer, removing the nitride layer and the first oxide layer from the selection tube region and the peripheral logic region, and removing the rest of the sacrificial layer. The manufacturing method of the SONOS memory has the following advantages:
generating a new sacrificial layer after ion implantation of a semiconductor substrate device and removal of a pad oxide layer on the surface of a semiconductor substrate, wherein the sacrificial layer can be removed in an etching process with a first oxide layer after etching of a nitride layer is finished, the removal difficulty is low, an additional removal process is not required, and the influence on the performance of the device on the semiconductor substrate is small;
in the process of etching the nitride layer, the first oxide layer and the residual sacrificial layer are used as etching stop layers, and the thickness of the sacrificial layer is larger than that of the pad oxide layer, so that the problem that the nitride layer is etched to the semiconductor substrate during etching can be effectively avoided, the damage to the semiconductor substrate during etching the nitride layer is reduced, and the reliability of the SONOS memory is improved;
and (III) the thickness of the sacrificial layer can be adjusted in the generation process, the process window of the nitride layer etching can be enlarged by increasing the thickness of the sacrificial layer, and the process stability is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A method for manufacturing a SONOS memory is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a shallow trench isolation structure and an active area limited by the shallow trench isolation structure are arranged in the semiconductor substrate, the active area comprises a storage tube area, a selection tube area and a peripheral logic area, well injection is performed on the storage tube area, the selection tube area and the peripheral logic area, and a pad oxide layer covers the surface of the semiconductor substrate;
removing the pad oxide layer, and generating a sacrificial layer on the surface of the semiconductor substrate, wherein the thickness of the sacrificial layer is greater than that of the pad oxide layer;
removing the sacrificial layer in the storage tube region;
depositing a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate in sequence, wherein the first oxide layer covers the remaining sacrificial layer and the semiconductor substrate exposed out of the storage tube region, the nitride layer covers the first oxide layer, and the second oxide layer covers the nitride layer;
removing the second oxide layer; and
and removing the nitride layer and the first oxide layer from the selection pipe area and the peripheral logic area, and removing the rest of the sacrificial layer.
2. The method of claim 1, wherein the step of forming the sacrificial layer on the surface of the semiconductor substrate comprises performing a low pressure base oxidation process, a chemical vapor deposition process, or a furnace oxidation process.
3. The method of claim 1, wherein prior to removing the pad oxide layer, the method further comprises performing a device well implant process and performing a threshold voltage tuning ion implant process in the peripheral logic region.
4. The method of fabricating the SONOS memory device of claim 3, wherein after the step of forming the sacrificial layer on the surface of the semiconductor substrate and before the step of removing the sacrificial layer in the region of the memory tube, the method further comprises: and performing an ion implantation process for adjusting the threshold voltage of the control gate in the storage tube region.
5. The method of fabricating the SONOS memory device of claim 1, wherein removing the nitride layer and the first oxide layer from portions of the select tube region and the peripheral logic region comprises:
forming a mask covering the storage tube region on the semiconductor substrate;
performing an etching process to remove the portions of the nitride layer located in the select transistor region and the peripheral logic region, wherein the first oxide layer and the remaining sacrificial layer are used as an etching stop layer; and
and removing the first oxide layer and the remaining sacrificial layer.
6. The method of fabricating the SONOS memory device of claim 5, wherein removing the portions of the nitride layer located in the select transistor region and the peripheral logic region employs a wet etching process and a dry etching process performed in sequence; and removing the first oxide layer and the rest sacrificial layer by adopting a wet etching process.
7. The method of fabricating the SONOS memory device of any one of claims 1 to 6, wherein the removing the sacrificial layer of the memory tube region comprises:
sequentially forming a bottom anti-reflection layer and a photoresist layer on the semiconductor substrate;
carrying out patterning treatment on the photoresist layer to expose the bottom anti-reflection layer of the storage tube region;
removing the exposed bottom anti-reflection layer to expose the sacrificial layer of the storage tube region; and
removing the sacrificial layer in the region of the storage tube.
8. The method of fabricating the SONOS memory device of any one of claims 1 to 6, wherein after removing the sacrificial layer of the memory tube region and before depositing the first oxide layer, the nitride layer and the second oxide layer, the method further comprises:
and pre-cleaning the surface of the semiconductor substrate, and removing a natural oxidation layer on the surface of the semiconductor substrate in the storage tube area.
9. The method of fabricating the SONOS memory device of any one of claims 1 to 6, wherein the sacrificial layer has a thickness of
The sacrificial layer is silicon oxide.
10. The method of one of claims 1 to 6, wherein removing the pad oxide layer is performed using a BOE solution or a hydrofluoric acid solution.
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| CN114927465A (en) * | 2022-07-19 | 2022-08-19 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
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