CN110750303B

CN110750303B - Pipelined instruction reading method and device based on FPGA

Info

Publication number: CN110750303B
Application number: CN201910913484.1A
Authority: CN
Inventors: 潘国振; 魏长征; 闫莺
Original assignee: Alipay Hangzhou Information Technology Co Ltd
Current assignee: Ant Blockchain Technology Shanghai Co Ltd
Priority date: 2019-09-25
Filing date: 2019-09-25
Publication date: 2020-10-20
Anticipated expiration: 2039-09-25
Also published as: WO2021057141A1; CN110750303A

Abstract

One or more embodiments of the present specification provide a pipelined instruction reading method and apparatus based on an FPGA, where the method may include: an on-chip processor on an FPGA chip determines a code program to be executed, wherein the on-chip processor is formed by loading a deployed circuit logic configuration file on an FPGA structure to which the FPGA chip belongs, and the code program corresponds to an intelligent contract of transaction call received by a block chain link point to which the FPGA structure belongs; and the on-chip processor analyzes the end bit of the non-fixed length operation instruction contained in the data segment read each time in the process of sequentially reading the data contained in the code program according to the preset length so as to enable the data segment read next time to be adjacent to the end bit.

Description

Pipelined instruction reading method and device based on FPGA

Technical Field

One or more embodiments of the present disclosure relate to the field of block chain technologies, and in particular, to a pipelined instruction reading method and apparatus based on an FPGA.

Background

The blockchain technique is built on top of a transport network, such as a point-to-point network. Network nodes in a transport network utilize a chained data structure to validate and store data and employ a distributed node consensus algorithm to generate and update data.

The two biggest challenges in the current enterprise-level blockchain platform technology are privacy and performance, which are often difficult to solve simultaneously. Most solutions trade privacy for loss of performance or do not consider privacy much to pursue performance. Common encryption technologies for solving privacy problems, such as Homomorphic encryption (Homomorphic encryption) and Zero-knowledge proof (Zero-knowledge proof), have high complexity and poor universality, and may cause serious performance loss.

Trusted Execution Environment (TEE) is another way to address privacy concerns. The TEE can play a role of a black box in hardware, a code and data operating system layer executed in the TEE cannot be peeped, and the TEE can be operated only through an interface defined in advance in the code. In the aspect of efficiency, due to the black box property of the TEE, plaintext data is operated in the TEE instead of complex cryptography operation in homomorphic encryption, and the efficiency of the calculation process is not lost, so that the safety and privacy of a block chain can be improved to a great extent on the premise of small performance loss by combining with the TEE. The industry is concerned with TEE solutions, and almost all mainstream chip and Software consortiums have their own TEE solutions, including Software-oriented TPM (Trusted Platform Module) and hardware-oriented Intel SGX (Software Guard Extensions), ARM Trustzone (Trusted zone), and Platform Security Processor (Platform Security Processor).

Disclosure of Invention

In view of this, one or more embodiments of the present disclosure provide a pipelined instruction reading method and apparatus based on an FPGA.

To achieve the above object, one or more embodiments of the present disclosure provide the following technical solutions:

according to a first aspect of one or more embodiments of the present specification, there is provided an FPGA-based pipelined instruction reading method, including:

an on-chip processor on an FPGA chip determines a code program to be executed, wherein the on-chip processor is formed by loading a deployed circuit logic configuration file on an FPGA structure to which the FPGA chip belongs, and the code program corresponds to an intelligent contract of transaction call received by a block chain link point to which the FPGA structure belongs;

and the on-chip processor analyzes the end bit of the non-fixed length operation instruction contained in the data segment read each time in the process of sequentially reading the data contained in the code program according to the preset length so as to enable the data segment read next time to be adjacent to the end bit.

According to a second aspect of one or more embodiments of the present specification, there is provided an FPGA-based pipelined instruction reading apparatus, comprising:

the system comprises a determining unit, a processing unit and a processing unit, wherein the determining unit enables an on-chip processor on an FPGA chip to determine a code program to be executed, the on-chip processor is formed by loading a deployed circuit logic configuration file on an FPGA structure to which the FPGA chip belongs by the FPGA chip, and the code program corresponds to an intelligent contract of transaction call received by a block chain link point to which the FPGA structure belongs;

and the analysis unit is used for analyzing the end bit of the non-fixed length operation instruction contained in the data segment read each time in the process of sequentially reading the data contained in the code program according to the preset length by the on-chip processor so as to enable the data segment read next time to be adjacent to the end bit.

According to a third aspect of one or more embodiments of the present specification, there is provided an electronic apparatus including:

a processor;

a memory for storing processor-executable instructions;

wherein the processor implements the method of the first aspect by executing the executable instructions.

According to a fourth aspect of one or more embodiments of the present description, a computer-readable storage medium is presented, having stored thereon computer instructions which, when executed by a processor, implement the steps of the method according to the first aspect.

Drawings

Fig. 1 is a flowchart of a pipelined instruction reading method based on an FPGA according to an exemplary embodiment.

Fig. 2 is a schematic structural diagram of a blockchain node according to an exemplary embodiment.

Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip according to an exemplary embodiment.

FIG. 4 is a schematic diagram of a pipelined fetch of operational instructions in accordance with an illustrative embodiment.

Fig. 5 is a block diagram of an FPGA-based pipelined instruction fetch apparatus according to an example embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with one or more embodiments of the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of one or more embodiments of the specification, as detailed in the claims which follow.

It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily performed in the order shown and described herein. In some other embodiments, the method may include more or fewer steps than those described herein. Moreover, a single step described in this specification may be broken down into multiple steps for description in other embodiments; multiple steps described in this specification may be combined into a single step in other embodiments.

Blockchains are generally divided into three types: public chain (Public Blockchain), private chain (PrivateBlockchain) and alliance chain (Consortium Blockchain). In addition, there are various types of combinations, such as private chain + federation chain, federation chain + public chain, and other different combinations. The most decentralized of these is the public chain. The public chain is represented by bitcoin and ether house, and the participators joining the public chain can read the data record on the chain, participate in transaction, compete for accounting right of new blocks, and the like. Furthermore, each participant (i.e., node) is free to join and leave the network and perform related operations. Private chains are the opposite, with the network's write rights controlled by an organization or organization and the data read rights specified by the organization. Briefly, a private chain can be a weakly centralized system with strictly limited and few participating nodes. This type of blockchain is more suitable for use within a particular establishment. A federation chain is a block chain between a public chain and a private chain, and "partial decentralization" can be achieved. Each node in a federation chain typically has a physical organization or organization corresponding to it; participants jointly maintain blockchain operation by authorizing to join the network and forming a benefit-related alliance.

Whether public, private, or alliance, nodes in a blockchain network may perform received transactions within a TEE (Trusted Execution Environment) for privacy protection purposes through a solution in which the blockchain is combined with the TEE. The TEE is a trusted execution environment that is based on a secure extension of the CPU hardware and is completely isolated from the outside. TEE was originally proposed by Global Platform to address the secure isolation of resources on mobile devices, providing a trusted and secure execution environment for applications parallel to the operating system. The Trust Zone technology of ARM realizes the real commercial TEE technology at the earliest. Along with the rapid development of the internet, the security requirement is higher and higher, and more requirements are provided for the TEE by mobile equipment, cloud equipment and a data center. The concept of TEE has also been developed and expanded at a high rate. The concept now referred to as TEE has been a more generalized TEE than the concept originally proposed. For example, server chip manufacturers Intel, AMD, etc. have introduced hardware-assisted TEE in turn and enriched the concept and characteristics of TEE, which have gained wide acceptance in the industry. The mention of TEE now is more generally directed to such hardware assisted TEE techniques.

Taking the Intel SGX technology as an example, SGX provides an enclosure (also called enclave), that is, an encrypted trusted execution area in memory, and a CPU protects data from being stolen. Taking the example that the first block link point adopts a CPU supporting SGX, a part of an area EPC (enclosure Page Cache, Enclave Page Cache, or Enclave Page Cache) may be allocated in the memory by using a newly added processor instruction, and data therein is encrypted by an Encryption engine mee (memory Encryption engine) in the CPU. The encrypted content in the EPC is decrypted into plaintext only after entering the CPU. Therefore, in the SGX, a user may not trust an operating System, a VMM (Virtual Machine Monitor), or even a BIOS (basic input Output System), and only need to trust the CPU to ensure that private data is not leaked. The enclosure thus corresponds to the TEE produced under SGX technology.

Unlike the mobile terminal, the cloud access requires remote access, and the end user is not visible to the hardware platform, so the first step of using the TEE is to confirm the authenticity and credibility of the TEE. For example, a remote attestation mechanism for the SGX techniques described above is provided in the related art to prove that the SGX platform on the target device deploys the same configuration file as the challenger. However, since the TEE technology in the related art is implemented in software or a combination of software and hardware, even though a remote attestation method may indicate to some extent that the configuration file deployed in the TEE is not tampered with, the operating environment on which the TEE itself depends cannot be verified. For example, on a blockchain node which needs to implement a privacy function, a virtual machine for executing an intelligent contract needs to be configured in the TEE, and the instruction executed by the virtual machine is not directly executed, but actually executes a corresponding number of X86 instructions (assuming that the target device adopts an X86 architecture), thereby posing a certain security risk.

Therefore, the present specification proposes a hardware TEE technique implemented based on an FPGA, where the FPGA implements the hardware TEE by loading a circuit logic configuration file. Because the contents of the circuit logic configuration file can be viewed and checked in advance, and the FPGA is configured to operate completely based on the logic recorded in the circuit logic configuration file, the hardware TEE realized by the FPGA can be ensured to have relatively higher safety. Meanwhile, the execution efficiency of the code program can be improved by improving the instruction reading mode of the code program in the specification.

The following describes a pipelined instruction reading method based on an FPGA according to an embodiment to improve execution efficiency of a code program.

Fig. 1 is a flowchart of a pipelined instruction reading method based on an FPGA according to an exemplary embodiment. As shown in fig. 1, the method applied to the FPGA structure may include the following steps:

step 102, an on-chip processor on an FPGA chip determines a code program to be executed, the on-chip processor is formed by loading a deployed circuit logic configuration file on an FPGA structure to which the FPGA chip belongs, and the code program corresponds to an intelligent contract of transaction call received by a block chain link point to which the FPGA structure belongs.

The FPGA chip comprises a plurality of editable hardware logic units, and the hardware logic units can be realized as corresponding functional modules after being configured by a circuit logic configuration file so as to realize corresponding logic functions. Specifically, the circuit logic configuration file may be burned into the FPGA fabric based on the form of the bit stream. For example, the above-mentioned on-chip processor and the like are formed by a deployed circuit logic configuration file, and by further deploying relevant other functional modules, the FPGA structure can be configured as a hardware TEE on a blockchain node. Since the functional modules are completely configured by the circuit logic configuration file, the information of all aspects such as logic and the like realized by the configured functional modules can be determined by checking the circuit logic configuration file, and the functional modules can be ensured to be formed and operated according to the requirements of complete users. For example, the virtual machine logic may include an execution logic of an ethernet virtual machine or an execution logic of a WASM virtual machine, and the description does not limit this.

After the user generates the circuit logic configuration file, if the circuit logic configuration file is located at the site of the FPGA structure, the circuit logic configuration file may be locally deployed to the FPGA structure, for example, the deployment operation may be performed in an offline environment to ensure security. Alternatively, a user may remotely deploy the circuit logic configuration file to the FPGA fabric in the case where the FPGA fabric is in an online environment.

The FPGA structure can obtain the contract address of the intelligent contract called by the transaction by analyzing the to field of the transaction, and obtains the code program of the corresponding intelligent contract based on the contract address. If the transaction is encrypted by the transaction initiator and then submitted to the blockchain, the FPGA fabric needs to decrypt the transaction to read the to field information. And a decryption module can be formed on the FPGA chip by loading the deployed circuit logic configuration file, so that the transaction is decrypted by the decryption module.

For example, the FPGA fabric may be maintained with a node private key, and a node public key corresponding to the node private key is published. Then, the transaction initiator may obtain the node public key, and may generate a symmetric key by itself, and perform an encryption operation in the form of a digital envelope on the plaintext transaction content based on the node public key and the symmetric key: the plaintext transaction content is encrypted through the symmetric key to obtain ciphertext transaction content, the symmetric key is encrypted through the node public key to obtain a ciphertext symmetric key, and the transaction comprises the ciphertext transaction content and the ciphertext symmetric key. Correspondingly, the decryption module can decrypt the ciphertext symmetric key contained in the transaction based on the node private key to obtain the symmetric key, and then the decryption module can decrypt the ciphertext transaction content based on the symmetric key to obtain the plaintext transaction content, so that the to field information is read from the plaintext transaction content, and the contract address of the intelligent contract called by the transaction is determined.

If the code program corresponding to the contract address can be deployed at the block link point, the FPGA structure needs to perform data interaction with the block link point, for example, send the contract address to the block link point, and receive the code program returned by the block link point. If the code program corresponding to the contract address is deployed in the local space of the FPGA structure, compared with the interaction with the block link point, the FPGA structure can acquire the code program from the local space, so that the resource efficiency is saved, and the waiting time is shortened. The local space may include an on-chip storage space formed on the FPGA chip, or an external storage space outside the FPGA chip, for example, the external storage space may include an external DDR plugged in the FPGA structure.

And 104, in the process of sequentially reading the data contained in the code program according to the preset length, the on-chip processor analyzes the end bit of the non-fixed length operation instruction contained in the data segment read each time so as to enable the data segment read next time to be adjacent to the end bit.

When the on-chip processor performs a read operation on the code program each time, the on-chip processor always reads the data segment with the same length (i.e. the preset length), so that the on-chip processor can improve the data reading efficiency. For example, the on-chip processor may read one data segment per clock cycle and implement pipelined processing operations with respect to the operation instructions contained in the read data segment, thereby executing one operation instruction contained in one data segment per clock cycle as much as possible.

Since the operation instruction contained in the code program is not fixed length (i.e. not fixed length), the on-chip processor cannot read the data segment based on the preset length only, otherwise the operation instruction may be truncated. For example, the length of the first operation instruction is 3B, the length of the second operation instruction is B, and the length of the third operation instruction is 2B, if the preset length is 2B, the first operation instruction cannot be completely intercepted, and therefore the preset length should not be less than the maximum length of a single operation instruction in the code program, so as to ensure that the data segment read each time can certainly and completely contain one operation instruction; and assuming that the maximum length of a single operation instruction is 5B, when the data segment is read according to the preset length of 5B, the data segment read for the first time not only comprises the first operation instruction, but also comprises a second operation instruction and a part of a third operation instruction, if the second data segment reading operation is carried out directly after the data segment read for the first time, the second operation instruction cannot be read, the third operation instruction cannot be completely read, and therefore the code program cannot be correctly executed.

Therefore, the on-chip processor can determine the end bit of the contained operation instruction by analyzing the data segment read each time, so that the data segment read next time is adjacent to the end bit instead of the data segment read last time. For example, in the above example, although the data segment with the length of 5B is read for the first time, the length of the first operation instruction may be analytically determined to be 3B, and then, when the data segment is read for the second time, it may be ensured that the data segment with the length of 5B is read backward from after the first operation instruction, so as to ensure that the read data segment contains the second operation instruction; similarly, the length of the second operation instruction is determined to be B by analyzing the data segment read for the second time, and when the data segment is read for the third time, it is ensured that the data segment with the length of 5B is read backward from the beginning after the second operation instruction, so as to ensure that the read data segment contains the third operation instruction, and so on. Therefore, based on the scheme, the data segment can be correctly read by the on-chip processor according to the fixed preset length each time under the condition that the operation instruction has the non-fixed length, so that the reading efficiency of the operation instruction is improved, and the execution efficiency of the code program is accelerated.

Each operation instruction contained in the code program contains an operation code indicating the type of operation that needs to be performed. Further, some of the operation instructions may contain operands, i.e., these operation instructions contain associated opcodes and operands, which are parameters when the respective opcodes are executed; the operation instruction may include one or more operands, typically 1 or 2 operands. It can be seen that the length of different operation instructions is not fixed because the operation instructions may or may not contain operands and the number of contained operands is not fixed, thereby forming the non-fixed-length operation instruction. In addition, there are other factors that may cause the length of the operation instruction to be non-fixed. For example, in the byte code employed by the intelligent contract, the length of each operand is typically fixed, such as 4B or 8B based on the different value types. However, if the operand is an encoded operand, such as the LEB (Little-Endian Base) encoding commonly used in the wasm bytecode program, the length of the encoded operand may vary, typically 2B or 4B, and may be 5B at most.

Each operation instruction has an operation code with a fixed length, for example, the length of each operation code in the byte code is 1B. When the on-chip processor reads the data segment, the first data segment is bound to start from the initial address of the first operation instruction, and the length of the operation code is fixed, so that the on-chip processor can analyze the operation code of the non-fixed length operation instruction contained in the first read data segment, and determine whether the operation code has a corresponding operand and the number of the corresponding operand according to the analysis result; the on-chip processor determines the last bit of the last operand as the end bit of the non-fixed length operation instruction according to the number of the contained operands and the length of each operand under the condition that the non-fixed length operation instruction contains the operands based on the operation code; and in the case that the on-chip processor determines that the non-fixed-length operation instruction does not contain the operand based on the operation code, taking the last bit of the operation code as the end bit of the non-fixed-length operation instruction. Then, the on-chip processor can ensure that the next read data segment inevitably starts from the start address of the second operation instruction based on the end bit determined in the above manner, so as to ensure that the on-chip processor can successfully analyze the operation code of the second operation instruction, and determine whether the operation code has the corresponding operand and the number of the corresponding operands according to the analysis result, thereby determining the end bit of the second operation instruction; and so on.

Fig. 2 is a schematic structural diagram of a blockchain node according to an exemplary embodiment. Based on the technical solution of the present specification, an FPGA structure may be added to a block chain node to implement the hardware TEE, for example, the FPGA structure may be an FPGA board card as shown in fig. 2. The FPGA board card can be connected to the block link nodes through the PCIE interface so as to realize data interaction between the FPGA board card and the block link nodes. The FPGA board card can comprise structures such as an FPGA chip, a Flash chip, a close-pipe chip and the like; of course, in some embodiments, only a portion of the remaining Flash chips, the crypto-chips, and the like may be included, or more structures may be included, in addition to the FPGA chip, which is only used for example.

In the initial stage, no logic defined by a user is burned on the FPGA chip, which is equivalent to that the FPGA chip is in a blank state. A user can form corresponding functions or logics on the FPGA chip by burning a circuit logic configuration file on the FPGA chip. When a circuit logic configuration file is burned for the first time, the FPGA board card does not have a safety protection capability, so that a safety environment is usually provided externally, for example, a user can burn the circuit logic configuration file in an offline environment to realize physical safety isolation, rather than remotely burn on line.

And aiming at the functions or logics required to be realized by the user, corresponding logic codes can be formed through an FPGA hardware language, and the logic codes are subjected to mirroring treatment, so that the circuit logic configuration file can be obtained. Before burning the logic codes to the FPGA board card, a user can check the logic codes. Particularly, when a plurality of users are involved at the same time, the logic codes can be checked by the plurality of users respectively, so that the FPGA board card can meet the requirements of all the users finally, and abnormal problems such as security risk, logic errors and fraud are prevented.

After determining that the code is correct, the user can burn the circuit logic configuration file to the FPGA board card in the off-line environment. Specifically, the circuit logic configuration file is transmitted from the block link point to the FPGA board, and is further deployed in the Flash chip shown in fig. 2, so that even if the FPGA board is powered off, the Flash chip can still store the circuit logic configuration file.

Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip according to an exemplary embodiment. By loading the circuit logic configuration file deployed in the Flash chip to the FPGA chip, the hardware logic unit included in the FPGA chip can be configured, so that a corresponding functional module is formed on the FPGA chip, for example, the formed functional module may include an on-chip cache module, a plaintext calculation module, a key negotiation module, a decryption and signature verification module, an encryption and decryption module, and the like shown in fig. 3. Meanwhile, the circuit logic configuration file can also be used for transmitting information to be stored to the FPGA board card, for example, a preset certificate can be stored on the FPGA chip, an authentication root key can be stored in the crypto-tube chip (the authentication root key can also be stored on the FPGA chip), and the like.

Based on a key agreement module formed on the FPGA chip and an authentication root key deployed on the FPGA board, the FPGA board can implement remote key agreement with a user, and the key agreement process can be implemented by using any algorithm or standard in the related art, which is not limited in this specification. By way of example, the key agreement procedure may include: the user can generate a key Ka-1 at a local client, the key negotiation module can generate a key Kb-1 at the local client, the client can calculate key negotiation information Ka-2 based on the key Ka-1, the key negotiation module can calculate key negotiation information Kb-2 based on the key Kb-1, then the client sends the key negotiation information Ka-2 to the key negotiation module, the key negotiation module sends the key negotiation information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key negotiation information Kb-2, the key negotiation module can generate the same secret value based on the key Kb-1 and the key negotiation information Ka-2, and finally the client and the key negotiation module derive the same configuration file deployment key from the same secret value based on a key derivation function respectively, the configuration file deployment key can be stored in an FPGA chip or a close-pipe chip. In the above process, although the key agreement information Ka-2 and the key agreement information Kb-2 are transmitted between the client and the key agreement module via the block chain node, since the key Ka-1 is grasped by the client and the key Kb-1 is grasped by the key agreement module, it can be ensured that the block chain node cannot acquire the finally obtained secret value and the configuration file deployment key, thereby avoiding the security risk that may be caused.

In addition to the configuration file deployment key, the secret value is used to derive a business secret deployment key; for example, the secret value may derive a 32-bit value, and the first 16 bits may be used as a configuration file deployment key and the last 16 bits may be used as a service secret deployment key. The user can deploy the service key to the FPGA card through the service secret deployment key, for example, the service key may include a node private key and a service root key. For example, a user can sign and encrypt the node private key or the service root key by using the service secret deployment key on the client, and send the signed and encrypted service root key to the FPGA board, so that the FPGA board deploys the obtained node private key or the service root key after decrypting and verifying the signature by the decryption and verification module.

Based on the deployed node key, the service root key, the encryption and decryption module on the FPGA chip and the plaintext calculation module, the FPGA board card can be realized as TEE on block chain link points to meet privacy requirements. For example, when a block link point receives a transaction, if the transaction is a plaintext transaction, the block link point may directly process the plaintext transaction, and if the transaction is a privacy transaction, the block link point may transmit the privacy transaction to the FPGA board for processing.

The transaction content of the clear text transaction is in a clear text form, and the contract state and the like generated after the transaction is executed are stored in a clear text form. The transaction content of the privacy transaction is in a ciphertext form, the transaction initiator encrypts the plaintext transaction content to obtain the encrypted plaintext transaction content, and contract states and the like generated after the transaction is executed need to be stored in the ciphertext form, so that the transaction privacy protection is ensured. For example, the transaction initiator may generate a symmetric key randomly or based on other manners, and similarly, the service public key corresponding to the service private key is disclosed, then the transaction initiator may perform digital envelope encryption on the plaintext transaction content based on the symmetric key and the service public key: the transaction initiator encrypts plaintext transaction content through a symmetric key, and encrypts the symmetric key through a service public key to obtain two parts of content which are both contained in the privacy transaction; in other words, the privacy transaction includes two parts: the clear text transaction content encrypted by adopting the symmetric key and the symmetric key encrypted by adopting the service public key.

Therefore, after receiving the private transaction transmitted by the block chain link point, the FPGA board can decrypt the symmetric key encrypted by the service public key through the service private key by the encryption and decryption module to obtain the symmetric key, and then decrypt the plaintext transaction content encrypted by the symmetric key through the symmetric key by the encryption and decryption module to obtain the plaintext transaction content. The private transaction may be used to deploy an intelligent contract, and then the data field of the content of the clear text transaction may contain the contract code of the intelligent contract to be deployed; alternatively, the private transaction may be used to invoke an intelligent contract, and then the to field of the plaintext transaction content may contain a contract address of the invoked intelligent contract, and the FPGA board may invoke a corresponding contract code based on the contract address.

The on-chip caching module may be to cache contract code and/or contract states to which the contract code relates. In some cases, the FPGA card may have an external DDR to which the contract code and/or the contract state to which the contract code relates may be stored. Of course, the contract code and/or the contract state to which the contract code relates may also be stored at a block link point. In contrast, the memory space of the external DDR is often larger or even much larger than that of the on-chip cache module, so that the external DDR can help to cache more data. Certainly, the FPGA board may include both the on-chip cache module and the external DDR, for example, the contract code with relatively higher heat rate may be cached in the on-chip cache module, and the contract code with relatively lower heat rate may be maintained in the external DDR. Compared with the block chain points, the on-chip cache module and the external DDR can be regarded as the local space of the FPGA board card, and the resource amount and the time consumed by data interaction with the local space are far less than those of the data interaction process between the on-chip cache module and the external DDR and the block chain points, so that the execution efficiency of the intelligent contract is improved.

The plaintext calculation module formed on the FPGA chip is used for realizing the logic of the virtual machine in the related technology, namely the plaintext calculation module is equivalent to a hardware virtual machine on the FPGA board card. Thus, after the contract code is determined based on the plaintext transaction content, the contract code may be passed into a plaintext calculation module for execution by the plaintext calculation module. The plaintext calculation module corresponds to an on-chip processor formed on an FPGA chip in this specification.

The process of executing the contract code by the plaintext calculation module can be decomposed into a process of reading and executing each operation instruction contained in the contract code. For example, FIG. 4 is a schematic diagram illustrating a pipelined fetch of operational instructions in accordance with an illustrative embodiment. As shown in fig. 4, it is assumed that the code program of the contract code includes a plurality of operation instructions, a first operation instruction includes an operation code P1 and an operand Q1, a second operation instruction includes an operation code P2 and operands Q21, Q22, a third operation instruction includes an operation code P3 and operands Q31, Q32, a fourth operation instruction includes an operation code P4, a fifth operation instruction includes an operation code P5, and the like. Assuming that the code program is a wasm bytecode program, each opcode is 1B in length, each operand is LEB encoded, is typically 2B or 4B in length and does not exceed 5B at most, and each operation instruction contains a maximum of 2 operands. Accordingly, it can be determined that each operation instruction in the present embodiment includes at most 1 opcode and 2 operands, and that each operation instruction has a length of at most 1+2 × 5 — 11B, that is, 88B.

Therefore, during the read operation instruction, the plaintext calculation module may set that the read operation is performed once every clock cycle and the data segment with the length of 88b is read each time. For example, as shown in fig. 4, in the first clock cycle C1, the plaintext calculation module reads a data segment with a length of 88b, which is the first data segment, and therefore the data segment must start with an operation code, so that the plaintext calculation module can directly read the operation code P1, which is the data of the first Byte of the data segment, and parse and determine the operand corresponding to the operation code P1. The plaintext calculation module may determine, based on the parsing result: the opcode P1 has 1 operand, the Q1 described above, and the length of the operand is 2B; and the plaintext calculation module may determine the ending bit of the operation instruction included in the data segment read in clock cycle C1, and in the second clock cycle C2, the plaintext calculation module may read the data segment with the length of 88b from the next bit of the ending bit.

Since the end bit in the data segment read in the clock cycle C1 is accurately analyzed, the data segment read by the plaintext calculation module in the clock cycle C2 must start with the opcode of the second operation instruction. Therefore, in a similar manner as described above, the plaintext calculation module may analyze the data segment read in the clock cycle C2 to determine that there are two operands with a length of 2B in the operation code P2 included in the data segment, i.e., the operands Q21 and Q22, thereby determining the end bit of the operation instruction included in the data segment read in the clock cycle C2, and further, in the third clock cycle C3, the plaintext calculation module may read the data segment with a length of 88B from the next bit of the end bit.

It can be seen that, since the plaintext calculation module can accurately analyze the end bit of the operation instruction included in the read data segment, the data segment in the code program can be sequentially intercepted according to the fixed length in each clock cycle, which is helpful for improving the reading efficiency of the code program and accelerating the execution speed of the intelligent contract.

For some reasons, a user may wish to perform version update on a circuit logic configuration file deployed on an FPGA board, for example, an authentication root key included in the circuit logic configuration file may be known by a risky user, and for example, the user may wish to upgrade a functional module deployed on the FPGA board, which is not limited in this specification. For the sake of distinction, the circuit logic configuration file already deployed in the above process may be referred to as an old version of circuit logic configuration file, and the circuit logic configuration file to be deployed may be referred to as a new version of circuit logic configuration file.

Similar to the old version of the circuit logic configuration file, a user can generate a new version of the circuit logic configuration file through the processes of writing codes, mirroring and the like. Furthermore, a user can sign the new circuit logic configuration file through a private key owned by the user, and then encrypt the signed new circuit logic configuration file through a configuration file deployment key issued by the above-mentioned assistant, so as to obtain the encrypted new circuit logic configuration file. In some cases, multiple users may exist at the same time, and then the preset certificates corresponding to the users need to be deployed to the FPGA board card for the old version of circuit logic configuration file, and the users need to sign the new version of circuit logic configuration file by using their own private keys.

The user can remotely send the encrypted new circuit logic configuration file to the block chain nodes through the client, and the encrypted new circuit logic configuration file is further transmitted to the FPGA board card through the block chain nodes. In the process, the decryption and signature checking module formed on the FPGA chip is located on a transmission path between the PCIE interface and the Flash chip, so that the encrypted new version of circuit logic configuration file can be transmitted into the Flash chip to realize credible update after being successfully processed by the decryption and signature checking module, and the Flash chip cannot be directly updated by bypassing the decryption and signature checking process.

After receiving the encrypted new version circuit logic configuration file, the decryption and signature verification module decrypts the encrypted new version circuit logic configuration file by using the configuration file deployment key deployed on the FPGA board card, and if the decryption is successful, the decryption and signature verification module further performs signature verification on the decrypted new version circuit logic configuration file based on a preset certificate deployed on the FPGA chip. If the decryption fails or the signature verification fails, the received file is not from the user or is tampered, and the decryption signature verification module triggers to terminate the current updating operation; and under the conditions that decryption is successful and the verification passes, the obtained new version of circuit logic configuration file can be determined to come from the user and is not tampered in the transmission process, and the new version of circuit logic configuration file can be further transmitted to the Flash chip so as to update and deploy the old version of circuit logic configuration file in the Flash chip.

After the new circuit logic configuration file is loaded to the FPGA chip, information such as the plaintext calculation module, the on-chip cache module, the key negotiation module, the encryption/decryption module, the decryption and signature verification module, a preset certificate is stored into the FPGA chip, and an authentication root key is stored into the crypto-tube chip can be formed on the FPGA chip. The formed plaintext calculation module, on-chip cache module, key negotiation module, encryption/decryption module, decryption and signature verification module and the like can change and upgrade the realized function logic, and the stored information such as the deployed preset certificate, the authentication root key and the like can be different from the information before updating. Then, the FPGA board may perform remote negotiation with the user based on the updated key negotiation module, the authentication root key, and the like to obtain a new configuration file deployment key, and the configuration file deployment key may be used in a next updateable process. Similarly, trusted update operations for the FPGA board can be continuously implemented accordingly.

After the updating and the deployment are completed, the FPGA board card can generate an authentication result aiming at the new version circuit logic configuration file. For example, the key agreement module may calculate, by using an algorithm such as sm3 or another algorithm, a hash value of the new version of circuit logic configuration file, a hash value of the configuration file deployment key negotiated based on the new version of circuit logic configuration file, and the obtained calculation result may be used as the authentication result, and the key agreement module sends the authentication result to the user. Correspondingly, the user can verify the authentication result on the client based on the maintained new version circuit logic configuration file and the configuration file deployment key negotiated according to the new version circuit logic configuration file, if the verification is successful, the new version circuit logic configuration file is successfully deployed on the FPGA board card, and the user and the FPGA board card successfully negotiate according to the configuration file deployment key to obtain the consistent configuration file deployment key, so that the successful completion of the updating and the deployment aiming at the circuit logic configuration file is confirmed.

Fig. 5 is a schematic block diagram of an FPGA-based pipelined instruction fetch apparatus according to an exemplary embodiment. Referring to fig. 5, in a software implementation, the terminal interaction apparatus may include:

a determining unit 501, configured to enable an on-chip processor on an FPGA chip to determine a code program to be executed, where the on-chip processor is formed by loading a deployed circuit logic configuration file on an FPGA structure to which the FPGA chip belongs, and the code program corresponds to an intelligent contract for transaction call received by a block link node to which the FPGA structure belongs;

the parsing unit 502 is configured to, in the process of sequentially reading the data included in the code program according to a preset length, enable the on-chip processor to parse an end bit of a non-fixed-length operation instruction included in a data segment read each time, so as to enable a data segment read next time to be adjacent to the end bit.

Optionally, the preset length is not less than the maximum length of a single operation instruction in the code program.

Optionally, the parsing unit 502 is specifically configured to:

enabling the on-chip processor to analyze the operation code of the non-fixed length operation instruction contained in the data segment read each time;

causing the on-chip processor to determine a last bit of a last operand as an end bit of the non-fixed-length operation instruction according to the number of operands and the length of each operand in the case that the non-fixed-length operation instruction is determined to contain the operands based on the opcode;

causing the on-chip processor to treat a last bit of the opcode as an end bit of the non-fixed-length operation instruction if it is determined based on the opcode that the non-fixed-length operation instruction does not include an operand.

Optionally, the operand is an encoded operand encoded by the LEB.

Optionally, the reading, by the on-chip processor, data included in the code program includes:

and the on-chip processor reads the data contained in the code program in sequence according to the frequency of reading once per clock cycle.

Optionally, the code program comprises a bytecode program.

Optionally, the bytecode program includes a wasm bytecode program.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.

In a typical configuration, a computer includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in one or more embodiments of the present description to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of one or more embodiments herein. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

The above description is only for the purpose of illustrating the preferred embodiments of the one or more embodiments of the present disclosure, and is not intended to limit the scope of the one or more embodiments of the present disclosure, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the one or more embodiments of the present disclosure should be included in the scope of the one or more embodiments of the present disclosure.

Claims

1. A pipelined instruction reading method based on FPGA includes:

2. The method of claim 1, wherein the preset length is not less than a maximum length of a single operation instruction in the code program.

3. The method of claim 1, wherein the on-chip processor resolves an end bit of a non-fixed-length operation instruction contained in a data segment read each time, and comprises the following steps:

the on-chip processor analyzes the operation code of the non-fixed length operation instruction contained in the data segment read each time;

the on-chip processor determines the last bit of the last operand as the end bit of the non-fixed length operation instruction according to the number of contained operands and the length of each operand under the condition that the non-fixed length operation instruction is determined to contain the operands based on the operation code;

the on-chip processor takes a last bit of the opcode as an end bit of the non-fixed-length operation instruction if it is determined based on the opcode that the non-fixed-length operation instruction does not include an operand.

4. The method of claim 3, the operand being an LEB encoded operand.

5. The method of claim 1, the on-chip processor reading data contained in the code program, comprising:

6. The method of claim 1, the code program comprising a bytecode program.

7. The method of claim 6, the bytecode program comprising a wasm bytecode program.

8. A pipelined instruction reading device based on FPGA includes:

9. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor implements the method of any one of claims 1-8 by executing the executable instructions.

10. A computer readable storage medium having stored thereon computer instructions which, when executed by a processor, carry out the steps of the method according to any one of claims 1 to 8.