CN110739373A - Light-emitting diode chip with composite nucleation layer and preparation method thereof - Google Patents

Abstract

The invention provides a light-emitting diode chip with a composite nucleation layer and a preparation method. The chip includes a sapphire substrate, a _SiO2 pattern array with a specific shape is arranged on the sapphire substrate, and AlN nucleation is arranged on the _SiO2 pattern array. layer, an AlGaN layer is grown on the AlN nucleation layer, the AlN nucleation layer and the AlGaN layer form a composite nucleation layer, and the composite nucleation layer is epitaxially grown on the u-GaN layer, n-GaN layer, superlattice, multi-quantum Well active layer and p-GaN layer; specific shapes include arrays combined with two parts, one part is an inverted conical pattern on a sapphire substrate, and the other part is a conical protrusion on the inverted conical pattern or raised by a frustum A ring-shaped peak combined with an inverted conical depression. In the invention, the special pattern array is etched on the sapphire substrate, and the nucleation layer is sputtered on the special pattern array at the same time, and the composite nucleation layer is grown on the nucleation layer, so as to further reduce the crystal formation between the GaN and the sapphire substrate. dislocations generated by lattice mismatch, thereby improving the external quantum efficiency of light-emitting diodes.

Description

Light-emitting diode chip with composite nucleation layer and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor light-emitting diodes, and in particular relates to a light-emitting diode chip with a composite nucleation layer and a preparation method thereof.

Background technique

Light-emitting diodes have significant advantages such as high electro-optical conversion efficiency, environmental protection, low power consumption, long life, and easy maintenance. Semiconductor lighting based on light-emitting diodes is considered to be one of the most promising high-tech fields in the world in recent years. External quantum efficiency is an important parameter for evaluating LED chips, and external quantum efficiency is the product of internal quantum efficiency and light extraction efficiency.

The use of a sapphire patterned substrate and a _SiO2 patterned array can simultaneously improve the crystal quality of the GaN epitaxial layer grown on the substrate and the light extraction efficiency of the LED chip. The mismatch of lattice constants and thermal expansion coefficients between the sapphire substrate and the gallium nitride epitaxial layer results in a high dislocation density in the gallium nitride epitaxial layer, which affects the light extraction efficiency of the light-emitting diode. The patterned substrate can change the growth process of gallium nitride grains, suppress the extension of dislocations on the surface of the epitaxial layer, and improve the internal quantum efficiency of the LED chip. Most of the existing sapphire patterned substrates are convex conical or circular patterns, and the dislocation density needs to be further reduced.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a light-emitting diode chip with a composite nucleation layer and a preparation method thereof, which can improve the external quantum efficiency of the light-emitting diode chip.

The technical scheme adopted by the present invention to solve the above technical problems is: a light-emitting diode chip with a composite nucleation layer, characterized in that: the chip includes a sapphire substrate, and the sapphire substrate is provided with a SiO ₂ pattern array of a specific shape , an AlN nucleation layer is arranged on the _SiO2 pattern array, an AlGaN layer is grown on the AlN nucleation layer, the AlN nucleation layer and the AlGaN layer form a composite nucleation layer, and a u-GaN layer is epitaxially grown on the composite nucleation layer in turn , n-GaN layer, superlattice, multiple quantum well active layer and p-GaN layer;

The specific shape includes a combination of two parts of the array, one of which is an inverted conical pattern located on the sapphire substrate, and the other part is a conical protrusion located on the inverted conical pattern or a combination of a truncated conical protrusion and an inverted conical depression. Ring Peak.

According to the above solution, the top of the inverted cone pattern and the top surface of the sapphire substrate are on the same plane, and the conical protrusion or annular peak is located in the AlN nucleation layer.

According to the above scheme, the diameter of the cone base of the inverted cone pattern is 0.5-2.5μm, the height of the cone is 1.0-5.0μm, the angle between the cone generatrix and the bottom surface of the cone is 66.4°, and the spacing of the inverted cone pattern array is 0.5μm.

According to the above scheme, the diameter of the bottom surface of the conical protrusion is 0.5-2.5 μm, the height of the cone is 1.0-5.0 μm, and the angle between the cone generatrix and the diameter of the bottom surface is 66.4°.

According to the above scheme, in the annular peak, the diameter of the lower bottom surface of the truncated cone is 0.5-2.5 μm, the diameter of the upper bottom surface is 0.25-1.25 μm, the height of the truncated cone is 0.5-2.5 μm, and the angle between the busbar of the truncated cone and the diameter of the lower bottom surface is 0.5-2.5 μm. is 66.4°; the inverted conical depression takes the upper bottom surface of the convex circular platform as the conical bottom surface, and the center of the lower bottom surface of the convex circular platform is the apex.

According to the above scheme, the thickness of the AlN layer is 14-24 nm.

According to the above scheme, the thickness of the AlGaN layer is 2.5-3.0 μm.

The method for preparing a light-emitting diode chip is characterized in that: the method comprises the following steps:

S101, providing a plane sapphire substrate;

S102, performing an etching process on the sapphire substrate to form a pit array of the inverted conical pattern on the sapphire substrate;

S103, growing SiO ₂ on the sapphire substrate, so that the pit array of the inverted conical pattern is filled with SiO ₂ to form an array of inverted conical patterns, and a layer of SiO ₂ thin film is provided on the sapphire substrate;

S104, performing an etching process on the SiO ₂ thin film, leaving a conical protrusion or an annular peak composed of a circular truncated protrusion and an inverted conical depression on each inverted conical pattern to form a SiO ₂ pattern array;

S105, growing an AlN nucleation layer on the SiO ₂ pattern array;

S106, growing an AlGaN layer on the AlN nucleation layer to form a composite nucleation layer;

S107, epitaxially grow a u-GaN layer, an n-GaN layer, a superlattice, a multiple quantum well active layer and a p-GaN layer on the composite nucleation layer in sequence.

According to the above method, the etching process is an ICP etching process.

According to the above method, the PECVD technique is used for the growth, and the MOCVD technique is used for the epitaxial growth.

The beneficial effects of the invention are as follows: by etching a special pattern array on the sapphire substrate, an inclined interface is formed between SiO ₂ and GaN, the extension of dislocation can be suppressed, and the light extraction efficiency of the light-emitting diode can be effectively improved; The sputtering nucleation layer on the special pattern array can reduce the dislocation density in the nucleation layer, improve the crystal quality, and grow the composite nucleation layer on the nucleation layer, further reducing the lattice mismatch between GaN and sapphire substrate. The dislocation can effectively reduce the dislocation density of the epitaxial layer, thereby improving the external quantum efficiency of the light-emitting diode.

Description of drawings

FIG. 1 is a flowchart of a method according to an embodiment of the present invention.

FIG. 2 is a structural diagram of a chip according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of an array of inverted conical recess patterns etched on a sapphire substrate.

FIG. 4 is a schematic diagram of growing and etched biconical SiO ₂ pattern array on a sapphire pattern substrate.

Figure 5 is a cross-sectional view of a biconical _SiO2 pattern array.

FIG. 6 is a schematic diagram of growing an etched annular peak-inverted conical SiO ₂ pattern array on a sapphire pattern substrate.

Figure 7 is a cross-sectional view of an annular peak-inverted conical _SiO2 pattern array.

In the picture: 201-sapphire substrate, 202- _SiO2 pattern array, 203-AlN nucleation layer, 204-AlGaN layer, 205-u-GaN layer, 206-n-GaN layer, 207-superlattice, 208- Multiple quantum well active layer, 209-p-GaN layer, 202-1-inverted cone pattern, 202-2-conical protrusion, 202-3-ring peak.

Detailed ways

The present invention will be further described below with reference to specific examples and accompanying drawings.

The present invention provides a light-emitting diode chip with a composite nucleation layer. As shown in FIG. ₂ , the chip includes a sapphire substrate 201. The sapphire substrate 201 is provided with a _SiO2 pattern array 202 with a specific shape. 202 is provided with an AlN nucleation layer 203, an AlGaN layer 204 is grown on the AlN nucleation layer 203, the AlN nucleation layer 203 and the AlGaN layer 204 form a composite nucleation layer, and a u-GaN layer is epitaxially grown on the composite nucleation layer in turn 205 , n-GaN layer 206 , superlattice 207 , multiple quantum well active layer 208 and p-GaN layer 209 . The specific shape includes a combination of two parts of the array, one of which is an inverted conical pattern located on the sapphire substrate 201, and the other part is a conical protrusion located on the inverted conical pattern or a combination of a truncated conical protrusion and an inverted conical depression. ring peak.

Further, the top of the inverted conical pattern and the top surface of the sapphire substrate 201 are on the same plane, and the conical protrusions or annular peaks are located in the AlN nucleation layer 203 .

As shown in Figure 1, the preparation method of the above-mentioned light-emitting diode chip is as follows:

S101, providing a planar sapphire substrate 201.

S102 , performing an etching process on the sapphire substrate 201 to form a pit array of the inverted conical pattern 202 - 1 on the sapphire substrate, as shown in FIG. 3 .

Specifically, a photoresist is spin-coated on the sapphire substrate 201, and the photoresist is exposed to a gray scale by using a laser direct writing technology. Using an ICP (Inductively Coupled Plasma: ICP) etching process, the sapphire substrate 201 is etched, and a pattern is transferred to the sapphire substrate 201 . Optionally, the thickness of the spin-on photoresist is 1.5-5.0 μm.

Optionally, the diameter of the cone base is 0.5-2.5 μm, the height of the cone is 1.0-5.0 μm, the angle between the cone generatrix and the cone base is 66.4°, and the pattern spacing is 0.5 μm.

S103, growing SiO ₂ on the sapphire substrate 201, so that the pit array of the inverted conical pattern 202-1 is filled with SiO ₂ to form an array of inverted conical patterns 202-1, and the sapphire substrate With a layer of _SiO2 film. In this embodiment, a plasma-enhanced chemical vapor deposition (PECVD) technique is used to grow a SiO ₂ film with a thickness of 1.0-5.0 μm.

S104, performing an etching process on the SiO ₂ thin film, leaving a conical protrusion 202-2 or an annular peak 202-3 composed of a circular truncated protrusion and an inverted conical depression on each inverted conical pattern 202-1 to form SiO ₂ Graphics array 202; as shown in Figures 4-7.

Specifically, a photoresist is spin _- coated on the SiO ₂ film, and the photoresist is exposed to a grayscale by using the laser direct writing technology. Photoresist mask pattern. Optionally, the thickness of the spin-on photoresist is 1.5-5.0 μm.

In the conical protrusion 202-2, optionally, the diameter of the conical bottom surface is 0.5-2.5 μm, the height of the conical protrusion is 1.0-5.0 μm, the angle between the conical generatrix and the bottom diameter is 66.4°, the The conical protrusions 202-2 and the inverted conical pattern 202-1 etched on the sapphire pattern substrate 201 form a double-cone SiO ₂ pattern array, which is the SiO ₂ pattern array 202 .

In the annular peak 202-3 of the combination of the circular truncated protrusion and the inverted conical depression, optionally, the diameter of the lower bottom surface of the circular truncated protrusion is 0.5-2.5 μm, the diameter of the upper bottom surface is 0.25-1.25 μm, and the height of the circular truncated cone is 0.5 μm -2.5μm, the included angle between the generatrix of the truncated truncated truncated cone and the diameter of the lower bottom surface is 66.4°, the inverted conical depression takes the upper bottom surface of the convex truncated truncated truncated truncated trough as the bottom surface of the cone, and the center of the lower bottom surface of the raised truncated truncated truncated surface is the apex. The annular peak 202-3 and The inverted conical pattern 202-1 etched on the sapphire substrate 201 forms an annular peak-inverted conical SiO ₂ pattern array 202 .

S105, growing an AlN nucleation layer 203 on the SiO ₂ pattern array. Specifically, the PECVD technique is used to sputter the AlN nucleation layer 203 on the SiO ₂ film. Optionally, the thickness of the AlN nucleation layer 203 is 14-24 nm.

S106 , growing an AlGaN layer 204 on the AlN nucleation layer 203 to form a composite nucleation layer. Specifically, the AlGaN layer 204 is sputtered on the AlN nucleation layer 203 by using PECVD technology. The thickness of the AlGaN composite nucleation layer 204 is 2.5-3.0 μm.

S107, sequentially epitaxially growing the u-GaN layer 205, the n-GaN layer 206, the superlattice 207, the multiple quantum well active layer 208 and the p-GaN layer 209 on the composite nucleation layer to form a complete light-emitting diode epitaxy structure.

The invention etches the sapphire substrate and the _SiO2 thin film to form a sapphire substrate with a special cone and a _SiO2 pattern array, forms an inclined interface between the _SiO2 and the GaN, improves the light extraction efficiency of the chip, and suppresses dislocations. extend. The AlN nucleation layer is sputtered on the _SiO2 pattern array, and AlGaN is grown on the AlN nucleation layer to form a composite nucleation layer, which reduces the dislocation density of the epitaxial layer and improves the external quantum efficiency of the chip.

The above embodiments are only used to illustrate the design ideas and features of the present invention, and the purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly, and the protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes or modifications made according to the principles and design ideas disclosed in the present invention fall within the protection scope of the present invention.

Claims (10)

1, kinds of LED chip with composite nucleation layer, which is characterized in that the chip comprises a sapphire substrate, on which SiO with specific shape is arranged₂Pattern array in SiO₂An AlN nucleating layer is arranged on the pattern array, an AlGaN layer grows on the AlN nucleating layer, the AlN nucleating layer and the AlGaN layer form a composite nucleating layer,a u-GaN layer, an n-GaN layer, a superlattice, a multi-quantum well active layer and a p-GaN layer are epitaxially grown on the composite nucleation layer in sequence;

the specific shape comprises an array formed by combining two part patterns, wherein part is an inverted cone pattern positioned on a sapphire substrate, and part is a cone bump positioned on the inverted cone pattern or an annular peak formed by combining a circular truncated cone bump and an inverted cone pit.

2. The light-emitting diode chip of claim 1, wherein the top of said inverted cone pattern is in the same plane with the top surface of said sapphire substrate, and said conical protrusions or annular peaks are located in said AlN nucleation layer.

3. The light-emitting diode chip as claimed in claim 1 or 2, characterized in that: the diameter of the bottom of the inverted cone is 0.5-2.5 mu m, the height of the cone is 1.0-5.0 mu m, the included angle between the generatrix of the cone and the bottom of the cone is 66.4 degrees, and the distance between the inverted cone pattern arrays is 0.5 mu m.

4. The light-emitting diode chip as claimed in claim 1 or 2, characterized in that: the diameter of the bottom surface of the conical bulge is 0.5-2.5 mu m, the height of the cone is 1.0-5.0 mu m, and the included angle between the conical generatrix and the diameter of the bottom surface is 66.4 degrees.

5. The light-emitting diode chip as claimed in claim 1 or 2, characterized in that: in the annular peak, the diameter of the lower bottom surface of the boss of the circular truncated cone is 0.5-2.5 microns, the diameter of the upper bottom surface of the boss of the circular truncated cone is 0.25-1.25 microns, the height of the circular truncated cone is 0.5-2.5 microns, and the included angle between the generatrix of the circular truncated cone and the diameter of the lower bottom surface is 66.4 degrees; the inverted cone is sunken, the upper bottom surface of the convex circular truncated cone is used as the bottom surface of the cone, and the center of the lower bottom surface of the convex circular truncated cone is used as the vertex.

6. The light-emitting diode chip of claim 1, wherein: the AlN layer has a thickness of 14-24 nm.

7. The light-emitting diode chip of claim 1, wherein: the thickness of the AlGaN layer is 2.5-3.0 μm.

8. The method for manufacturing a light-emitting diode chip as claimed in claim 1, wherein: the method comprises the following steps:

s101, providing a planar sapphire substrate;

s102, carrying out an etching process on the sapphire substrate, and forming a concave pit array of the inverted cone pattern on the sapphire substrate;

s103, growing SiO on the sapphire substrate₂So that the pit array of the reverse conical pattern is filled with SiO₂Forming an array of an inverted conical pattern and having layers of SiO on a sapphire substrate₂A film;

s104, subjecting the SiO₂Etching the film to leave a cone bulge or an annular peak formed by combining the cone bulge and the inverted cone depression on each inverted cone pattern to form SiO₂A graphics array;

s105 in the SiO₂ AlN nucleating layers are grown on the pattern array;

s106, growing an AlGaN layer on the AlN nucleating layer to form a composite nucleating layer;

s107, sequentially epitaxially growing a u-GaN layer, an n-GaN layer, a superlattice, a multi-quantum well active layer and a p-GaN layer on the composite nucleating layer.

9. The method of claim 8, wherein: the etching process is an ICP etching process.

10. The method of claim 8, wherein: the growth adopts a PECVD technology, and the epitaxial growth adopts an MOCVD technology.

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